drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 /*
  21  * Determine Rtt value.
  22  *
  23  * This should likely be either board or controller specific.
  24  *
  25  * Rtt(nominal) - DDR2:
  26  *      0 = Rtt disabled
  27  *      1 = 75 ohm
  28  *      2 = 150 ohm
  29  *      3 = 50 ohm
  30  * Rtt(nominal) - DDR3:
  31  *      0 = Rtt disabled
  32  *      1 = 60 ohm
  33  *      2 = 120 ohm
  34  *      3 = 40 ohm
  35  *      4 = 20 ohm
  36  *      5 = 30 ohm
  37  *
  38  * FIXME: Apparently 8641 needs a value of 2
  39  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  40  *
  41  * FIXME: There was some effort down this line earlier:
  42  *
  43  *      unsigned int i;
  44  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  45  *              if (popts->dimmslot[i].num_valid_cs
  46  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  47  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  48  *                      rtt = 2;
  49  *                      break;
  50  *              }
  51  *      }
  52  */
  53 static inline int fsl_ddr_get_rtt(void)
  54 {
  55         int rtt;
  56
  57 #if defined(CONFIG_SYS_FSL_DDR1)
  58         rtt = 0;
  59 #elif defined(CONFIG_SYS_FSL_DDR2)
  60         rtt = 3;
  61 #else
  62         rtt = 0;
  63 #endif
  64
  65         return rtt;
  66 }
  67
  68 #ifdef CONFIG_SYS_FSL_DDR4
  69 /*
  70  * compute CAS write latency according to DDR4 spec
  71  * CWL = 9 for <= 1600MT/s
  72  *       10 for <= 1866MT/s
  73  *       11 for <= 2133MT/s
  74  *       12 for <= 2400MT/s
  75  *       14 for <= 2667MT/s
  76  *       16 for <= 2933MT/s
  77  *       18 for higher
  78  */
  79 static inline unsigned int compute_cas_write_latency(
  80                                 const unsigned int ctrl_num)
  81 {
  82         unsigned int cwl;
  83         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  84         if (mclk_ps >= 1250)
  85                 cwl = 9;
  86         else if (mclk_ps >= 1070)
  87                 cwl = 10;
  88         else if (mclk_ps >= 935)
  89                 cwl = 11;
  90         else if (mclk_ps >= 833)
  91                 cwl = 12;
  92         else if (mclk_ps >= 750)
  93                 cwl = 14;
  94         else if (mclk_ps >= 681)
  95                 cwl = 16;
  96         else
  97                 cwl = 18;
  98
  99         return cwl;
 100 }
 101 #else
 102 /*
 103  * compute the CAS write latency according to DDR3 spec
 104  * CWL = 5 if tCK >= 2.5ns
 105  *       6 if 2.5ns > tCK >= 1.875ns
 106  *       7 if 1.875ns > tCK >= 1.5ns
 107  *       8 if 1.5ns > tCK >= 1.25ns
 108  *       9 if 1.25ns > tCK >= 1.07ns
 109  *       10 if 1.07ns > tCK >= 0.935ns
 110  *       11 if 0.935ns > tCK >= 0.833ns
 111  *       12 if 0.833ns > tCK >= 0.75ns
 112  */
 113 static inline unsigned int compute_cas_write_latency(
 114                                 const unsigned int ctrl_num)
 115 {
 116         unsigned int cwl;
 117         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 118
 119         if (mclk_ps >= 2500)
 120                 cwl = 5;
 121         else if (mclk_ps >= 1875)
 122                 cwl = 6;
 123         else if (mclk_ps >= 1500)
 124                 cwl = 7;
 125         else if (mclk_ps >= 1250)
 126                 cwl = 8;
 127         else if (mclk_ps >= 1070)
 128                 cwl = 9;
 129         else if (mclk_ps >= 935)
 130                 cwl = 10;
 131         else if (mclk_ps >= 833)
 132                 cwl = 11;
 133         else if (mclk_ps >= 750)
 134                 cwl = 12;
 135         else {
 136                 cwl = 12;
 137                 printf("Warning: CWL is out of range\n");
 138         }
 139         return cwl;
 140 }
 141 #endif
 142
 143 /* Chip Select Configuration (CSn_CONFIG) */
 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 145                                const memctl_options_t *popts,
 146                                const dimm_params_t *dimm_params)
 147 {
 148         unsigned int cs_n_en = 0; /* Chip Select enable */
 149         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 150         unsigned int intlv_ctl = 0; /* Interleaving control */
 151         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 152         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 153         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 154         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 155         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 156         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 157         int go_config = 0;
 158 #ifdef CONFIG_SYS_FSL_DDR4
 159         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 160 #else
 161         unsigned int n_banks_per_sdram_device;
 162 #endif
 163
 164         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 165         switch (i) {
 166         case 0:
 167                 if (dimm_params[dimm_number].n_ranks > 0) {
 168                         go_config = 1;
 169                         /* These fields only available in CS0_CONFIG */
 170                         if (!popts->memctl_interleaving)
 171                                 break;
 172                         switch (popts->memctl_interleaving_mode) {
 173                         case FSL_DDR_256B_INTERLEAVING:
 174                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 175                         case FSL_DDR_PAGE_INTERLEAVING:
 176                         case FSL_DDR_BANK_INTERLEAVING:
 177                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 178                                 intlv_en = popts->memctl_interleaving;
 179                                 intlv_ctl = popts->memctl_interleaving_mode;
 180                                 break;
 181                         default:
 182                                 break;
 183                         }
 184                 }
 185                 break;
 186         case 1:
 187                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 188                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 189                         go_config = 1;
 190                 break;
 191         case 2:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 193                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 3:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 198                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 199                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 200                         go_config = 1;
 201                 break;
 202         default:
 203                 break;
 204         }
 205         if (go_config) {
 206                 cs_n_en = 1;
 207                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 208                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 209                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 210 #ifdef CONFIG_SYS_FSL_DDR4
 211                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 212                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 213 #else
 214                 n_banks_per_sdram_device
 215                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 216                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 217 #endif
 218                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 219                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 220         }
 221         ddr->cs[i].config = (0
 222                 | ((cs_n_en & 0x1) << 31)
 223                 | ((intlv_en & 0x3) << 29)
 224                 | ((intlv_ctl & 0xf) << 24)
 225                 | ((ap_n_en & 0x1) << 23)
 226
 227                 /* XXX: some implementation only have 1 bit starting at left */
 228                 | ((odt_rd_cfg & 0x7) << 20)
 229
 230                 /* XXX: Some implementation only have 1 bit starting at left */
 231                 | ((odt_wr_cfg & 0x7) << 16)
 232
 233                 | ((ba_bits_cs_n & 0x3) << 14)
 234                 | ((row_bits_cs_n & 0x7) << 8)
 235 #ifdef CONFIG_SYS_FSL_DDR4
 236                 | ((bg_bits_cs_n & 0x3) << 4)
 237 #endif
 238                 | ((col_bits_cs_n & 0x7) << 0)
 239                 );
 240         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 241 }
 242
 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 244 /* FIXME: 8572 */
 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 246 {
 247         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 248
 249         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 250         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 251 }
 252
 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 254
 255 #if !defined(CONFIG_SYS_FSL_DDR1)
 256 /*
 257  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 258  * Return 1 if other two slots configuration. Return 0 if single slot.
 259  */
 260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 261 {
 262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 263         if (dimm_params[0].n_ranks == 4)
 264                 return 2;
 265 #endif
 266
 267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 268         if ((dimm_params[0].n_ranks == 2) &&
 269                 (dimm_params[1].n_ranks == 2))
 270                 return 2;
 271
 272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 273         if (dimm_params[0].n_ranks == 4)
 274                 return 2;
 275 #endif
 276
 277         if ((dimm_params[0].n_ranks != 0) &&
 278             (dimm_params[2].n_ranks != 0))
 279                 return 1;
 280 #endif
 281         return 0;
 282 }
 283
 284 /*
 285  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 286  *
 287  * Avoid writing for DDR I.  The new PQ38 DDR controller
 288  * dreams up non-zero default values to be backwards compatible.
 289  */
 290 static void set_timing_cfg_0(const unsigned int ctrl_num,
 291                                 fsl_ddr_cfg_regs_t *ddr,
 292                                 const memctl_options_t *popts,
 293                                 const dimm_params_t *dimm_params)
 294 {
 295         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 296         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 297         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 298         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 299         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 300
 301         /* Active powerdown exit timing (tXARD and tXARDS). */
 302         unsigned char act_pd_exit_mclk;
 303         /* Precharge powerdown exit timing (tXP). */
 304         unsigned char pre_pd_exit_mclk;
 305         /* ODT powerdown exit timing (tAXPD). */
 306         unsigned char taxpd_mclk = 0;
 307         /* Mode register set cycle time (tMRD). */
 308         unsigned char tmrd_mclk;
 309 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 310         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 311 #endif
 312
 313 #ifdef CONFIG_SYS_FSL_DDR4
 314         /* tXP=max(4nCK, 6ns) */
 315         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 316         unsigned int data_rate = get_ddr_freq(ctrl_num);
 317
 318         /* for faster clock, need more time for data setup */
 319         trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 320         twrt_mclk = 1;
 321         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 322         pre_pd_exit_mclk = act_pd_exit_mclk;
 323         /*
 324          * MRS_CYC = max(tMRD, tMOD)
 325          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 326          */
 327         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 328 #elif defined(CONFIG_SYS_FSL_DDR3)
 329         unsigned int data_rate = get_ddr_freq(ctrl_num);
 330         int txp;
 331         unsigned int ip_rev;
 332         int odt_overlap;
 333         /*
 334          * (tXARD and tXARDS). Empirical?
 335          * The DDR3 spec has not tXARD,
 336          * we use the tXP instead of it.
 337          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 338          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 339          * spec has not the tAXPD, we use
 340          * tAXPD=1, need design to confirm.
 341          */
 342         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 343
 344         ip_rev = fsl_ddr_get_version(ctrl_num);
 345         if (ip_rev >= 0x40700) {
 346                 /*
 347                  * MRS_CYC = max(tMRD, tMOD)
 348                  * tMRD = 4nCK (8nCK for RDIMM)
 349                  * tMOD = max(12nCK, 15ns)
 350                  */
 351                 tmrd_mclk = max((unsigned int)12,
 352                                 picos_to_mclk(ctrl_num, 15000));
 353         } else {
 354                 /*
 355                  * MRS_CYC = tMRD
 356                  * tMRD = 4nCK (8nCK for RDIMM)
 357                  */
 358                 if (popts->registered_dimm_en)
 359                         tmrd_mclk = 8;
 360                 else
 361                         tmrd_mclk = 4;
 362         }
 363
 364         /* set the turnaround time */
 365
 366         /*
 367          * for single quad-rank DIMM and two-slot DIMMs
 368          * to avoid ODT overlap
 369          */
 370         odt_overlap = avoid_odt_overlap(dimm_params);
 371         switch (odt_overlap) {
 372         case 2:
 373                 twwt_mclk = 2;
 374                 trrt_mclk = 1;
 375                 break;
 376         case 1:
 377                 twwt_mclk = 1;
 378                 trrt_mclk = 0;
 379                 break;
 380         default:
 381                 break;
 382         }
 383
 384         /* for faster clock, need more time for data setup */
 385         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 386
 387         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 388                 twrt_mclk = 1;
 389
 390         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 391                 act_pd_exit_mclk = 1;
 392                 pre_pd_exit_mclk = 1;
 393                 taxpd_mclk = 1;
 394         } else {
 395                 /* act_pd_exit_mclk = tXARD, see above */
 396                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 397                 /* Mode register MR0[A12] is '1' - fast exit */
 398                 pre_pd_exit_mclk = act_pd_exit_mclk;
 399                 taxpd_mclk = 1;
 400         }
 401 #else /* CONFIG_SYS_FSL_DDR2 */
 402         /*
 403          * (tXARD and tXARDS). Empirical?
 404          * tXARD = 2 for DDR2
 405          * tXP=2
 406          * tAXPD=8
 407          */
 408         act_pd_exit_mclk = 2;
 409         pre_pd_exit_mclk = 2;
 410         taxpd_mclk = 8;
 411         tmrd_mclk = 2;
 412 #endif
 413
 414         if (popts->trwt_override)
 415                 trwt_mclk = popts->trwt;
 416
 417         ddr->timing_cfg_0 = (0
 418                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 419                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 420                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 421                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 422                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 423                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 424                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 425                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 426                 );
 427         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 428 }
 429 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 430
 431 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 432 static void set_timing_cfg_3(const unsigned int ctrl_num,
 433                              fsl_ddr_cfg_regs_t *ddr,
 434                              const memctl_options_t *popts,
 435                              const common_timing_params_t *common_dimm,
 436                              unsigned int cas_latency,
 437                              unsigned int additive_latency)
 438 {
 439         /* Extended precharge to activate interval (tRP) */
 440         unsigned int ext_pretoact = 0;
 441         /* Extended Activate to precharge interval (tRAS) */
 442         unsigned int ext_acttopre = 0;
 443         /* Extended activate to read/write interval (tRCD) */
 444         unsigned int ext_acttorw = 0;
 445         /* Extended refresh recovery time (tRFC) */
 446         unsigned int ext_refrec;
 447         /* Extended MCAS latency from READ cmd */
 448         unsigned int ext_caslat = 0;
 449         /* Extended additive latency */
 450         unsigned int ext_add_lat = 0;
 451         /* Extended last data to precharge interval (tWR) */
 452         unsigned int ext_wrrec = 0;
 453         /* Control Adjust */
 454         unsigned int cntl_adj = 0;
 455
 456         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 457         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 458         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 459         ext_caslat = (2 * cas_latency - 1) >> 4;
 460         ext_add_lat = additive_latency >> 4;
 461 #ifdef CONFIG_SYS_FSL_DDR4
 462         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 463 #else
 464         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 465         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 466 #endif
 467         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 468                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 469
 470         ddr->timing_cfg_3 = (0
 471                 | ((ext_pretoact & 0x1) << 28)
 472                 | ((ext_acttopre & 0x3) << 24)
 473                 | ((ext_acttorw & 0x1) << 22)
 474                 | ((ext_refrec & 0x1F) << 16)
 475                 | ((ext_caslat & 0x3) << 12)
 476                 | ((ext_add_lat & 0x1) << 10)
 477                 | ((ext_wrrec & 0x1) << 8)
 478                 | ((cntl_adj & 0x7) << 0)
 479                 );
 480         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 481 }
 482
 483 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 484 static void set_timing_cfg_1(const unsigned int ctrl_num,
 485                              fsl_ddr_cfg_regs_t *ddr,
 486                              const memctl_options_t *popts,
 487                              const common_timing_params_t *common_dimm,
 488                              unsigned int cas_latency)
 489 {
 490         /* Precharge-to-activate interval (tRP) */
 491         unsigned char pretoact_mclk;
 492         /* Activate to precharge interval (tRAS) */
 493         unsigned char acttopre_mclk;
 494         /*  Activate to read/write interval (tRCD) */
 495         unsigned char acttorw_mclk;
 496         /* CASLAT */
 497         unsigned char caslat_ctrl;
 498         /*  Refresh recovery time (tRFC) ; trfc_low */
 499         unsigned char refrec_ctrl;
 500         /* Last data to precharge minimum interval (tWR) */
 501         unsigned char wrrec_mclk;
 502         /* Activate-to-activate interval (tRRD) */
 503         unsigned char acttoact_mclk;
 504         /* Last write data pair to read command issue interval (tWTR) */
 505         unsigned char wrtord_mclk;
 506 #ifdef CONFIG_SYS_FSL_DDR4
 507         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 508         static const u8 wrrec_table[] = {
 509                 10, 10, 10, 10, 10,
 510                 10, 10, 10, 10, 10,
 511                 12, 12, 14, 14, 16,
 512                 16, 18, 18, 20, 20,
 513                 24, 24, 24, 24};
 514 #else
 515         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 516         static const u8 wrrec_table[] = {
 517                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 518 #endif
 519
 520         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 521         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 522         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 523
 524         /*
 525          * Translate CAS Latency to a DDR controller field value:
 526          *
 527          *      CAS Lat DDR I   DDR II  Ctrl
 528          *      Clocks  SPD Bit SPD Bit Value
 529          *      ------- ------- ------- -----
 530          *      1.0     0               0001
 531          *      1.5     1               0010
 532          *      2.0     2       2       0011
 533          *      2.5     3               0100
 534          *      3.0     4       3       0101
 535          *      3.5     5               0110
 536          *      4.0             4       0111
 537          *      4.5                     1000
 538          *      5.0             5       1001
 539          */
 540 #if defined(CONFIG_SYS_FSL_DDR1)
 541         caslat_ctrl = (cas_latency + 1) & 0x07;
 542 #elif defined(CONFIG_SYS_FSL_DDR2)
 543         caslat_ctrl = 2 * cas_latency - 1;
 544 #else
 545         /*
 546          * if the CAS latency more than 8 cycle,
 547          * we need set extend bit for it at
 548          * TIMING_CFG_3[EXT_CASLAT]
 549          */
 550         if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 551                 caslat_ctrl = 2 * cas_latency - 1;
 552         else
 553                 caslat_ctrl = (cas_latency - 1) << 1;
 554 #endif
 555
 556 #ifdef CONFIG_SYS_FSL_DDR4
 557         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 558         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 559         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 560         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 561         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 562                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 563         else
 564                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 565 #else
 566         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 567         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 568         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 569         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 570         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 571                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 572         else
 573                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 574 #endif
 575         if (popts->otf_burst_chop_en)
 576                 wrrec_mclk += 2;
 577
 578         /*
 579          * JEDEC has min requirement for tRRD
 580          */
 581 #if defined(CONFIG_SYS_FSL_DDR3)
 582         if (acttoact_mclk < 4)
 583                 acttoact_mclk = 4;
 584 #endif
 585         /*
 586          * JEDEC has some min requirements for tWTR
 587          */
 588 #if defined(CONFIG_SYS_FSL_DDR2)
 589         if (wrtord_mclk < 2)
 590                 wrtord_mclk = 2;
 591 #elif defined(CONFIG_SYS_FSL_DDR3)
 592         if (wrtord_mclk < 4)
 593                 wrtord_mclk = 4;
 594 #endif
 595         if (popts->otf_burst_chop_en)
 596                 wrtord_mclk += 2;
 597
 598         ddr->timing_cfg_1 = (0
 599                 | ((pretoact_mclk & 0x0F) << 28)
 600                 | ((acttopre_mclk & 0x0F) << 24)
 601                 | ((acttorw_mclk & 0xF) << 20)
 602                 | ((caslat_ctrl & 0xF) << 16)
 603                 | ((refrec_ctrl & 0xF) << 12)
 604                 | ((wrrec_mclk & 0x0F) << 8)
 605                 | ((acttoact_mclk & 0x0F) << 4)
 606                 | ((wrtord_mclk & 0x0F) << 0)
 607                 );
 608         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 609 }
 610
 611 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 612 static void set_timing_cfg_2(const unsigned int ctrl_num,
 613                              fsl_ddr_cfg_regs_t *ddr,
 614                              const memctl_options_t *popts,
 615                              const common_timing_params_t *common_dimm,
 616                              unsigned int cas_latency,
 617                              unsigned int additive_latency)
 618 {
 619         /* Additive latency */
 620         unsigned char add_lat_mclk;
 621         /* CAS-to-preamble override */
 622         unsigned short cpo;
 623         /* Write latency */
 624         unsigned char wr_lat;
 625         /*  Read to precharge (tRTP) */
 626         unsigned char rd_to_pre;
 627         /* Write command to write data strobe timing adjustment */
 628         unsigned char wr_data_delay;
 629         /* Minimum CKE pulse width (tCKE) */
 630         unsigned char cke_pls;
 631         /* Window for four activates (tFAW) */
 632         unsigned short four_act;
 633 #ifdef CONFIG_SYS_FSL_DDR3
 634         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 635 #endif
 636
 637         /* FIXME add check that this must be less than acttorw_mclk */
 638         add_lat_mclk = additive_latency;
 639         cpo = popts->cpo_override;
 640
 641 #if defined(CONFIG_SYS_FSL_DDR1)
 642         /*
 643          * This is a lie.  It should really be 1, but if it is
 644          * set to 1, bits overlap into the old controller's
 645          * otherwise unused ACSM field.  If we leave it 0, then
 646          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 647          */
 648         wr_lat = 0;
 649 #elif defined(CONFIG_SYS_FSL_DDR2)
 650         wr_lat = cas_latency - 1;
 651 #else
 652         wr_lat = compute_cas_write_latency(ctrl_num);
 653 #endif
 654
 655 #ifdef CONFIG_SYS_FSL_DDR4
 656         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 657 #else
 658         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 659 #endif
 660         /*
 661          * JEDEC has some min requirements for tRTP
 662          */
 663 #if defined(CONFIG_SYS_FSL_DDR2)
 664         if (rd_to_pre  < 2)
 665                 rd_to_pre  = 2;
 666 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 667         if (rd_to_pre < 4)
 668                 rd_to_pre = 4;
 669 #endif
 670         if (popts->otf_burst_chop_en)
 671                 rd_to_pre += 2; /* according to UM */
 672
 673         wr_data_delay = popts->write_data_delay;
 674 #ifdef CONFIG_SYS_FSL_DDR4
 675         cpo = 0;
 676         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 677 #elif defined(CONFIG_SYS_FSL_DDR3)
 678         /*
 679          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 680          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 681          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 682          */
 683         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 684                                         (mclk_ps > 1245 ? 5625 : 5000)));
 685 #else
 686         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 687 #endif
 688         four_act = picos_to_mclk(ctrl_num,
 689                                  popts->tfaw_window_four_activates_ps);
 690
 691         ddr->timing_cfg_2 = (0
 692                 | ((add_lat_mclk & 0xf) << 28)
 693                 | ((cpo & 0x1f) << 23)
 694                 | ((wr_lat & 0xf) << 19)
 695                 | ((wr_lat & 0x10) << 14)
 696                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 697                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 698                 | ((cke_pls & 0x7) << 6)
 699                 | ((four_act & 0x3f) << 0)
 700                 );
 701         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 702 }
 703
 704 /* DDR SDRAM Register Control Word */
 705 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 706                                const memctl_options_t *popts,
 707                                const common_timing_params_t *common_dimm)
 708 {
 709         if (common_dimm->all_dimms_registered &&
 710             !common_dimm->all_dimms_unbuffered) {
 711                 if (popts->rcw_override) {
 712                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 713                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 714                 } else {
 715                         ddr->ddr_sdram_rcw_1 =
 716                                 common_dimm->rcw[0] << 28 | \
 717                                 common_dimm->rcw[1] << 24 | \
 718                                 common_dimm->rcw[2] << 20 | \
 719                                 common_dimm->rcw[3] << 16 | \
 720                                 common_dimm->rcw[4] << 12 | \
 721                                 common_dimm->rcw[5] << 8 | \
 722                                 common_dimm->rcw[6] << 4 | \
 723                                 common_dimm->rcw[7];
 724                         ddr->ddr_sdram_rcw_2 =
 725                                 common_dimm->rcw[8] << 28 | \
 726                                 common_dimm->rcw[9] << 24 | \
 727                                 common_dimm->rcw[10] << 20 | \
 728                                 common_dimm->rcw[11] << 16 | \
 729                                 common_dimm->rcw[12] << 12 | \
 730                                 common_dimm->rcw[13] << 8 | \
 731                                 common_dimm->rcw[14] << 4 | \
 732                                 common_dimm->rcw[15];
 733                 }
 734                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 735                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 736         }
 737 }
 738
 739 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 740 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 741                                const memctl_options_t *popts,
 742                                const common_timing_params_t *common_dimm)
 743 {
 744         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 745         unsigned int sren;              /* Self refresh enable (during sleep) */
 746         unsigned int ecc_en;            /* ECC enable. */
 747         unsigned int rd_en;             /* Registered DIMM enable */
 748         unsigned int sdram_type;        /* Type of SDRAM */
 749         unsigned int dyn_pwr;           /* Dynamic power management mode */
 750         unsigned int dbw;               /* DRAM dta bus width */
 751         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 752         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 753         unsigned int threet_en;         /* Enable 3T timing */
 754         unsigned int twot_en;           /* Enable 2T timing */
 755         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 756         unsigned int x32_en = 0;        /* x32 enable */
 757         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 758         unsigned int hse;               /* Global half strength override */
 759         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 760         unsigned int mem_halt = 0;      /* memory controller halt */
 761         unsigned int bi = 0;            /* Bypass initialization */
 762
 763         mem_en = 1;
 764         sren = popts->self_refresh_in_sleep;
 765         if (common_dimm->all_dimms_ecc_capable) {
 766                 /* Allow setting of ECC only if all DIMMs are ECC. */
 767                 ecc_en = popts->ecc_mode;
 768         } else {
 769                 ecc_en = 0;
 770         }
 771
 772         if (common_dimm->all_dimms_registered &&
 773             !common_dimm->all_dimms_unbuffered) {
 774                 rd_en = 1;
 775                 twot_en = 0;
 776         } else {
 777                 rd_en = 0;
 778                 twot_en = popts->twot_en;
 779         }
 780
 781         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 782
 783         dyn_pwr = popts->dynamic_power;
 784         dbw = popts->data_bus_width;
 785         /* 8-beat burst enable DDR-III case
 786          * we must clear it when use the on-the-fly mode,
 787          * must set it when use the 32-bits bus mode.
 788          */
 789         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 790             (sdram_type == SDRAM_TYPE_DDR4)) {
 791                 if (popts->burst_length == DDR_BL8)
 792                         eight_be = 1;
 793                 if (popts->burst_length == DDR_OTF)
 794                         eight_be = 0;
 795                 if (dbw == 0x1)
 796                         eight_be = 1;
 797         }
 798
 799         threet_en = popts->threet_en;
 800         ba_intlv_ctl = popts->ba_intlv_ctl;
 801         hse = popts->half_strength_driver_enable;
 802
 803         /* set when ddr bus width < 64 */
 804         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 805
 806         ddr->ddr_sdram_cfg = (0
 807                         | ((mem_en & 0x1) << 31)
 808                         | ((sren & 0x1) << 30)
 809                         | ((ecc_en & 0x1) << 29)
 810                         | ((rd_en & 0x1) << 28)
 811                         | ((sdram_type & 0x7) << 24)
 812                         | ((dyn_pwr & 0x1) << 21)
 813                         | ((dbw & 0x3) << 19)
 814                         | ((eight_be & 0x1) << 18)
 815                         | ((ncap & 0x1) << 17)
 816                         | ((threet_en & 0x1) << 16)
 817                         | ((twot_en & 0x1) << 15)
 818                         | ((ba_intlv_ctl & 0x7F) << 8)
 819                         | ((x32_en & 0x1) << 5)
 820                         | ((pchb8 & 0x1) << 4)
 821                         | ((hse & 0x1) << 3)
 822                         | ((acc_ecc_en & 0x1) << 2)
 823                         | ((mem_halt & 0x1) << 1)
 824                         | ((bi & 0x1) << 0)
 825                         );
 826         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 827 }
 828
 829 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 830 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 831                                fsl_ddr_cfg_regs_t *ddr,
 832                                const memctl_options_t *popts,
 833                                const unsigned int unq_mrs_en)
 834 {
 835         unsigned int frc_sr = 0;        /* Force self refresh */
 836         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 837         unsigned int odt_cfg = 0;       /* ODT configuration */
 838         unsigned int num_pr;            /* Number of posted refreshes */
 839         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 840         unsigned int x4_en = 0;         /* x4 DRAM enable */
 841         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 842         unsigned int ap_en;             /* Address Parity Enable */
 843         unsigned int d_init;            /* DRAM data initialization */
 844         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 845         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 846         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 847         int i;
 848 #ifndef CONFIG_SYS_FSL_DDR4
 849         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 850         unsigned int dqs_cfg;           /* DQS configuration */
 851
 852         dqs_cfg = popts->dqs_config;
 853 #endif
 854         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 855                 if (popts->cs_local_opts[i].odt_rd_cfg
 856                         || popts->cs_local_opts[i].odt_wr_cfg) {
 857                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 858                         break;
 859                 }
 860         }
 861
 862         num_pr = 1;     /* Make this configurable */
 863
 864         /*
 865          * 8572 manual says
 866          *     {TIMING_CFG_1[PRETOACT]
 867          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 868          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 869          *      << DDR_SDRAM_INTERVAL[REFINT]
 870          */
 871 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 872         obc_cfg = popts->otf_burst_chop_en;
 873 #else
 874         obc_cfg = 0;
 875 #endif
 876
 877 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 878         slow = get_ddr_freq(ctrl_num) < 1249000000;
 879 #endif
 880
 881         if (popts->registered_dimm_en) {
 882                 rcw_en = 1;
 883                 ap_en = popts->ap_en;
 884         } else {
 885                 ap_en = 0;
 886         }
 887
 888         x4_en = popts->x4_en ? 1 : 0;
 889
 890 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 891         /* Use the DDR controller to auto initialize memory. */
 892         d_init = popts->ecc_init_using_memctl;
 893         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 894         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 895 #else
 896         /* Memory will be initialized via DMA, or not at all. */
 897         d_init = 0;
 898 #endif
 899
 900 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 901         md_en = popts->mirrored_dimm;
 902 #endif
 903         qd_en = popts->quad_rank_present ? 1 : 0;
 904         ddr->ddr_sdram_cfg_2 = (0
 905                 | ((frc_sr & 0x1) << 31)
 906                 | ((sr_ie & 0x1) << 30)
 907 #ifndef CONFIG_SYS_FSL_DDR4
 908                 | ((dll_rst_dis & 0x1) << 29)
 909                 | ((dqs_cfg & 0x3) << 26)
 910 #endif
 911                 | ((odt_cfg & 0x3) << 21)
 912                 | ((num_pr & 0xf) << 12)
 913                 | ((slow & 1) << 11)
 914                 | (x4_en << 10)
 915                 | (qd_en << 9)
 916                 | (unq_mrs_en << 8)
 917                 | ((obc_cfg & 0x1) << 6)
 918                 | ((ap_en & 0x1) << 5)
 919                 | ((d_init & 0x1) << 4)
 920                 | ((rcw_en & 0x1) << 2)
 921                 | ((md_en & 0x1) << 0)
 922                 );
 923         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 924 }
 925
 926 #ifdef CONFIG_SYS_FSL_DDR4
 927 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 928 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 929                                 fsl_ddr_cfg_regs_t *ddr,
 930                                 const memctl_options_t *popts,
 931                                 const common_timing_params_t *common_dimm,
 932                                 const unsigned int unq_mrs_en)
 933 {
 934         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 935         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 936         int i;
 937         unsigned int wr_crc = 0;        /* Disable */
 938         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 939         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 940         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 941         unsigned int mpr = 0;   /* serial */
 942         unsigned int wc_lat;
 943         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 944
 945         if (popts->rtt_override)
 946                 rtt_wr = popts->rtt_wr_override_value;
 947         else
 948                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 949
 950         if (common_dimm->extended_op_srt)
 951                 srt = common_dimm->extended_op_srt;
 952
 953         esdmode2 = (0
 954                 | ((wr_crc & 0x1) << 12)
 955                 | ((rtt_wr & 0x3) << 9)
 956                 | ((srt & 0x3) << 6)
 957                 | ((cwl & 0x7) << 3));
 958
 959         if (mclk_ps >= 1250)
 960                 wc_lat = 0;
 961         else if (mclk_ps >= 833)
 962                 wc_lat = 1;
 963         else
 964                 wc_lat = 2;
 965
 966         esdmode3 = (0
 967                 | ((mpr & 0x3) << 11)
 968                 | ((wc_lat & 0x3) << 9));
 969
 970         ddr->ddr_sdram_mode_2 = (0
 971                                  | ((esdmode2 & 0xFFFF) << 16)
 972                                  | ((esdmode3 & 0xFFFF) << 0)
 973                                  );
 974         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 975
 976         if (unq_mrs_en) {       /* unique mode registers are supported */
 977                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 978                         if (popts->rtt_override)
 979                                 rtt_wr = popts->rtt_wr_override_value;
 980                         else
 981                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 982
 983                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 984                         esdmode2 |= (rtt_wr & 0x3) << 9;
 985                         switch (i) {
 986                         case 1:
 987                                 ddr->ddr_sdram_mode_4 = (0
 988                                         | ((esdmode2 & 0xFFFF) << 16)
 989                                         | ((esdmode3 & 0xFFFF) << 0)
 990                                         );
 991                                 break;
 992                         case 2:
 993                                 ddr->ddr_sdram_mode_6 = (0
 994                                         | ((esdmode2 & 0xFFFF) << 16)
 995                                         | ((esdmode3 & 0xFFFF) << 0)
 996                                         );
 997                                 break;
 998                         case 3:
 999                                 ddr->ddr_sdram_mode_8 = (0
1000                                         | ((esdmode2 & 0xFFFF) << 16)
1001                                         | ((esdmode3 & 0xFFFF) << 0)
1002                                         );
1003                                 break;
1004                         }
1005                 }
1006                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1007                       ddr->ddr_sdram_mode_4);
1008                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1009                       ddr->ddr_sdram_mode_6);
1010                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1011                       ddr->ddr_sdram_mode_8);
1012         }
1013 }
1014 #elif defined(CONFIG_SYS_FSL_DDR3)
1015 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1016 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1017                                 fsl_ddr_cfg_regs_t *ddr,
1018                                 const memctl_options_t *popts,
1019                                 const common_timing_params_t *common_dimm,
1020                                 const unsigned int unq_mrs_en)
1021 {
1022         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1023         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1024         int i;
1025         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1026         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1027         unsigned int asr = 0;   /* auto self-refresh disable */
1028         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1029         unsigned int pasr = 0;  /* partial array self refresh disable */
1030
1031         if (popts->rtt_override)
1032                 rtt_wr = popts->rtt_wr_override_value;
1033         else
1034                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1035
1036         if (common_dimm->extended_op_srt)
1037                 srt = common_dimm->extended_op_srt;
1038
1039         esdmode2 = (0
1040                 | ((rtt_wr & 0x3) << 9)
1041                 | ((srt & 0x1) << 7)
1042                 | ((asr & 0x1) << 6)
1043                 | ((cwl & 0x7) << 3)
1044                 | ((pasr & 0x7) << 0));
1045         ddr->ddr_sdram_mode_2 = (0
1046                                  | ((esdmode2 & 0xFFFF) << 16)
1047                                  | ((esdmode3 & 0xFFFF) << 0)
1048                                  );
1049         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1050
1051         if (unq_mrs_en) {       /* unique mode registers are supported */
1052                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1053                         if (popts->rtt_override)
1054                                 rtt_wr = popts->rtt_wr_override_value;
1055                         else
1056                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1057
1058                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1059                         esdmode2 |= (rtt_wr & 0x3) << 9;
1060                         switch (i) {
1061                         case 1:
1062                                 ddr->ddr_sdram_mode_4 = (0
1063                                         | ((esdmode2 & 0xFFFF) << 16)
1064                                         | ((esdmode3 & 0xFFFF) << 0)
1065                                         );
1066                                 break;
1067                         case 2:
1068                                 ddr->ddr_sdram_mode_6 = (0
1069                                         | ((esdmode2 & 0xFFFF) << 16)
1070                                         | ((esdmode3 & 0xFFFF) << 0)
1071                                         );
1072                                 break;
1073                         case 3:
1074                                 ddr->ddr_sdram_mode_8 = (0
1075                                         | ((esdmode2 & 0xFFFF) << 16)
1076                                         | ((esdmode3 & 0xFFFF) << 0)
1077                                         );
1078                                 break;
1079                         }
1080                 }
1081                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1082                         ddr->ddr_sdram_mode_4);
1083                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1084                         ddr->ddr_sdram_mode_6);
1085                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1086                         ddr->ddr_sdram_mode_8);
1087         }
1088 }
1089
1090 #else /* for DDR2 and DDR1 */
1091 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1092 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1093                                 fsl_ddr_cfg_regs_t *ddr,
1094                                 const memctl_options_t *popts,
1095                                 const common_timing_params_t *common_dimm,
1096                                 const unsigned int unq_mrs_en)
1097 {
1098         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1099         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1100
1101         ddr->ddr_sdram_mode_2 = (0
1102                                  | ((esdmode2 & 0xFFFF) << 16)
1103                                  | ((esdmode3 & 0xFFFF) << 0)
1104                                  );
1105         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1106 }
1107 #endif
1108
1109 #ifdef CONFIG_SYS_FSL_DDR4
1110 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1111 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1112                                 const memctl_options_t *popts,
1113                                 const common_timing_params_t *common_dimm,
1114                                 const unsigned int unq_mrs_en)
1115 {
1116         int i;
1117         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1118         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1119         int rtt_park = 0;
1120
1121         if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1122                 esdmode5 = 0x00000500;  /* Data mask enable, RTT_PARK CS0 */
1123                 rtt_park = 1;
1124         } else {
1125                 esdmode5 = 0x00000400;  /* Data mask enabled */
1126         }
1127
1128         ddr->ddr_sdram_mode_9 = (0
1129                                  | ((esdmode4 & 0xffff) << 16)
1130                                  | ((esdmode5 & 0xffff) << 0)
1131                                 );
1132
1133         /* only mode_9 use 0x500, others use 0x400 */
1134
1135         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1136         if (unq_mrs_en) {       /* unique mode registers are supported */
1137                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1138                         if (!rtt_park &&
1139                             (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1140                                 esdmode5 |= 0x00000500; /* RTT_PARK */
1141                                 rtt_park = 1;
1142                         } else {
1143                                 esdmode5 = 0x00000400;
1144                         }
1145                         switch (i) {
1146                         case 1:
1147                                 ddr->ddr_sdram_mode_11 = (0
1148                                         | ((esdmode4 & 0xFFFF) << 16)
1149                                         | ((esdmode5 & 0xFFFF) << 0)
1150                                         );
1151                                 break;
1152                         case 2:
1153                                 ddr->ddr_sdram_mode_13 = (0
1154                                         | ((esdmode4 & 0xFFFF) << 16)
1155                                         | ((esdmode5 & 0xFFFF) << 0)
1156                                         );
1157                                 break;
1158                         case 3:
1159                                 ddr->ddr_sdram_mode_15 = (0
1160                                         | ((esdmode4 & 0xFFFF) << 16)
1161                                         | ((esdmode5 & 0xFFFF) << 0)
1162                                         );
1163                                 break;
1164                         }
1165                 }
1166                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1167                       ddr->ddr_sdram_mode_11);
1168                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1169                       ddr->ddr_sdram_mode_13);
1170                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1171                       ddr->ddr_sdram_mode_15);
1172         }
1173 }
1174
1175 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1176 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1177                                 fsl_ddr_cfg_regs_t *ddr,
1178                                 const memctl_options_t *popts,
1179                                 const common_timing_params_t *common_dimm,
1180                                 const unsigned int unq_mrs_en)
1181 {
1182         int i;
1183         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1184         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1185         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1186
1187         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1188
1189         ddr->ddr_sdram_mode_10 = (0
1190                                  | ((esdmode6 & 0xffff) << 16)
1191                                  | ((esdmode7 & 0xffff) << 0)
1192                                 );
1193         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1194         if (unq_mrs_en) {       /* unique mode registers are supported */
1195                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1196                         switch (i) {
1197                         case 1:
1198                                 ddr->ddr_sdram_mode_12 = (0
1199                                         | ((esdmode6 & 0xFFFF) << 16)
1200                                         | ((esdmode7 & 0xFFFF) << 0)
1201                                         );
1202                                 break;
1203                         case 2:
1204                                 ddr->ddr_sdram_mode_14 = (0
1205                                         | ((esdmode6 & 0xFFFF) << 16)
1206                                         | ((esdmode7 & 0xFFFF) << 0)
1207                                         );
1208                                 break;
1209                         case 3:
1210                                 ddr->ddr_sdram_mode_16 = (0
1211                                         | ((esdmode6 & 0xFFFF) << 16)
1212                                         | ((esdmode7 & 0xFFFF) << 0)
1213                                         );
1214                                 break;
1215                         }
1216                 }
1217                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1218                       ddr->ddr_sdram_mode_12);
1219                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1220                       ddr->ddr_sdram_mode_14);
1221                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1222                       ddr->ddr_sdram_mode_16);
1223         }
1224 }
1225
1226 #endif
1227
1228 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1229 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1230                                 fsl_ddr_cfg_regs_t *ddr,
1231                                 const memctl_options_t *popts,
1232                                 const common_timing_params_t *common_dimm)
1233 {
1234         unsigned int refint;    /* Refresh interval */
1235         unsigned int bstopre;   /* Precharge interval */
1236
1237         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1238
1239         bstopre = popts->bstopre;
1240
1241         /* refint field used 0x3FFF in earlier controllers */
1242         ddr->ddr_sdram_interval = (0
1243                                    | ((refint & 0xFFFF) << 16)
1244                                    | ((bstopre & 0x3FFF) << 0)
1245                                    );
1246         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1247 }
1248
1249 #ifdef CONFIG_SYS_FSL_DDR4
1250 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1251 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1252                                fsl_ddr_cfg_regs_t *ddr,
1253                                const memctl_options_t *popts,
1254                                const common_timing_params_t *common_dimm,
1255                                unsigned int cas_latency,
1256                                unsigned int additive_latency,
1257                                const unsigned int unq_mrs_en)
1258 {
1259         int i;
1260         unsigned short esdmode;         /* Extended SDRAM mode */
1261         unsigned short sdmode;          /* SDRAM mode */
1262
1263         /* Mode Register - MR1 */
1264         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1265         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1266         unsigned int rtt;
1267         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1268         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1269         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1270         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1271                                                        0=Disable (Test/Debug) */
1272
1273         /* Mode Register - MR0 */
1274         unsigned int wr = 0;    /* Write Recovery */
1275         unsigned int dll_rst;   /* DLL Reset */
1276         unsigned int mode;      /* Normal=0 or Test=1 */
1277         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1278         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1279         unsigned int bt;
1280         unsigned int bl;        /* BL: Burst Length */
1281
1282         unsigned int wr_mclk;
1283         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1284         static const u8 wr_table[] = {
1285                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1286         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1287         static const u8 cas_latency_table[] = {
1288                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1289                 9, 9, 10, 10, 11, 11};
1290
1291         if (popts->rtt_override)
1292                 rtt = popts->rtt_override_value;
1293         else
1294                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1295
1296         if (additive_latency == (cas_latency - 1))
1297                 al = 1;
1298         if (additive_latency == (cas_latency - 2))
1299                 al = 2;
1300
1301         if (popts->quad_rank_present)
1302                 dic = 1;        /* output driver impedance 240/7 ohm */
1303
1304         /*
1305          * The esdmode value will also be used for writing
1306          * MR1 during write leveling for DDR3, although the
1307          * bits specifically related to the write leveling
1308          * scheme will be handled automatically by the DDR
1309          * controller. so we set the wrlvl_en = 0 here.
1310          */
1311         esdmode = (0
1312                 | ((qoff & 0x1) << 12)
1313                 | ((tdqs_en & 0x1) << 11)
1314                 | ((rtt & 0x7) << 8)
1315                 | ((wrlvl_en & 0x1) << 7)
1316                 | ((al & 0x3) << 3)
1317                 | ((dic & 0x3) << 1)   /* DIC field is split */
1318                 | ((dll_en & 0x1) << 0)
1319                 );
1320
1321         /*
1322          * DLL control for precharge PD
1323          * 0=slow exit DLL off (tXPDLL)
1324          * 1=fast exit DLL on (tXP)
1325          */
1326
1327         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1328         if (wr_mclk <= 24) {
1329                 wr = wr_table[wr_mclk - 10];
1330         } else {
1331                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1332                        wr_mclk);
1333         }
1334
1335         dll_rst = 0;    /* dll no reset */
1336         mode = 0;       /* normal mode */
1337
1338         /* look up table to get the cas latency bits */
1339         if (cas_latency >= 9 && cas_latency <= 24)
1340                 caslat = cas_latency_table[cas_latency - 9];
1341         else
1342                 printf("Error: unsupported cas latency for mode register\n");
1343
1344         bt = 0; /* Nibble sequential */
1345
1346         switch (popts->burst_length) {
1347         case DDR_BL8:
1348                 bl = 0;
1349                 break;
1350         case DDR_OTF:
1351                 bl = 1;
1352                 break;
1353         case DDR_BC4:
1354                 bl = 2;
1355                 break;
1356         default:
1357                 printf("Error: invalid burst length of %u specified. ",
1358                        popts->burst_length);
1359                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1360                 bl = 1;
1361                 break;
1362         }
1363
1364         sdmode = (0
1365                   | ((wr & 0x7) << 9)
1366                   | ((dll_rst & 0x1) << 8)
1367                   | ((mode & 0x1) << 7)
1368                   | (((caslat >> 1) & 0x7) << 4)
1369                   | ((bt & 0x1) << 3)
1370                   | ((caslat & 1) << 2)
1371                   | ((bl & 0x3) << 0)
1372                   );
1373
1374         ddr->ddr_sdram_mode = (0
1375                                | ((esdmode & 0xFFFF) << 16)
1376                                | ((sdmode & 0xFFFF) << 0)
1377                                );
1378
1379         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1380
1381         if (unq_mrs_en) {       /* unique mode registers are supported */
1382                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1383                         if (popts->rtt_override)
1384                                 rtt = popts->rtt_override_value;
1385                         else
1386                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1387
1388                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1389                         esdmode |= (rtt & 0x7) << 8;
1390                         switch (i) {
1391                         case 1:
1392                                 ddr->ddr_sdram_mode_3 = (0
1393                                        | ((esdmode & 0xFFFF) << 16)
1394                                        | ((sdmode & 0xFFFF) << 0)
1395                                        );
1396                                 break;
1397                         case 2:
1398                                 ddr->ddr_sdram_mode_5 = (0
1399                                        | ((esdmode & 0xFFFF) << 16)
1400                                        | ((sdmode & 0xFFFF) << 0)
1401                                        );
1402                                 break;
1403                         case 3:
1404                                 ddr->ddr_sdram_mode_7 = (0
1405                                        | ((esdmode & 0xFFFF) << 16)
1406                                        | ((sdmode & 0xFFFF) << 0)
1407                                        );
1408                                 break;
1409                         }
1410                 }
1411                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1412                       ddr->ddr_sdram_mode_3);
1413                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1414                       ddr->ddr_sdram_mode_5);
1415                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1416                       ddr->ddr_sdram_mode_5);
1417         }
1418 }
1419
1420 #elif defined(CONFIG_SYS_FSL_DDR3)
1421 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1422 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1423                                fsl_ddr_cfg_regs_t *ddr,
1424                                const memctl_options_t *popts,
1425                                const common_timing_params_t *common_dimm,
1426                                unsigned int cas_latency,
1427                                unsigned int additive_latency,
1428                                const unsigned int unq_mrs_en)
1429 {
1430         int i;
1431         unsigned short esdmode;         /* Extended SDRAM mode */
1432         unsigned short sdmode;          /* SDRAM mode */
1433
1434         /* Mode Register - MR1 */
1435         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1436         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1437         unsigned int rtt;
1438         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1439         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1440         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1441         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1442                                                        1=Disable (Test/Debug) */
1443
1444         /* Mode Register - MR0 */
1445         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1446         unsigned int wr = 0;    /* Write Recovery */
1447         unsigned int dll_rst;   /* DLL Reset */
1448         unsigned int mode;      /* Normal=0 or Test=1 */
1449         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1450         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1451         unsigned int bt;
1452         unsigned int bl;        /* BL: Burst Length */
1453
1454         unsigned int wr_mclk;
1455         /*
1456          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1457          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1458          * for this table
1459          */
1460         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1461
1462         if (popts->rtt_override)
1463                 rtt = popts->rtt_override_value;
1464         else
1465                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1466
1467         if (additive_latency == (cas_latency - 1))
1468                 al = 1;
1469         if (additive_latency == (cas_latency - 2))
1470                 al = 2;
1471
1472         if (popts->quad_rank_present)
1473                 dic = 1;        /* output driver impedance 240/7 ohm */
1474
1475         /*
1476          * The esdmode value will also be used for writing
1477          * MR1 during write leveling for DDR3, although the
1478          * bits specifically related to the write leveling
1479          * scheme will be handled automatically by the DDR
1480          * controller. so we set the wrlvl_en = 0 here.
1481          */
1482         esdmode = (0
1483                 | ((qoff & 0x1) << 12)
1484                 | ((tdqs_en & 0x1) << 11)
1485                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1486                 | ((wrlvl_en & 0x1) << 7)
1487                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1488                 | ((dic & 0x2) << 4)   /* DIC field is split */
1489                 | ((al & 0x3) << 3)
1490                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1491                 | ((dic & 0x1) << 1)   /* DIC field is split */
1492                 | ((dll_en & 0x1) << 0)
1493                 );
1494
1495         /*
1496          * DLL control for precharge PD
1497          * 0=slow exit DLL off (tXPDLL)
1498          * 1=fast exit DLL on (tXP)
1499          */
1500         dll_on = 1;
1501
1502         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1503         if (wr_mclk <= 16) {
1504                 wr = wr_table[wr_mclk - 5];
1505         } else {
1506                 printf("Error: unsupported write recovery for mode register "
1507                        "wr_mclk = %d\n", wr_mclk);
1508         }
1509
1510         dll_rst = 0;    /* dll no reset */
1511         mode = 0;       /* normal mode */
1512
1513         /* look up table to get the cas latency bits */
1514         if (cas_latency >= 5 && cas_latency <= 16) {
1515                 unsigned char cas_latency_table[] = {
1516                         0x2,    /* 5 clocks */
1517                         0x4,    /* 6 clocks */
1518                         0x6,    /* 7 clocks */
1519                         0x8,    /* 8 clocks */
1520                         0xa,    /* 9 clocks */
1521                         0xc,    /* 10 clocks */
1522                         0xe,    /* 11 clocks */
1523                         0x1,    /* 12 clocks */
1524                         0x3,    /* 13 clocks */
1525                         0x5,    /* 14 clocks */
1526                         0x7,    /* 15 clocks */
1527                         0x9,    /* 16 clocks */
1528                 };
1529                 caslat = cas_latency_table[cas_latency - 5];
1530         } else {
1531                 printf("Error: unsupported cas latency for mode register\n");
1532         }
1533
1534         bt = 0; /* Nibble sequential */
1535
1536         switch (popts->burst_length) {
1537         case DDR_BL8:
1538                 bl = 0;
1539                 break;
1540         case DDR_OTF:
1541                 bl = 1;
1542                 break;
1543         case DDR_BC4:
1544                 bl = 2;
1545                 break;
1546         default:
1547                 printf("Error: invalid burst length of %u specified. "
1548                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1549                         popts->burst_length);
1550                 bl = 1;
1551                 break;
1552         }
1553
1554         sdmode = (0
1555                   | ((dll_on & 0x1) << 12)
1556                   | ((wr & 0x7) << 9)
1557                   | ((dll_rst & 0x1) << 8)
1558                   | ((mode & 0x1) << 7)
1559                   | (((caslat >> 1) & 0x7) << 4)
1560                   | ((bt & 0x1) << 3)
1561                   | ((caslat & 1) << 2)
1562                   | ((bl & 0x3) << 0)
1563                   );
1564
1565         ddr->ddr_sdram_mode = (0
1566                                | ((esdmode & 0xFFFF) << 16)
1567                                | ((sdmode & 0xFFFF) << 0)
1568                                );
1569
1570         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1571
1572         if (unq_mrs_en) {       /* unique mode registers are supported */
1573                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1574                         if (popts->rtt_override)
1575                                 rtt = popts->rtt_override_value;
1576                         else
1577                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1578
1579                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1580                         esdmode |= (0
1581                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1582                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1583                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1584                                 );
1585                         switch (i) {
1586                         case 1:
1587                                 ddr->ddr_sdram_mode_3 = (0
1588                                        | ((esdmode & 0xFFFF) << 16)
1589                                        | ((sdmode & 0xFFFF) << 0)
1590                                        );
1591                                 break;
1592                         case 2:
1593                                 ddr->ddr_sdram_mode_5 = (0
1594                                        | ((esdmode & 0xFFFF) << 16)
1595                                        | ((sdmode & 0xFFFF) << 0)
1596                                        );
1597                                 break;
1598                         case 3:
1599                                 ddr->ddr_sdram_mode_7 = (0
1600                                        | ((esdmode & 0xFFFF) << 16)
1601                                        | ((sdmode & 0xFFFF) << 0)
1602                                        );
1603                                 break;
1604                         }
1605                 }
1606                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1607                         ddr->ddr_sdram_mode_3);
1608                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1609                         ddr->ddr_sdram_mode_5);
1610                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1611                         ddr->ddr_sdram_mode_5);
1612         }
1613 }
1614
1615 #else /* !CONFIG_SYS_FSL_DDR3 */
1616
1617 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1618 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1619                                fsl_ddr_cfg_regs_t *ddr,
1620                                const memctl_options_t *popts,
1621                                const common_timing_params_t *common_dimm,
1622                                unsigned int cas_latency,
1623                                unsigned int additive_latency,
1624                                const unsigned int unq_mrs_en)
1625 {
1626         unsigned short esdmode;         /* Extended SDRAM mode */
1627         unsigned short sdmode;          /* SDRAM mode */
1628
1629         /*
1630          * FIXME: This ought to be pre-calculated in a
1631          * technology-specific routine,
1632          * e.g. compute_DDR2_mode_register(), and then the
1633          * sdmode and esdmode passed in as part of common_dimm.
1634          */
1635
1636         /* Extended Mode Register */
1637         unsigned int mrs = 0;           /* Mode Register Set */
1638         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1639         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1640         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1641         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1642                                            0x7=OCD default state */
1643         unsigned int rtt;
1644         unsigned int al;                /* Posted CAS# additive latency (AL) */
1645         unsigned int ods = 0;           /* Output Drive Strength:
1646                                                 0 = Full strength (18ohm)
1647                                                 1 = Reduced strength (4ohm) */
1648         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1649                                                        1=Disable (Test/Debug) */
1650
1651         /* Mode Register (MR) */
1652         unsigned int mr;        /* Mode Register Definition */
1653         unsigned int pd;        /* Power-Down Mode */
1654         unsigned int wr;        /* Write Recovery */
1655         unsigned int dll_res;   /* DLL Reset */
1656         unsigned int mode;      /* Normal=0 or Test=1 */
1657         unsigned int caslat = 0;/* CAS# latency */
1658         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1659         unsigned int bt;
1660         unsigned int bl;        /* BL: Burst Length */
1661
1662         dqs_en = !popts->dqs_config;
1663         rtt = fsl_ddr_get_rtt();
1664
1665         al = additive_latency;
1666
1667         esdmode = (0
1668                 | ((mrs & 0x3) << 14)
1669                 | ((outputs & 0x1) << 12)
1670                 | ((rdqs_en & 0x1) << 11)
1671                 | ((dqs_en & 0x1) << 10)
1672                 | ((ocd & 0x7) << 7)
1673                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1674                 | ((al & 0x7) << 3)
1675                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1676                 | ((ods & 0x1) << 1)
1677                 | ((dll_en & 0x1) << 0)
1678                 );
1679
1680         mr = 0;          /* FIXME: CHECKME */
1681
1682         /*
1683          * 0 = Fast Exit (Normal)
1684          * 1 = Slow Exit (Low Power)
1685          */
1686         pd = 0;
1687
1688 #if defined(CONFIG_SYS_FSL_DDR1)
1689         wr = 0;       /* Historical */
1690 #elif defined(CONFIG_SYS_FSL_DDR2)
1691         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1692 #endif
1693         dll_res = 0;
1694         mode = 0;
1695
1696 #if defined(CONFIG_SYS_FSL_DDR1)
1697         if (1 <= cas_latency && cas_latency <= 4) {
1698                 unsigned char mode_caslat_table[4] = {
1699                         0x5,    /* 1.5 clocks */
1700                         0x2,    /* 2.0 clocks */
1701                         0x6,    /* 2.5 clocks */
1702                         0x3     /* 3.0 clocks */
1703                 };
1704                 caslat = mode_caslat_table[cas_latency - 1];
1705         } else {
1706                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1707         }
1708 #elif defined(CONFIG_SYS_FSL_DDR2)
1709         caslat = cas_latency;
1710 #endif
1711         bt = 0;
1712
1713         switch (popts->burst_length) {
1714         case DDR_BL4:
1715                 bl = 2;
1716                 break;
1717         case DDR_BL8:
1718                 bl = 3;
1719                 break;
1720         default:
1721                 printf("Error: invalid burst length of %u specified. "
1722                         " Defaulting to 4 beats.\n",
1723                         popts->burst_length);
1724                 bl = 2;
1725                 break;
1726         }
1727
1728         sdmode = (0
1729                   | ((mr & 0x3) << 14)
1730                   | ((pd & 0x1) << 12)
1731                   | ((wr & 0x7) << 9)
1732                   | ((dll_res & 0x1) << 8)
1733                   | ((mode & 0x1) << 7)
1734                   | ((caslat & 0x7) << 4)
1735                   | ((bt & 0x1) << 3)
1736                   | ((bl & 0x7) << 0)
1737                   );
1738
1739         ddr->ddr_sdram_mode = (0
1740                                | ((esdmode & 0xFFFF) << 16)
1741                                | ((sdmode & 0xFFFF) << 0)
1742                                );
1743         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1744 }
1745 #endif
1746
1747 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1748 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1749 {
1750         unsigned int init_value;        /* Initialization value */
1751
1752 #ifdef CONFIG_MEM_INIT_VALUE
1753         init_value = CONFIG_MEM_INIT_VALUE;
1754 #else
1755         init_value = 0xDEADBEEF;
1756 #endif
1757         ddr->ddr_data_init = init_value;
1758 }
1759
1760 /*
1761  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1762  * The old controller on the 8540/60 doesn't have this register.
1763  * Hope it's OK to set it (to 0) anyway.
1764  */
1765 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1766                                          const memctl_options_t *popts)
1767 {
1768         unsigned int clk_adjust;        /* Clock adjust */
1769         unsigned int ss_en = 0;         /* Source synchronous enable */
1770
1771 #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
1772         /* Per FSL Application Note: AN2805 */
1773         ss_en = 1;
1774 #endif
1775         clk_adjust = popts->clk_adjust;
1776         ddr->ddr_sdram_clk_cntl = (0
1777                                    | ((ss_en & 0x1) << 31)
1778                                    | ((clk_adjust & 0xF) << 23)
1779                                    );
1780         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1781 }
1782
1783 /* DDR Initialization Address (DDR_INIT_ADDR) */
1784 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1785 {
1786         unsigned int init_addr = 0;     /* Initialization address */
1787
1788         ddr->ddr_init_addr = init_addr;
1789 }
1790
1791 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1792 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1793 {
1794         unsigned int uia = 0;   /* Use initialization address */
1795         unsigned int init_ext_addr = 0; /* Initialization address */
1796
1797         ddr->ddr_init_ext_addr = (0
1798                                   | ((uia & 0x1) << 31)
1799                                   | (init_ext_addr & 0xF)
1800                                   );
1801 }
1802
1803 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1804 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1805                                 const memctl_options_t *popts)
1806 {
1807         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1808         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1809         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1810         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1811         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1812
1813 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1814         if (popts->burst_length == DDR_BL8) {
1815                 /* We set BL/2 for fixed BL8 */
1816                 rrt = 0;        /* BL/2 clocks */
1817                 wwt = 0;        /* BL/2 clocks */
1818         } else {
1819                 /* We need to set BL/2 + 2 to BC4 and OTF */
1820                 rrt = 2;        /* BL/2 + 2 clocks */
1821                 wwt = 2;        /* BL/2 + 2 clocks */
1822         }
1823 #endif
1824
1825 #ifdef CONFIG_SYS_FSL_DDR4
1826         dll_lock = 2;   /* tDLLK = 1024 clocks */
1827 #elif defined(CONFIG_SYS_FSL_DDR3)
1828         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1829 #endif
1830         ddr->timing_cfg_4 = (0
1831                              | ((rwt & 0xf) << 28)
1832                              | ((wrt & 0xf) << 24)
1833                              | ((rrt & 0xf) << 20)
1834                              | ((wwt & 0xf) << 16)
1835                              | (dll_lock & 0x3)
1836                              );
1837         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1838 }
1839
1840 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1841 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1842 {
1843         unsigned int rodt_on = 0;       /* Read to ODT on */
1844         unsigned int rodt_off = 0;      /* Read to ODT off */
1845         unsigned int wodt_on = 0;       /* Write to ODT on */
1846         unsigned int wodt_off = 0;      /* Write to ODT off */
1847
1848 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1849         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1850                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1851         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1852         if (cas_latency >= wr_lat)
1853                 rodt_on = cas_latency - wr_lat + 1;
1854         rodt_off = 4;   /*  4 clocks */
1855         wodt_on = 1;    /*  1 clocks */
1856         wodt_off = 4;   /*  4 clocks */
1857 #endif
1858
1859         ddr->timing_cfg_5 = (0
1860                              | ((rodt_on & 0x1f) << 24)
1861                              | ((rodt_off & 0x7) << 20)
1862                              | ((wodt_on & 0x1f) << 12)
1863                              | ((wodt_off & 0x7) << 8)
1864                              );
1865         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1866 }
1867
1868 #ifdef CONFIG_SYS_FSL_DDR4
1869 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1870 {
1871         unsigned int hs_caslat = 0;
1872         unsigned int hs_wrlat = 0;
1873         unsigned int hs_wrrec = 0;
1874         unsigned int hs_clkadj = 0;
1875         unsigned int hs_wrlvl_start = 0;
1876
1877         ddr->timing_cfg_6 = (0
1878                              | ((hs_caslat & 0x1f) << 24)
1879                              | ((hs_wrlat & 0x1f) << 19)
1880                              | ((hs_wrrec & 0x1f) << 12)
1881                              | ((hs_clkadj & 0x1f) << 6)
1882                              | ((hs_wrlvl_start & 0x1f) << 0)
1883                             );
1884         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1885 }
1886
1887 static void set_timing_cfg_7(const unsigned int ctrl_num,
1888                              fsl_ddr_cfg_regs_t *ddr,
1889                              const common_timing_params_t *common_dimm)
1890 {
1891         unsigned int txpr, tcksre, tcksrx;
1892         unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1893
1894         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1895         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1896         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1897         par_lat = 0;
1898         cs_to_cmd = 0;
1899
1900         if (txpr <= 200)
1901                 cke_rst = 0;
1902         else if (txpr <= 256)
1903                 cke_rst = 1;
1904         else if (txpr <= 512)
1905                 cke_rst = 2;
1906         else
1907                 cke_rst = 3;
1908
1909         if (tcksre <= 19)
1910                 cksre = tcksre - 5;
1911         else
1912                 cksre = 15;
1913
1914         if (tcksrx <= 19)
1915                 cksrx = tcksrx - 5;
1916         else
1917                 cksrx = 15;
1918
1919         ddr->timing_cfg_7 = (0
1920                              | ((cke_rst & 0x3) << 28)
1921                              | ((cksre & 0xf) << 24)
1922                              | ((cksrx & 0xf) << 20)
1923                              | ((par_lat & 0xf) << 16)
1924                              | ((cs_to_cmd & 0xf) << 4)
1925                             );
1926         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1927 }
1928
1929 static void set_timing_cfg_8(const unsigned int ctrl_num,
1930                              fsl_ddr_cfg_regs_t *ddr,
1931                              const memctl_options_t *popts,
1932                              const common_timing_params_t *common_dimm,
1933                              unsigned int cas_latency)
1934 {
1935         unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1936         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1937         unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1938         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1939                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1940
1941         rwt_bg = cas_latency + 2 + 4 - wr_lat;
1942         if (rwt_bg < tccdl)
1943                 rwt_bg = tccdl - rwt_bg;
1944         else
1945                 rwt_bg = 0;
1946
1947         wrt_bg = wr_lat + 4 + 1 - cas_latency;
1948         if (wrt_bg < tccdl)
1949                 wrt_bg = tccdl - wrt_bg;
1950         else
1951                 wrt_bg = 0;
1952
1953         if (popts->burst_length == DDR_BL8) {
1954                 rrt_bg = tccdl - 4;
1955                 wwt_bg = tccdl - 4;
1956         } else {
1957                 rrt_bg = tccdl - 2;
1958                 wwt_bg = tccdl - 2;
1959         }
1960
1961         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
1962         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
1963         if (popts->otf_burst_chop_en)
1964                 wrtord_bg += 2;
1965
1966         pre_all_rec = 0;
1967
1968         ddr->timing_cfg_8 = (0
1969                              | ((rwt_bg & 0xf) << 28)
1970                              | ((wrt_bg & 0xf) << 24)
1971                              | ((rrt_bg & 0xf) << 20)
1972                              | ((wwt_bg & 0xf) << 16)
1973                              | ((acttoact_bg & 0xf) << 12)
1974                              | ((wrtord_bg & 0xf) << 8)
1975                              | ((pre_all_rec & 0x1f) << 0)
1976                             );
1977
1978         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1979 }
1980
1981 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1982 {
1983         ddr->timing_cfg_9 = 0;
1984         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1985 }
1986
1987 /* This function needs to be called after set_ddr_sdram_cfg() is called */
1988 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1989                                const dimm_params_t *dimm_params)
1990 {
1991         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
1992         int i;
1993
1994         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
1995                 if (dimm_params[i].n_ranks)
1996                         break;
1997         }
1998         if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
1999                 puts("DDR error: no DIMM found!\n");
2000                 return;
2001         }
2002
2003         ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2004                         ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2005                         ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2006                         ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2007                         ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2008
2009         ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2010                         ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2011                         ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2012                         ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2013                         ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2014
2015         ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2016                         ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2017                         ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2018                         ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2019                         ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2020
2021         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2022         ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2023                         ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2024                         (acc_ecc_en ? 0 :
2025                          (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2026                         dimm_params[i].dq_mapping_ors;
2027
2028         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2029         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2030         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2031         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2032 }
2033 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2034                                const memctl_options_t *popts)
2035 {
2036         int rd_pre;
2037
2038         rd_pre = popts->quad_rank_present ? 1 : 0;
2039
2040         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2041
2042         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2043 }
2044 #endif  /* CONFIG_SYS_FSL_DDR4 */
2045
2046 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2047 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2048 {
2049         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2050         /* Normal Operation Full Calibration Time (tZQoper) */
2051         unsigned int zqoper = 0;
2052         /* Normal Operation Short Calibration Time (tZQCS) */
2053         unsigned int zqcs = 0;
2054 #ifdef CONFIG_SYS_FSL_DDR4
2055         unsigned int zqcs_init;
2056 #endif
2057
2058         if (zq_en) {
2059 #ifdef CONFIG_SYS_FSL_DDR4
2060                 zqinit = 10;    /* 1024 clocks */
2061                 zqoper = 9;     /* 512 clocks */
2062                 zqcs = 7;       /* 128 clocks */
2063                 zqcs_init = 5;  /* 1024 refresh sequences */
2064 #else
2065                 zqinit = 9;     /* 512 clocks */
2066                 zqoper = 8;     /* 256 clocks */
2067                 zqcs = 6;       /* 64 clocks */
2068 #endif
2069         }
2070
2071         ddr->ddr_zq_cntl = (0
2072                             | ((zq_en & 0x1) << 31)
2073                             | ((zqinit & 0xF) << 24)
2074                             | ((zqoper & 0xF) << 16)
2075                             | ((zqcs & 0xF) << 8)
2076 #ifdef CONFIG_SYS_FSL_DDR4
2077                             | ((zqcs_init & 0xF) << 0)
2078 #endif
2079                             );
2080         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2081 }
2082
2083 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2084 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2085                                 const memctl_options_t *popts)
2086 {
2087         /*
2088          * First DQS pulse rising edge after margining mode
2089          * is programmed (tWL_MRD)
2090          */
2091         unsigned int wrlvl_mrd = 0;
2092         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2093         unsigned int wrlvl_odten = 0;
2094         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2095         unsigned int wrlvl_dqsen = 0;
2096         /* WRLVL_SMPL: Write leveling sample time */
2097         unsigned int wrlvl_smpl = 0;
2098         /* WRLVL_WLR: Write leveling repeition time */
2099         unsigned int wrlvl_wlr = 0;
2100         /* WRLVL_START: Write leveling start time */
2101         unsigned int wrlvl_start = 0;
2102
2103         /* suggest enable write leveling for DDR3 due to fly-by topology */
2104         if (wrlvl_en) {
2105                 /* tWL_MRD min = 40 nCK, we set it 64 */
2106                 wrlvl_mrd = 0x6;
2107                 /* tWL_ODTEN 128 */
2108                 wrlvl_odten = 0x7;
2109                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2110                 wrlvl_dqsen = 0x5;
2111                 /*
2112                  * Write leveling sample time at least need 6 clocks
2113                  * higher than tWLO to allow enough time for progagation
2114                  * delay and sampling the prime data bits.
2115                  */
2116                 wrlvl_smpl = 0xf;
2117                 /*
2118                  * Write leveling repetition time
2119                  * at least tWLO + 6 clocks clocks
2120                  * we set it 64
2121                  */
2122                 wrlvl_wlr = 0x6;
2123                 /*
2124                  * Write leveling start time
2125                  * The value use for the DQS_ADJUST for the first sample
2126                  * when write leveling is enabled. It probably needs to be
2127                  * overriden per platform.
2128                  */
2129                 wrlvl_start = 0x8;
2130                 /*
2131                  * Override the write leveling sample and start time
2132                  * according to specific board
2133                  */
2134                 if (popts->wrlvl_override) {
2135                         wrlvl_smpl = popts->wrlvl_sample;
2136                         wrlvl_start = popts->wrlvl_start;
2137                 }
2138         }
2139
2140         ddr->ddr_wrlvl_cntl = (0
2141                                | ((wrlvl_en & 0x1) << 31)
2142                                | ((wrlvl_mrd & 0x7) << 24)
2143                                | ((wrlvl_odten & 0x7) << 20)
2144                                | ((wrlvl_dqsen & 0x7) << 16)
2145                                | ((wrlvl_smpl & 0xf) << 12)
2146                                | ((wrlvl_wlr & 0x7) << 8)
2147                                | ((wrlvl_start & 0x1F) << 0)
2148                                );
2149         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2150         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2151         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2152         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2153         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2154
2155 }
2156
2157 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2158 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2159 {
2160         /* Self Refresh Idle Threshold */
2161         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2162 }
2163
2164 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2165 {
2166         if (popts->addr_hash) {
2167                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2168                 puts("Address hashing enabled.\n");
2169         }
2170 }
2171
2172 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2173 {
2174         ddr->ddr_cdr1 = popts->ddr_cdr1;
2175         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2176 }
2177
2178 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2179 {
2180         ddr->ddr_cdr2 = popts->ddr_cdr2;
2181         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2182 }
2183
2184 unsigned int
2185 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2186 {
2187         unsigned int res = 0;
2188
2189         /*
2190          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2191          * not set at the same time.
2192          */
2193         if (ddr->ddr_sdram_cfg & 0x10000000
2194             && ddr->ddr_sdram_cfg & 0x00008000) {
2195                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2196                                 " should not be set at the same time.\n");
2197                 res++;
2198         }
2199
2200         return res;
2201 }
2202
2203 unsigned int
2204 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2205                                const memctl_options_t *popts,
2206                                fsl_ddr_cfg_regs_t *ddr,
2207                                const common_timing_params_t *common_dimm,
2208                                const dimm_params_t *dimm_params,
2209                                unsigned int dbw_cap_adj,
2210                                unsigned int size_only)
2211 {
2212         unsigned int i;
2213         unsigned int cas_latency;
2214         unsigned int additive_latency;
2215         unsigned int sr_it;
2216         unsigned int zq_en;
2217         unsigned int wrlvl_en;
2218         unsigned int ip_rev = 0;
2219         unsigned int unq_mrs_en = 0;
2220         int cs_en = 1;
2221
2222         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2223
2224         if (common_dimm == NULL) {
2225                 printf("Error: subset DIMM params struct null pointer\n");
2226                 return 1;
2227         }
2228
2229         /*
2230          * Process overrides first.
2231          *
2232          * FIXME: somehow add dereated caslat to this
2233          */
2234         cas_latency = (popts->cas_latency_override)
2235                 ? popts->cas_latency_override_value
2236                 : common_dimm->lowest_common_spd_caslat;
2237
2238         additive_latency = (popts->additive_latency_override)
2239                 ? popts->additive_latency_override_value
2240                 : common_dimm->additive_latency;
2241
2242         sr_it = (popts->auto_self_refresh_en)
2243                 ? popts->sr_it
2244                 : 0;
2245         /* ZQ calibration */
2246         zq_en = (popts->zq_en) ? 1 : 0;
2247         /* write leveling */
2248         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2249
2250         /* Chip Select Memory Bounds (CSn_BNDS) */
2251         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2252                 unsigned long long ea, sa;
2253                 unsigned int cs_per_dimm
2254                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2255                 unsigned int dimm_number
2256                         = i / cs_per_dimm;
2257                 unsigned long long rank_density
2258                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2259
2260                 if (dimm_params[dimm_number].n_ranks == 0) {
2261                         debug("Skipping setup of CS%u "
2262                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2263                         continue;
2264                 }
2265                 if (popts->memctl_interleaving) {
2266                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2267                         case FSL_DDR_CS0_CS1_CS2_CS3:
2268                                 break;
2269                         case FSL_DDR_CS0_CS1:
2270                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2271                                 if (i > 1)
2272                                         cs_en = 0;
2273                                 break;
2274                         case FSL_DDR_CS2_CS3:
2275                         default:
2276                                 if (i > 0)
2277                                         cs_en = 0;
2278                                 break;
2279                         }
2280                         sa = common_dimm->base_address;
2281                         ea = sa + common_dimm->total_mem - 1;
2282                 } else if (!popts->memctl_interleaving) {
2283                         /*
2284                          * If memory interleaving between controllers is NOT
2285                          * enabled, the starting address for each memory
2286                          * controller is distinct.  However, because rank
2287                          * interleaving is enabled, the starting and ending
2288                          * addresses of the total memory on that memory
2289                          * controller needs to be programmed into its
2290                          * respective CS0_BNDS.
2291                          */
2292                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2293                         case FSL_DDR_CS0_CS1_CS2_CS3:
2294                                 sa = common_dimm->base_address;
2295                                 ea = sa + common_dimm->total_mem - 1;
2296                                 break;
2297                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2298                                 if ((i >= 2) && (dimm_number == 0)) {
2299                                         sa = dimm_params[dimm_number].base_address +
2300                                               2 * rank_density;
2301                                         ea = sa + 2 * rank_density - 1;
2302                                 } else {
2303                                         sa = dimm_params[dimm_number].base_address;
2304                                         ea = sa + 2 * rank_density - 1;
2305                                 }
2306                                 break;
2307                         case FSL_DDR_CS0_CS1:
2308                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2309                                         sa = dimm_params[dimm_number].base_address;
2310                                         ea = sa + rank_density - 1;
2311                                         if (i != 1)
2312                                                 sa += (i % cs_per_dimm) * rank_density;
2313                                         ea += (i % cs_per_dimm) * rank_density;
2314                                 } else {
2315                                         sa = 0;
2316                                         ea = 0;
2317                                 }
2318                                 if (i == 0)
2319                                         ea += rank_density;
2320                                 break;
2321                         case FSL_DDR_CS2_CS3:
2322                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2323                                         sa = dimm_params[dimm_number].base_address;
2324                                         ea = sa + rank_density - 1;
2325                                         if (i != 3)
2326                                                 sa += (i % cs_per_dimm) * rank_density;
2327                                         ea += (i % cs_per_dimm) * rank_density;
2328                                 } else {
2329                                         sa = 0;
2330                                         ea = 0;
2331                                 }
2332                                 if (i == 2)
2333                                         ea += (rank_density >> dbw_cap_adj);
2334                                 break;
2335                         default:  /* No bank(chip-select) interleaving */
2336                                 sa = dimm_params[dimm_number].base_address;
2337                                 ea = sa + rank_density - 1;
2338                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2339                                         sa += (i % cs_per_dimm) * rank_density;
2340                                         ea += (i % cs_per_dimm) * rank_density;
2341                                 } else {
2342                                         sa = 0;
2343                                         ea = 0;
2344                                 }
2345                                 break;
2346                         }
2347                 }
2348
2349                 sa >>= 24;
2350                 ea >>= 24;
2351
2352                 if (cs_en) {
2353                         ddr->cs[i].bnds = (0
2354                                 | ((sa & 0xffff) << 16) /* starting address */
2355                                 | ((ea & 0xffff) << 0)  /* ending address */
2356                                 );
2357                 } else {
2358                         /* setting bnds to 0xffffffff for inactive CS */
2359                         ddr->cs[i].bnds = 0xffffffff;
2360                 }
2361
2362                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2363                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2364                 set_csn_config_2(i, ddr);
2365         }
2366
2367         /*
2368          * In the case we only need to compute the ddr sdram size, we only need
2369          * to set csn registers, so return from here.
2370          */
2371         if (size_only)
2372                 return 0;
2373
2374         set_ddr_eor(ddr, popts);
2375
2376 #if !defined(CONFIG_SYS_FSL_DDR1)
2377         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2378 #endif
2379
2380         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2381                          additive_latency);
2382         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2383         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2384                          cas_latency, additive_latency);
2385
2386         set_ddr_cdr1(ddr, popts);
2387         set_ddr_cdr2(ddr, popts);
2388         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2389         ip_rev = fsl_ddr_get_version(ctrl_num);
2390         if (ip_rev > 0x40400)
2391                 unq_mrs_en = 1;
2392
2393         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2394                 ddr->debug[18] = popts->cswl_override;
2395
2396         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2397         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2398                            cas_latency, additive_latency, unq_mrs_en);
2399         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2400 #ifdef CONFIG_SYS_FSL_DDR4
2401         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2402         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2403 #endif
2404         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2405         set_ddr_data_init(ddr);
2406         set_ddr_sdram_clk_cntl(ddr, popts);
2407         set_ddr_init_addr(ddr);
2408         set_ddr_init_ext_addr(ddr);
2409         set_timing_cfg_4(ddr, popts);
2410         set_timing_cfg_5(ddr, cas_latency);
2411 #ifdef CONFIG_SYS_FSL_DDR4
2412         set_ddr_sdram_cfg_3(ddr, popts);
2413         set_timing_cfg_6(ddr);
2414         set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2415         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2416         set_timing_cfg_9(ddr);
2417         set_ddr_dq_mapping(ddr, dimm_params);
2418 #endif
2419
2420         set_ddr_zq_cntl(ddr, zq_en);
2421         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2422
2423         set_ddr_sr_cntr(ddr, sr_it);
2424
2425         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2426
2427 #ifdef CONFIG_SYS_FSL_DDR_EMU
2428         /* disble DDR training for emulator */
2429         ddr->debug[2] = 0x00000400;
2430         ddr->debug[4] = 0xff800800;
2431         ddr->debug[5] = 0x08000800;
2432         ddr->debug[6] = 0x08000800;
2433         ddr->debug[7] = 0x08000800;
2434         ddr->debug[8] = 0x08000800;
2435 #endif
2436 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2437         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2438                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2439 #endif
2440
2441         return check_fsl_memctl_config_regs(ddr);
2442 }