drivers/ddr/altera/sdram_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright Altera Corporation (C) 2014-2015
   4  */
   5 #include <common.h>
   6 #include <dm.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <init.h>
  10 #include <ram.h>
  11 #include <reset.h>
  12 #include <watchdog.h>
  13 #include <asm/arch/fpga_manager.h>
  14 #include <asm/arch/reset_manager.h>
  15 #include <asm/arch/sdram.h>
  16 #include <asm/arch/system_manager.h>
  17 #include <asm/io.h>
  18 #include <dm/device_compat.h>
  19
  20 #include "sequencer.h"
  21
  22 #ifdef CONFIG_SPL_BUILD
  23
  24 struct altera_gen5_sdram_priv {
  25         struct ram_info info;
  26 };
  27
  28 struct altera_gen5_sdram_platdata {
  29         struct socfpga_sdr *sdr;
  30 };
  31
  32 struct sdram_prot_rule {
  33         u32     sdram_start;    /* SDRAM start address */
  34         u32     sdram_end;      /* SDRAM end address */
  35         u32     rule;           /* SDRAM protection rule number: 0-19 */
  36         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  37
  38         u32     security;
  39         u32     portmask;
  40         u32     result;
  41         u32     lo_prot_id;
  42         u32     hi_prot_id;
  43 };
  44
  45 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
  46
  47 /**
  48  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  49  * @cfg:        SDRAM controller configuration data
  50  *
  51  * SDRAM Failure happens when accessing non-existent memory. Artificially
  52  * increase the number of rows so that the memory controller thinks it has
  53  * 4GB of RAM. This function returns such amount of rows.
  54  */
  55 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  56 {
  57         /* Define constant for 4G memory - used for SDRAM errata workaround */
  58 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  59         const unsigned long long memsize = MEMSIZE_4G;
  60         const unsigned int cs =
  61                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  62                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  63         const unsigned int rows =
  64                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  65                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  66         const unsigned int banks =
  67                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  68                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  69         const unsigned int cols =
  70                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  71                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  72         const unsigned int width = 8;
  73
  74         unsigned long long newrows;
  75         int bits, inewrowslog2;
  76
  77         debug("workaround rows - memsize %lld\n", memsize);
  78         debug("workaround rows - cs        %d\n", cs);
  79         debug("workaround rows - width     %d\n", width);
  80         debug("workaround rows - rows      %d\n", rows);
  81         debug("workaround rows - banks     %d\n", banks);
  82         debug("workaround rows - cols      %d\n", cols);
  83
  84         newrows = lldiv(memsize, cs * (width / 8));
  85         debug("rows workaround - term1 %lld\n", newrows);
  86
  87         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  88         debug("rows workaround - term2 %lld\n", newrows);
  89
  90         /*
  91          * Compute the hamming weight - same as number of bits set.
  92          * Need to see if result is ordinal power of 2 before
  93          * attempting log2 of result.
  94          */
  95         bits = generic_hweight32(newrows);
  96
  97         debug("rows workaround - bits %d\n", bits);
  98
  99         if (bits != 1) {
 100                 printf("SDRAM workaround failed, bits set %d\n", bits);
 101                 return rows;
 102         }
 103
 104         if (newrows > UINT_MAX) {
 105                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
 106                 return rows;
 107         }
 108
 109         inewrowslog2 = __ilog2(newrows);
 110
 111         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 112
 113         if (inewrowslog2 == -1) {
 114                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 115                 return rows;
 116         }
 117
 118         return inewrowslog2;
 119 }
 120
 121 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 122 static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
 123                            struct sdram_prot_rule *prule)
 124 {
 125         u32 lo_addr_bits;
 126         u32 hi_addr_bits;
 127         int ruleno = prule->rule;
 128
 129         /* Select the rule */
 130         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 131
 132         /* Obtain the address bits */
 133         lo_addr_bits = prule->sdram_start >> 20ULL;
 134         hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 135
 136         debug("sdram set rule start %x, %d\n", lo_addr_bits,
 137               prule->sdram_start);
 138         debug("sdram set rule end   %x, %d\n", hi_addr_bits,
 139               prule->sdram_end);
 140
 141         /* Set rule addresses */
 142         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 143
 144         /* Set rule protection ids */
 145         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 146                &sdr_ctrl->prot_rule_id);
 147
 148         /* Set the rule data */
 149         writel(prule->security | (prule->valid << 2) |
 150                (prule->portmask << 3) | (prule->result << 13),
 151                &sdr_ctrl->prot_rule_data);
 152
 153         /* write the rule */
 154         writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
 155
 156         /* Set rule number to 0 by default */
 157         writel(0, &sdr_ctrl->prot_rule_rdwr);
 158 }
 159
 160 static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
 161                            struct sdram_prot_rule *prule)
 162 {
 163         u32 addr;
 164         u32 id;
 165         u32 data;
 166         int ruleno = prule->rule;
 167
 168         /* Read the rule */
 169         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 170         writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
 171
 172         /* Get the addresses */
 173         addr = readl(&sdr_ctrl->prot_rule_addr);
 174         prule->sdram_start = (addr & 0xFFF) << 20;
 175         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 176
 177         /* Get the configured protection IDs */
 178         id = readl(&sdr_ctrl->prot_rule_id);
 179         prule->lo_prot_id = id & 0xFFF;
 180         prule->hi_prot_id = (id >> 12) & 0xFFF;
 181
 182         /* Get protection data */
 183         data = readl(&sdr_ctrl->prot_rule_data);
 184
 185         prule->security = data & 0x3;
 186         prule->valid = (data >> 2) & 0x1;
 187         prule->portmask = (data >> 3) & 0x3FF;
 188         prule->result = (data >> 13) & 0x1;
 189 }
 190
 191 static void
 192 sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
 193                             const u32 sdram_start, const u32 sdram_end)
 194 {
 195         struct sdram_prot_rule rule;
 196         int rules;
 197
 198         /* Start with accepting all SDRAM transaction */
 199         writel(0x0, &sdr_ctrl->protport_default);
 200
 201         /* Clear all protection rules for warm boot case */
 202         memset(&rule, 0, sizeof(rule));
 203
 204         for (rules = 0; rules < 20; rules++) {
 205                 rule.rule = rules;
 206                 sdram_set_rule(sdr_ctrl, &rule);
 207         }
 208
 209         /* new rule: accept SDRAM */
 210         rule.sdram_start = sdram_start;
 211         rule.sdram_end = sdram_end;
 212         rule.lo_prot_id = 0x0;
 213         rule.hi_prot_id = 0xFFF;
 214         rule.portmask = 0x3FF;
 215         rule.security = 0x3;
 216         rule.result = 0;
 217         rule.valid = 1;
 218         rule.rule = 0;
 219
 220         /* set new rule */
 221         sdram_set_rule(sdr_ctrl, &rule);
 222
 223         /* default rule: reject everything */
 224         writel(0x3ff, &sdr_ctrl->protport_default);
 225 }
 226
 227 static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
 228 {
 229         struct sdram_prot_rule rule;
 230         int rules;
 231
 232         debug("SDRAM Prot rule, default %x\n",
 233               readl(&sdr_ctrl->protport_default));
 234
 235         for (rules = 0; rules < 20; rules++) {
 236                 rule.rule = rules;
 237                 sdram_get_rule(sdr_ctrl, &rule);
 238                 debug("Rule %d, rules ...\n", rules);
 239                 debug("    sdram start %x\n", rule.sdram_start);
 240                 debug("    sdram end   %x\n", rule.sdram_end);
 241                 debug("    low prot id %d, hi prot id %d\n",
 242                       rule.lo_prot_id,
 243                       rule.hi_prot_id);
 244                 debug("    portmask %x\n", rule.portmask);
 245                 debug("    security %d\n", rule.security);
 246                 debug("    result %d\n", rule.result);
 247                 debug("    valid %d\n", rule.valid);
 248         }
 249 }
 250
 251 /**
 252  * sdram_write_verify() - write to register and verify the write.
 253  * @addr:       Register address
 254  * @val:        Value to be written and verified
 255  *
 256  * This function writes to a register, reads back the value and compares
 257  * the result with the written value to check if the data match.
 258  */
 259 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
 260 {
 261         u32 rval;
 262
 263         debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
 264         writel(val, addr);
 265
 266         debug("   Read and verify...");
 267         rval = readl(addr);
 268         if (rval != val) {
 269                 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
 270                       addr, val, rval);
 271                 return -EINVAL;
 272         }
 273
 274         debug("correct!\n");
 275         return 0;
 276 }
 277
 278 /**
 279  * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 280  * @cfg:        SDRAM controller configuration data
 281  *
 282  * Return the value of DRAM CTRLCFG register.
 283  */
 284 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 285 {
 286         const u32 csbits =
 287                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 288                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 289         u32 addrorder =
 290                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 291                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 292
 293         u32 ctrl_cfg = cfg->ctrl_cfg;
 294
 295         /*
 296          * SDRAM Failure When Accessing Non-Existent Memory
 297          * Set the addrorder field of the SDRAM control register
 298          * based on the CSBITs setting.
 299          */
 300         if (csbits == 1) {
 301                 if (addrorder != 0)
 302                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 303                 addrorder = 0;
 304         } else if (csbits == 2) {
 305                 if (addrorder != 2)
 306                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 307                 addrorder = 2;
 308         }
 309
 310         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 311         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 312
 313         return ctrl_cfg;
 314 }
 315
 316 /**
 317  * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 318  * @cfg:        SDRAM controller configuration data
 319  *
 320  * Return the value of DRAM ADDRW register.
 321  */
 322 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 323 {
 324         /*
 325          * SDRAM Failure When Accessing Non-Existent Memory
 326          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 327          * log2(number of chip select bits). Since there's only
 328          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 329          * which is the same as "chip selects" - 1.
 330          */
 331         const int rows = get_errata_rows(cfg);
 332         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 333
 334         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 335 }
 336
 337 /**
 338  * sdr_load_regs() - Load SDRAM controller registers
 339  * @cfg:        SDRAM controller configuration data
 340  *
 341  * This function loads the register values into the SDRAM controller block.
 342  */
 343 static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
 344                           const struct socfpga_sdram_config *cfg)
 345 {
 346         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 347         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 348
 349         debug("\nConfiguring CTRLCFG\n");
 350         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 351
 352         debug("Configuring DRAMTIMING1\n");
 353         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 354
 355         debug("Configuring DRAMTIMING2\n");
 356         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 357
 358         debug("Configuring DRAMTIMING3\n");
 359         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 360
 361         debug("Configuring DRAMTIMING4\n");
 362         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 363
 364         debug("Configuring LOWPWRTIMING\n");
 365         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 366
 367         debug("Configuring DRAMADDRW\n");
 368         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 369
 370         debug("Configuring DRAMIFWIDTH\n");
 371         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 372
 373         debug("Configuring DRAMDEVWIDTH\n");
 374         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 375
 376         debug("Configuring LOWPWREQ\n");
 377         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 378
 379         debug("Configuring DRAMINTR\n");
 380         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 381
 382         debug("Configuring STATICCFG\n");
 383         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 384
 385         debug("Configuring CTRLWIDTH\n");
 386         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 387
 388         debug("Configuring PORTCFG\n");
 389         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 390
 391         debug("Configuring FIFOCFG\n");
 392         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 393
 394         debug("Configuring MPPRIORITY\n");
 395         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 396
 397         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 398         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 399         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 400         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 401         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 402
 403         debug("Configuring MPPACING_MPPACING_0\n");
 404         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 405         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 406         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 407         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 408
 409         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 410         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 411         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 412         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 413
 414         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 415         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 416
 417         debug("Configuring CPORTWIDTH\n");
 418         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 419
 420         debug("Configuring CPORTWMAP\n");
 421         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 422
 423         debug("Configuring CPORTRMAP\n");
 424         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 425
 426         debug("Configuring RFIFOCMAP\n");
 427         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 428
 429         debug("Configuring WFIFOCMAP\n");
 430         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 431
 432         debug("Configuring CPORTRDWR\n");
 433         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 434
 435         debug("Configuring DRAMODT\n");
 436         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 437
 438         if (dram_is_ddr(3)) {
 439                 debug("Configuring EXTRATIME1\n");
 440                 writel(cfg->extratime1, &sdr_ctrl->extratime1);
 441         }
 442 }
 443
 444 /**
 445  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 446  * @sdr_phy_reg:        Value of the PHY control register 0
 447  *
 448  * Initialize the SDRAM MMR.
 449  */
 450 int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
 451                         unsigned int sdr_phy_reg)
 452 {
 453         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 454         const unsigned int rows =
 455                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 456                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 457         int ret;
 458
 459         writel(rows,
 460                socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 461
 462         sdr_load_regs(sdr_ctrl, cfg);
 463
 464         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 465         writel(cfg->fpgaport_rst,
 466                socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
 467
 468         /* only enable if the FPGA is programmed */
 469         if (fpgamgr_test_fpga_ready()) {
 470                 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 471                                          cfg->fpgaport_rst);
 472                 if (ret)
 473                         return ret;
 474         }
 475
 476         /* Restore the SDR PHY Register if valid */
 477         if (sdr_phy_reg != 0xffffffff)
 478                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 479
 480         /* Final step - apply configuration changes */
 481         debug("Configuring STATICCFG\n");
 482         clrsetbits_le32(&sdr_ctrl->static_cfg,
 483                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 484                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 485
 486         sdram_set_protection_config(sdr_ctrl, 0,
 487                                     sdram_calculate_size(sdr_ctrl) - 1);
 488
 489         sdram_dump_protection_config(sdr_ctrl);
 490
 491         return 0;
 492 }
 493
 494 /**
 495  * sdram_calculate_size() - Calculate SDRAM size
 496  *
 497  * Calculate SDRAM device size based on SDRAM controller parameters.
 498  * Size is specified in bytes.
 499  */
 500 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
 501 {
 502         unsigned long temp;
 503         unsigned long row, bank, col, cs, width;
 504         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 505         const unsigned int csbits =
 506                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 507                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 508         const unsigned int rowbits =
 509                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 510                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 511
 512         temp = readl(&sdr_ctrl->dram_addrw);
 513         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 514                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 515
 516         /*
 517          * SDRAM Failure When Accessing Non-Existent Memory
 518          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 519          * since the FB specifies we modify ROWBITs to work around SDRAM
 520          * controller issue.
 521          */
 522         row = readl(socfpga_get_sysmgr_addr() +
 523                     SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 524         if (row == 0)
 525                 row = rowbits;
 526         /*
 527          * If the stored handoff value for rows is greater than
 528          * the field width in the sdr.dramaddrw register then
 529          * something is very wrong. Revert to using the the #define
 530          * value handed off by the SOCEDS tool chain instead of
 531          * using a broken value.
 532          */
 533         if (row > 31)
 534                 row = rowbits;
 535
 536         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 537                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 538
 539         /*
 540          * SDRAM Failure When Accessing Non-Existent Memory
 541          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 542          * since the FB specifies we modify CSBITs to work around SDRAM
 543          * controller issue.
 544          */
 545         cs = csbits;
 546
 547         width = readl(&sdr_ctrl->dram_if_width);
 548
 549         /* ECC would not be calculated as its not addressible */
 550         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 551                 width = 32;
 552         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 553                 width = 16;
 554
 555         /* calculate the SDRAM size base on this info */
 556         temp = 1 << (row + bank + col);
 557         temp = temp * cs * (width  / 8);
 558
 559         debug("%s returns %ld\n", __func__, temp);
 560
 561         return temp;
 562 }
 563
 564 static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
 565 {
 566         struct altera_gen5_sdram_platdata *plat = dev->platdata;
 567
 568         plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
 569         if (!plat->sdr)
 570                 return -ENODEV;
 571
 572         return 0;
 573 }
 574
 575 static int altera_gen5_sdram_probe(struct udevice *dev)
 576 {
 577         int ret;
 578         unsigned long sdram_size;
 579         struct altera_gen5_sdram_platdata *plat = dev->platdata;
 580         struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
 581         struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
 582         struct reset_ctl_bulk resets;
 583
 584         ret = reset_get_bulk(dev, &resets);
 585         if (ret) {
 586                 dev_err(dev, "Can't get reset: %d\n", ret);
 587                 return -ENODEV;
 588         }
 589         reset_deassert_bulk(&resets);
 590
 591         if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
 592                 puts("SDRAM init failed.\n");
 593                 goto failed;
 594         }
 595
 596         debug("SDRAM: Calibrating PHY\n");
 597         /* SDRAM calibration */
 598         if (sdram_calibration_full(plat->sdr) == 0) {
 599                 puts("SDRAM calibration failed.\n");
 600                 goto failed;
 601         }
 602
 603         sdram_size = sdram_calculate_size(sdr_ctrl);
 604         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 605
 606         /* Sanity check ensure correct SDRAM size specified */
 607         if (get_ram_size(0, sdram_size) != sdram_size) {
 608                 puts("SDRAM size check failed!\n");
 609                 goto failed;
 610         }
 611
 612         priv->info.base = 0;
 613         priv->info.size = sdram_size;
 614
 615         return 0;
 616
 617 failed:
 618         reset_release_bulk(&resets);
 619         return -ENODEV;
 620 }
 621
 622 static int altera_gen5_sdram_get_info(struct udevice *dev,
 623                                       struct ram_info *info)
 624 {
 625         struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
 626
 627         info->base = priv->info.base;
 628         info->size = priv->info.size;
 629
 630         return 0;
 631 }
 632
 633 static const struct ram_ops altera_gen5_sdram_ops = {
 634         .get_info = altera_gen5_sdram_get_info,
 635 };
 636
 637 static const struct udevice_id altera_gen5_sdram_ids[] = {
 638         { .compatible = "altr,sdr-ctl" },
 639         { /* sentinel */ }
 640 };
 641
 642 U_BOOT_DRIVER(altera_gen5_sdram) = {
 643         .name = "altr_sdr_ctl",
 644         .id = UCLASS_RAM,
 645         .of_match = altera_gen5_sdram_ids,
 646         .ops = &altera_gen5_sdram_ops,
 647         .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
 648         .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata),
 649         .probe = altera_gen5_sdram_probe,
 650         .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv),
 651 };
 652
 653 #endif /* CONFIG_SPL_BUILD */