drivers/ddr/altera/sdram_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <wait_bit.h>
  14 #include <watchdog.h>
  15 #include <asm/cache.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/fpga_manager.h>
  18 #include <asm/arch/misc.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/arch/sdram.h>
  21 #include <linux/kernel.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static void sdram_mmr_init(void);
  26 static u64 sdram_size_calc(void);
  27
  28 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  29 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  30
  31 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  32         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  33 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  34 #define DDR_REG_SEQ2CORE        0xFFD0507C
  35 #define DDR_REG_CORE2SEQ        0xFFD05078
  36 #define DDR_READ_LATENCY_DELAY  40
  37 #define DDR_SIZE_2GB_HEX        0x80000000
  38
  39 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  40 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  41 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  42 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  43
  44 #define SEQ2CORE_MASK           0xF
  45 #define CORE2SEQ_INT_REQ        0xF
  46 #define SEQ2CORE_INT_RESP_BIT   3
  47
  48 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  49                 (void *)SOCFPGA_SDR_ADDRESS;
  50 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  51                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  52 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  53                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  54                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  55 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  56                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  57 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  58                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  59
  60 /* The following are the supported configurations */
  61 static u32 ddr_config[] = {
  62         /* Chip - Row - Bank - Column Style */
  63         /* All Types */
  64         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  65         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  66         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  67         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  68         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  69         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  70         /* LPDDR x16 */
  71         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  72         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  73         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  74         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  75         /* DDR4 Only */
  76         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  77         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  78         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  79         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  80         /* Chip - Bank - Row - Column Style */
  81         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  82         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  83         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  84         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  85         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  86         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  87         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  88         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  89         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  90         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  91         /* DDR4 Only */
  92         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  93         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  94         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  95         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  96 };
  97
  98 static int match_ddr_conf(u32 ddr_conf)
  99 {
 100         int i;
 101
 102         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
 103                 if (ddr_conf == ddr_config[i])
 104                         return i;
 105         }
 106         return 0;
 107 }
 108
 109 static int emif_clear(void)
 110 {
 111         writel(0, DDR_REG_CORE2SEQ);
 112
 113         return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 114                                 SEQ2CORE_MASK, 0, 1000, 0);
 115 }
 116
 117 static int emif_reset(void)
 118 {
 119         u32 c2s, s2c;
 120         int ret;
 121
 122         c2s = readl(DDR_REG_CORE2SEQ);
 123         s2c = readl(DDR_REG_SEQ2CORE);
 124
 125         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 126              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 127              readl(IO48_MMR_NIOS2_RESERVE1),
 128              readl(IO48_MMR_NIOS2_RESERVE2),
 129              readl(IO48_MMR_DRAMSTS));
 130
 131         if (s2c & SEQ2CORE_MASK) {
 132                 ret = emif_clear();
 133                 if (ret) {
 134                         debug("failed emif_clear()\n");
 135                         return -EPERM;
 136                 }
 137         }
 138
 139         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 140
 141         ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 142                                 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
 143         if (ret) {
 144                 debug("emif_reset failed to see interrupt acknowledge\n");
 145                 emif_clear();
 146                 return ret;
 147         }
 148
 149         mdelay(1);
 150
 151         ret = emif_clear();
 152         if (ret) {
 153                 debug("emif_clear() failed\n");
 154                 return -EPERM;
 155         }
 156         debug("emif_reset interrupt cleared\n");
 157
 158         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 159              readl(IO48_MMR_NIOS2_RESERVE0),
 160              readl(IO48_MMR_NIOS2_RESERVE1),
 161              readl(IO48_MMR_NIOS2_RESERVE2));
 162
 163         return 0;
 164 }
 165
 166 static int ddr_setup(void)
 167 {
 168         int i, ret;
 169
 170         /* Try 32 times to do a calibration */
 171         for (i = 0; i < 32; i++) {
 172                 mdelay(500);
 173                 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
 174                                         BIT(0), true, 500, false);
 175                 if (!ret)
 176                         return 0;
 177
 178                 ret = emif_reset();
 179                 if (ret)
 180                         puts("Error: Failed to reset EMIF\n");
 181         }
 182
 183         puts("Error: Could Not Calibrate SDRAM\n");
 184         return -EPERM;
 185 }
 186
 187 static int sdram_is_ecc_enabled(void)
 188 {
 189         return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
 190                   ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
 191 }
 192
 193 /* Initialize SDRAM ECC bits to avoid false DBE */
 194 static void sdram_init_ecc_bits(u32 size)
 195 {
 196         icache_enable();
 197
 198         memset(0, 0, 0x8000);
 199         gd->arch.tlb_addr = 0x4000;
 200         gd->arch.tlb_size = PGTABLE_SIZE;
 201
 202         dcache_enable();
 203
 204         printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
 205         memset((void *)0x8000, 0, size - 0x8000);
 206         flush_dcache_all();
 207         printf("DDRCAL: Scrubbing ECC RAM done.\n");
 208         dcache_disable();
 209 }
 210
 211 /* Function to startup the SDRAM*/
 212 static int sdram_startup(void)
 213 {
 214         /* Release NOC ddr scheduler from reset */
 215         socfpga_reset_deassert_noc_ddr_scheduler();
 216
 217         /* Bringup the DDR (calibration and configuration) */
 218         return ddr_setup();
 219 }
 220
 221 static u64 sdram_size_calc(void)
 222 {
 223         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 224
 225         u64 size = BIT(((dramaddrw &
 226                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 227                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 228                 ((dramaddrw &
 229                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 230                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 231                 ((dramaddrw &
 232                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 233                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 234                 ((dramaddrw &
 235                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 236                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 237                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 238
 239         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 240                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 241
 242         debug("SDRAM size=%llu\n", size);
 243
 244         return size;
 245 }
 246
 247 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 248 static void sdram_mmr_init(void)
 249 {
 250         u32 update_value, io48_value;
 251         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 252         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 253         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 254         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 255         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 256         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 257         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 258         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 259         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 260         u32 ddrioctl;
 261
 262         /*
 263          * Configure the DDR IO size [0xFFCFB008]
 264          * niosreserve0: Used to indicate DDR width &
 265          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 266          *      bit[8]   = 1 if user-mode OCT is present
 267          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 268          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 269          * niosreserve1: IP ADCDS version encoded as 16 bit value
 270          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 271          *                          3=EAP, 4-6 are reserved)
 272          *      bit[5:3] = Service Pack # (e.g. 1)
 273          *      bit[9:6] = Minor Release #
 274          *      bit[14:10] = Major Release #
 275          */
 276         if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 277                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 278                 writel(((update_value & 0xFF) >> 5),
 279                        &socfpga_ecc_hmc_base->ddrioctrl);
 280         }
 281
 282         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 283
 284         /* Set the DDR Configuration [0xFFD12400] */
 285         io48_value = ARRIA_DDR_CONFIG(
 286                         ((ctrlcfg1 &
 287                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 288                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 289                         ((dramaddrw &
 290                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 291                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 292                         ((dramaddrw &
 293                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 294                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 295                         (dramaddrw &
 296                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 297                         ((dramaddrw &
 298                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 299                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 300
 301         update_value = match_ddr_conf(io48_value);
 302         if (update_value)
 303                 writel(update_value,
 304                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 305
 306         /*
 307          * Configure DDR timing [0xFFD1240C]
 308          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 309          *  WRTOMISS = WL + tWR + tRP + tRCD and
 310          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 311          *  First part of equation is in memory clock units so divide by 2
 312          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 313          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 314          */
 315         u32 ctrlcfg0_cfg_ctrl_burst_len =
 316                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 317                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 318
 319         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 320                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 321
 322         u32 caltim0_cfg_act_to_act =
 323                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 324                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 325
 326         u32 caltim0_cfg_act_to_act_db =
 327                 (caltim0 &
 328                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 329                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 330
 331         u32 caltim1_cfg_rd_to_wr =
 332                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 333                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 334
 335         u32 caltim1_cfg_rd_to_rd_dc =
 336                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 337                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 338
 339         u32 caltim1_cfg_rd_to_wr_dc =
 340                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 341                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 342
 343         u32 caltim2_cfg_rd_to_pch =
 344                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 345                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 346
 347         u32 caltim3_cfg_wr_to_rd =
 348                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 349                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 350
 351         u32 caltim3_cfg_wr_to_rd_dc =
 352                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 353                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 354
 355         u32 caltim4_cfg_pch_to_valid =
 356                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 357                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 358
 359         u32 caltim9_cfg_4_act_to_act = caltim9 &
 360                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 361
 362         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 363                         caltim0_cfg_act_to_rdwr -
 364                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 365
 366         io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 367                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 368                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 369                       /* Up to here was in memory cycles so divide by 2 */
 370                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 371                       caltim4_cfg_pch_to_valid);
 372
 373         writel(((caltim0_cfg_act_to_act <<
 374                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 375                 (update_value <<
 376                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 377                 (io48_value <<
 378                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 379                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 380                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 381                 (caltim1_cfg_rd_to_wr <<
 382                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 383                 (caltim3_cfg_wr_to_rd <<
 384                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 385                 (((ddrioctl == 1) ? 1 : 0) <<
 386                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 387                 &socfpga_noc_ddr_scheduler_base->
 388                         ddr_t_main_scheduler_ddrtiming);
 389
 390         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 391         writel(((ddrioctl ? 0 : 1) <<
 392                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 393                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 394
 395         /* Configure the read latency [0xFFD12414] */
 396         writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 397                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 398                 DDR_READ_LATENCY_DELAY,
 399                 &socfpga_noc_ddr_scheduler_base->
 400                         ddr_t_main_scheduler_readlatency);
 401
 402         /*
 403          * Configuring timing values concerning activate commands
 404          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 405          */
 406         writel(((caltim0_cfg_act_to_act_db <<
 407                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 408                 (caltim9_cfg_4_act_to_act <<
 409                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 410                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 411                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 412                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 413
 414         /*
 415          * Configuring timing values concerning device to device data bus
 416          * ownership change [0xFFD1243C]
 417          */
 418         writel(((caltim1_cfg_rd_to_rd_dc <<
 419                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 420                 (caltim1_cfg_rd_to_wr_dc <<
 421                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 422                 (caltim3_cfg_wr_to_rd_dc <<
 423                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 424                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 425
 426         /* Enable or disable the SDRAM ECC */
 427         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 428                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 429                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 430                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 431                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 432                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 433                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 434                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 435                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 436                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 437                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 438         } else {
 439                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 440                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 441                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 442                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 443                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 444                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 445                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 446         }
 447 }
 448
 449 struct firewall_entry {
 450         const char *prop_name;
 451         const u32 cfg_addr;
 452         const u32 en_addr;
 453         const u32 en_bit;
 454 };
 455 #define FW_MPU_FPGA_ADDRESS \
 456         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 457         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 458
 459 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 460                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 461                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 462
 463 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 464                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 465                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 466
 467 const struct firewall_entry firewall_table[] = {
 468         {
 469                 "mpu0",
 470                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 471                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 472                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 473         },
 474         {
 475                 "mpu1",
 476                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 477                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 478                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 479                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 480         },
 481         {
 482                 "mpu2",
 483                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 484                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 485                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 486         },
 487         {
 488                 "mpu3",
 489                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 490                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 491                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 492         },
 493         {
 494                 "l3-0",
 495                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 496                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 497                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 498         },
 499         {
 500                 "l3-1",
 501                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 502                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 503                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 504         },
 505         {
 506                 "l3-2",
 507                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 508                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 509                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 510         },
 511         {
 512                 "l3-3",
 513                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 514                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 515                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 516         },
 517         {
 518                 "l3-4",
 519                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 520                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 521                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 522         },
 523         {
 524                 "l3-5",
 525                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 526                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 527                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 528         },
 529         {
 530                 "l3-6",
 531                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 532                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 533                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 534         },
 535         {
 536                 "l3-7",
 537                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 538                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 539                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 540         },
 541         {
 542                 "fpga2sdram0-0",
 543                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 544                 (fpga2sdram0region0addr),
 545                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 546                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 547         },
 548         {
 549                 "fpga2sdram0-1",
 550                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 551                 (fpga2sdram0region1addr),
 552                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 553                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 554         },
 555         {
 556                 "fpga2sdram0-2",
 557                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 558                 (fpga2sdram0region2addr),
 559                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 560                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 561         },
 562         {
 563                 "fpga2sdram0-3",
 564                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 565                 (fpga2sdram0region3addr),
 566                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 567                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 568         },
 569         {
 570                 "fpga2sdram1-0",
 571                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 572                 (fpga2sdram1region0addr),
 573                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 574                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 575         },
 576         {
 577                 "fpga2sdram1-1",
 578                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 579                 (fpga2sdram1region1addr),
 580                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 581                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 582         },
 583         {
 584                 "fpga2sdram1-2",
 585                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 586                 (fpga2sdram1region2addr),
 587                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 588                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 589         },
 590         {
 591                 "fpga2sdram1-3",
 592                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 593                 (fpga2sdram1region3addr),
 594                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 595                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 596         },
 597         {
 598                 "fpga2sdram2-0",
 599                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 600                 (fpga2sdram2region0addr),
 601                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 602                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 603         },
 604         {
 605                 "fpga2sdram2-1",
 606                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 607                 (fpga2sdram2region1addr),
 608                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 609                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 610         },
 611         {
 612                 "fpga2sdram2-2",
 613                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 614                 (fpga2sdram2region2addr),
 615                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 616                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 617         },
 618         {
 619                 "fpga2sdram2-3",
 620                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 621                 (fpga2sdram2region3addr),
 622                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 623                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 624         },
 625
 626 };
 627
 628 static int of_sdram_firewall_setup(const void *blob)
 629 {
 630         int child, i, node, ret;
 631         u32 start_end[2];
 632         char name[32];
 633
 634         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 635         if (node < 0)
 636                 return -ENXIO;
 637
 638         child = fdt_first_subnode(blob, node);
 639         if (child < 0)
 640                 return -ENXIO;
 641
 642         /* set to default state */
 643         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 644         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 645
 646
 647         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 648                 sprintf(name, "%s", firewall_table[i].prop_name);
 649                 ret = fdtdec_get_int_array(blob, child, name,
 650                                            start_end, 2);
 651                 if (ret) {
 652                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 653                         ret = fdtdec_get_int_array(blob, child, name,
 654                                                    start_end, 2);
 655                         if (ret)
 656                                 continue;
 657                 }
 658
 659                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 660                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 661                        firewall_table[i].cfg_addr);
 662                 setbits_le32(firewall_table[i].en_addr,
 663                              firewall_table[i].en_bit);
 664         }
 665
 666         return 0;
 667 }
 668
 669 int ddr_calibration_sequence(void)
 670 {
 671         WATCHDOG_RESET();
 672
 673         /* Check to see if SDRAM cal was success */
 674         if (sdram_startup()) {
 675                 puts("DDRCAL: Failed\n");
 676                 return -EPERM;
 677         }
 678
 679         puts("DDRCAL: Success\n");
 680
 681         WATCHDOG_RESET();
 682
 683         /* initialize the MMR register */
 684         sdram_mmr_init();
 685
 686         /* assigning the SDRAM size */
 687         u64 size = sdram_size_calc();
 688
 689         /*
 690          * If size is less than zero, this is invalid/weird value from
 691          * calculation, use default Config size.
 692          * Up to 2GB is supported, 2GB would be used if more than that.
 693          */
 694         if (size <= 0)
 695                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 696         else if (DDR_SIZE_2GB_HEX <= size)
 697                 gd->ram_size = DDR_SIZE_2GB_HEX;
 698         else
 699                 gd->ram_size = (u32)size;
 700
 701         /* setup the dram info within bd */
 702         dram_init_banksize();
 703
 704         if (of_sdram_firewall_setup(gd->fdt_blob))
 705                 puts("FW: Error Configuring Firewall\n");
 706
 707         if (sdram_is_ecc_enabled())
 708                 sdram_init_ecc_bits(gd->ram_size);
 709
 710         return 0;
 711 }