drivers/ddr/altera/sdram_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <wait_bit.h>
  12 #include <watchdog.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/fpga_manager.h>
  15 #include <asm/arch/misc.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/sdram.h>
  18 #include <linux/kernel.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static void sdram_mmr_init(void);
  23 static u64 sdram_size_calc(void);
  24
  25 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  26 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  27
  28 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  29         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  30 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  31 #define DDR_REG_SEQ2CORE        0xFFD0507C
  32 #define DDR_REG_CORE2SEQ        0xFFD05078
  33 #define DDR_READ_LATENCY_DELAY  40
  34 #define DDR_SIZE_2GB_HEX        0x80000000
  35
  36 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  37 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  38 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  39 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  40
  41 #define SEQ2CORE_MASK           0xF
  42 #define CORE2SEQ_INT_REQ        0xF
  43 #define SEQ2CORE_INT_RESP_BIT   3
  44
  45 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  46                 (void *)SOCFPGA_SDR_ADDRESS;
  47 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  48                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  49 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  50                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  51                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  52 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  53                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  54 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  55                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  56
  57 /* The following are the supported configurations */
  58 static u32 ddr_config[] = {
  59         /* Chip - Row - Bank - Column Style */
  60         /* All Types */
  61         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  62         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  63         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  64         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  65         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  66         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  67         /* LPDDR x16 */
  68         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  69         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  70         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  71         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  72         /* DDR4 Only */
  73         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  74         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  75         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  76         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  77         /* Chip - Bank - Row - Column Style */
  78         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  79         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  80         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  81         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  82         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  83         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  84         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  85         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  86         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  87         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  88         /* DDR4 Only */
  89         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  90         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  91         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  92         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  93 };
  94
  95 static int match_ddr_conf(u32 ddr_conf)
  96 {
  97         int i;
  98
  99         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
 100                 if (ddr_conf == ddr_config[i])
 101                         return i;
 102         }
 103         return 0;
 104 }
 105
 106 static int emif_clear(void)
 107 {
 108         writel(0, DDR_REG_CORE2SEQ);
 109
 110         return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 111                                 SEQ2CORE_MASK, 0, 1000, 0);
 112 }
 113
 114 static int emif_reset(void)
 115 {
 116         u32 c2s, s2c;
 117         int ret;
 118
 119         c2s = readl(DDR_REG_CORE2SEQ);
 120         s2c = readl(DDR_REG_SEQ2CORE);
 121
 122         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 123              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 124              readl(IO48_MMR_NIOS2_RESERVE1),
 125              readl(IO48_MMR_NIOS2_RESERVE2),
 126              readl(IO48_MMR_DRAMSTS));
 127
 128         if (s2c & SEQ2CORE_MASK) {
 129                 ret = emif_clear();
 130                 if (ret) {
 131                         debug("failed emif_clear()\n");
 132                         return -EPERM;
 133                 }
 134         }
 135
 136         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 137
 138         ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 139                                 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
 140         if (ret) {
 141                 debug("emif_reset failed to see interrupt acknowledge\n");
 142                 emif_clear();
 143                 return ret;
 144         }
 145
 146         mdelay(1);
 147
 148         ret = emif_clear();
 149         if (ret) {
 150                 debug("emif_clear() failed\n");
 151                 return -EPERM;
 152         }
 153         debug("emif_reset interrupt cleared\n");
 154
 155         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 156              readl(IO48_MMR_NIOS2_RESERVE0),
 157              readl(IO48_MMR_NIOS2_RESERVE1),
 158              readl(IO48_MMR_NIOS2_RESERVE2));
 159
 160         return 0;
 161 }
 162
 163 static int ddr_setup(void)
 164 {
 165         int i, ret;
 166
 167         /* Try 32 times to do a calibration */
 168         for (i = 0; i < 32; i++) {
 169                 mdelay(500);
 170                 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
 171                                         BIT(0), true, 500, false);
 172                 if (!ret)
 173                         return 0;
 174
 175                 ret = emif_reset();
 176                 if (ret)
 177                         puts("Error: Failed to reset EMIF\n");
 178         }
 179
 180         puts("Error: Could Not Calibrate SDRAM\n");
 181         return -EPERM;
 182 }
 183
 184 static int sdram_is_ecc_enabled(void)
 185 {
 186         return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
 187                   ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
 188 }
 189
 190 /* Initialize SDRAM ECC bits to avoid false DBE */
 191 static void sdram_init_ecc_bits(u32 size)
 192 {
 193         icache_enable();
 194
 195         memset(0, 0, 0x8000);
 196         gd->arch.tlb_addr = 0x4000;
 197         gd->arch.tlb_size = PGTABLE_SIZE;
 198
 199         dcache_enable();
 200
 201         printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
 202         memset((void *)0x8000, 0, size - 0x8000);
 203         flush_dcache_all();
 204         printf("DDRCAL: Scrubbing ECC RAM done.\n");
 205         dcache_disable();
 206 }
 207
 208 /* Function to startup the SDRAM*/
 209 static int sdram_startup(void)
 210 {
 211         /* Release NOC ddr scheduler from reset */
 212         socfpga_reset_deassert_noc_ddr_scheduler();
 213
 214         /* Bringup the DDR (calibration and configuration) */
 215         return ddr_setup();
 216 }
 217
 218 static u64 sdram_size_calc(void)
 219 {
 220         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 221
 222         u64 size = BIT(((dramaddrw &
 223                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 224                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 225                 ((dramaddrw &
 226                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 227                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 228                 ((dramaddrw &
 229                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 230                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 231                 ((dramaddrw &
 232                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 233                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 234                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 235
 236         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 237                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 238
 239         debug("SDRAM size=%llu\n", size);
 240
 241         return size;
 242 }
 243
 244 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 245 static void sdram_mmr_init(void)
 246 {
 247         u32 update_value, io48_value;
 248         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 249         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 250         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 251         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 252         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 253         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 254         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 255         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 256         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 257         u32 ddrioctl;
 258
 259         /*
 260          * Configure the DDR IO size [0xFFCFB008]
 261          * niosreserve0: Used to indicate DDR width &
 262          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 263          *      bit[8]   = 1 if user-mode OCT is present
 264          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 265          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 266          * niosreserve1: IP ADCDS version encoded as 16 bit value
 267          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 268          *                          3=EAP, 4-6 are reserved)
 269          *      bit[5:3] = Service Pack # (e.g. 1)
 270          *      bit[9:6] = Minor Release #
 271          *      bit[14:10] = Major Release #
 272          */
 273         if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 274                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 275                 writel(((update_value & 0xFF) >> 5),
 276                        &socfpga_ecc_hmc_base->ddrioctrl);
 277         }
 278
 279         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 280
 281         /* Set the DDR Configuration [0xFFD12400] */
 282         io48_value = ARRIA_DDR_CONFIG(
 283                         ((ctrlcfg1 &
 284                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 285                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 286                         ((dramaddrw &
 287                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 288                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 289                         ((dramaddrw &
 290                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 291                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 292                         (dramaddrw &
 293                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 294                         ((dramaddrw &
 295                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 296                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 297
 298         update_value = match_ddr_conf(io48_value);
 299         if (update_value)
 300                 writel(update_value,
 301                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 302
 303         /*
 304          * Configure DDR timing [0xFFD1240C]
 305          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 306          *  WRTOMISS = WL + tWR + tRP + tRCD and
 307          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 308          *  First part of equation is in memory clock units so divide by 2
 309          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 310          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 311          */
 312         u32 ctrlcfg0_cfg_ctrl_burst_len =
 313                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 314                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 315
 316         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 317                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 318
 319         u32 caltim0_cfg_act_to_act =
 320                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 321                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 322
 323         u32 caltim0_cfg_act_to_act_db =
 324                 (caltim0 &
 325                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 326                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 327
 328         u32 caltim1_cfg_rd_to_wr =
 329                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 330                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 331
 332         u32 caltim1_cfg_rd_to_rd_dc =
 333                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 334                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 335
 336         u32 caltim1_cfg_rd_to_wr_dc =
 337                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 338                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 339
 340         u32 caltim2_cfg_rd_to_pch =
 341                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 342                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 343
 344         u32 caltim3_cfg_wr_to_rd =
 345                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 346                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 347
 348         u32 caltim3_cfg_wr_to_rd_dc =
 349                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 350                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 351
 352         u32 caltim4_cfg_pch_to_valid =
 353                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 354                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 355
 356         u32 caltim9_cfg_4_act_to_act = caltim9 &
 357                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 358
 359         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 360                         caltim0_cfg_act_to_rdwr -
 361                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 362
 363         io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 364                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 365                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 366                       /* Up to here was in memory cycles so divide by 2 */
 367                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 368                       caltim4_cfg_pch_to_valid);
 369
 370         writel(((caltim0_cfg_act_to_act <<
 371                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 372                 (update_value <<
 373                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 374                 (io48_value <<
 375                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 376                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 377                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 378                 (caltim1_cfg_rd_to_wr <<
 379                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 380                 (caltim3_cfg_wr_to_rd <<
 381                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 382                 (((ddrioctl == 1) ? 1 : 0) <<
 383                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 384                 &socfpga_noc_ddr_scheduler_base->
 385                         ddr_t_main_scheduler_ddrtiming);
 386
 387         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 388         writel(((ddrioctl ? 0 : 1) <<
 389                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 390                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 391
 392         /* Configure the read latency [0xFFD12414] */
 393         writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 394                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 395                 DDR_READ_LATENCY_DELAY,
 396                 &socfpga_noc_ddr_scheduler_base->
 397                         ddr_t_main_scheduler_readlatency);
 398
 399         /*
 400          * Configuring timing values concerning activate commands
 401          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 402          */
 403         writel(((caltim0_cfg_act_to_act_db <<
 404                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 405                 (caltim9_cfg_4_act_to_act <<
 406                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 407                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 408                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 409                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 410
 411         /*
 412          * Configuring timing values concerning device to device data bus
 413          * ownership change [0xFFD1243C]
 414          */
 415         writel(((caltim1_cfg_rd_to_rd_dc <<
 416                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 417                 (caltim1_cfg_rd_to_wr_dc <<
 418                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 419                 (caltim3_cfg_wr_to_rd_dc <<
 420                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 421                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 422
 423         /* Enable or disable the SDRAM ECC */
 424         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 425                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 426                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 427                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 428                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 429                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 430                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 431                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 432                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 433                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 434                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 435         } else {
 436                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 437                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 438                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 439                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 440                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 441                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 442                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 443         }
 444 }
 445
 446 struct firewall_entry {
 447         const char *prop_name;
 448         const u32 cfg_addr;
 449         const u32 en_addr;
 450         const u32 en_bit;
 451 };
 452 #define FW_MPU_FPGA_ADDRESS \
 453         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 454         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 455
 456 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 457                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 458                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 459
 460 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 461                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 462                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 463
 464 const struct firewall_entry firewall_table[] = {
 465         {
 466                 "mpu0",
 467                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 468                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 469                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 470         },
 471         {
 472                 "mpu1",
 473                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 474                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 475                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 476                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 477         },
 478         {
 479                 "mpu2",
 480                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 481                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 482                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 483         },
 484         {
 485                 "mpu3",
 486                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 487                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 488                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 489         },
 490         {
 491                 "l3-0",
 492                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 493                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 494                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 495         },
 496         {
 497                 "l3-1",
 498                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 499                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 500                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 501         },
 502         {
 503                 "l3-2",
 504                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 505                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 506                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 507         },
 508         {
 509                 "l3-3",
 510                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 511                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 512                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 513         },
 514         {
 515                 "l3-4",
 516                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 517                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 518                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 519         },
 520         {
 521                 "l3-5",
 522                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 523                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 524                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 525         },
 526         {
 527                 "l3-6",
 528                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 529                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 530                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 531         },
 532         {
 533                 "l3-7",
 534                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 535                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 536                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 537         },
 538         {
 539                 "fpga2sdram0-0",
 540                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 541                 (fpga2sdram0region0addr),
 542                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 543                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 544         },
 545         {
 546                 "fpga2sdram0-1",
 547                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 548                 (fpga2sdram0region1addr),
 549                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 550                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 551         },
 552         {
 553                 "fpga2sdram0-2",
 554                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 555                 (fpga2sdram0region2addr),
 556                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 557                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 558         },
 559         {
 560                 "fpga2sdram0-3",
 561                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 562                 (fpga2sdram0region3addr),
 563                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 564                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 565         },
 566         {
 567                 "fpga2sdram1-0",
 568                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 569                 (fpga2sdram1region0addr),
 570                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 571                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 572         },
 573         {
 574                 "fpga2sdram1-1",
 575                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 576                 (fpga2sdram1region1addr),
 577                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 578                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 579         },
 580         {
 581                 "fpga2sdram1-2",
 582                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 583                 (fpga2sdram1region2addr),
 584                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 585                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 586         },
 587         {
 588                 "fpga2sdram1-3",
 589                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 590                 (fpga2sdram1region3addr),
 591                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 592                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 593         },
 594         {
 595                 "fpga2sdram2-0",
 596                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 597                 (fpga2sdram2region0addr),
 598                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 599                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 600         },
 601         {
 602                 "fpga2sdram2-1",
 603                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 604                 (fpga2sdram2region1addr),
 605                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 606                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 607         },
 608         {
 609                 "fpga2sdram2-2",
 610                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 611                 (fpga2sdram2region2addr),
 612                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 613                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 614         },
 615         {
 616                 "fpga2sdram2-3",
 617                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 618                 (fpga2sdram2region3addr),
 619                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 620                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 621         },
 622
 623 };
 624
 625 static int of_sdram_firewall_setup(const void *blob)
 626 {
 627         int child, i, node, ret;
 628         u32 start_end[2];
 629         char name[32];
 630
 631         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 632         if (node < 0)
 633                 return -ENXIO;
 634
 635         child = fdt_first_subnode(blob, node);
 636         if (child < 0)
 637                 return -ENXIO;
 638
 639         /* set to default state */
 640         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 641         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 642
 643
 644         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 645                 sprintf(name, "%s", firewall_table[i].prop_name);
 646                 ret = fdtdec_get_int_array(blob, child, name,
 647                                            start_end, 2);
 648                 if (ret) {
 649                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 650                         ret = fdtdec_get_int_array(blob, child, name,
 651                                                    start_end, 2);
 652                         if (ret)
 653                                 continue;
 654                 }
 655
 656                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 657                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 658                        firewall_table[i].cfg_addr);
 659                 setbits_le32(firewall_table[i].en_addr,
 660                              firewall_table[i].en_bit);
 661         }
 662
 663         return 0;
 664 }
 665
 666 int ddr_calibration_sequence(void)
 667 {
 668         WATCHDOG_RESET();
 669
 670         /* Check to see if SDRAM cal was success */
 671         if (sdram_startup()) {
 672                 puts("DDRCAL: Failed\n");
 673                 return -EPERM;
 674         }
 675
 676         puts("DDRCAL: Success\n");
 677
 678         WATCHDOG_RESET();
 679
 680         /* initialize the MMR register */
 681         sdram_mmr_init();
 682
 683         /* assigning the SDRAM size */
 684         u64 size = sdram_size_calc();
 685
 686         /*
 687          * If size is less than zero, this is invalid/weird value from
 688          * calculation, use default Config size.
 689          * Up to 2GB is supported, 2GB would be used if more than that.
 690          */
 691         if (size <= 0)
 692                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 693         else if (DDR_SIZE_2GB_HEX <= size)
 694                 gd->ram_size = DDR_SIZE_2GB_HEX;
 695         else
 696                 gd->ram_size = (u32)size;
 697
 698         /* setup the dram info within bd */
 699         dram_init_banksize();
 700
 701         if (of_sdram_firewall_setup(gd->fdt_blob))
 702                 puts("FW: Error Configuring Firewall\n");
 703
 704         if (sdram_is_ecc_enabled())
 705                 sdram_init_ecc_bits(gd->ram_size);
 706
 707         return 0;
 708 }