drivers/ddr/altera/sdram_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <wait_bit.h>
  14 #include <watchdog.h>
  15 #include <asm/cache.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/fpga_manager.h>
  18 #include <asm/arch/misc.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/arch/sdram.h>
  21 #include <linux/delay.h>
  22 #include <linux/kernel.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static void sdram_mmr_init(void);
  27 static u64 sdram_size_calc(void);
  28
  29 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  30 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  31
  32 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  33         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  34 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  35 #define DDR_REG_SEQ2CORE        0xFFD0507C
  36 #define DDR_REG_CORE2SEQ        0xFFD05078
  37 #define DDR_READ_LATENCY_DELAY  40
  38 #define DDR_SIZE_2GB_HEX        0x80000000
  39
  40 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  41 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  42 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  43 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  44
  45 #define SEQ2CORE_MASK           0xF
  46 #define CORE2SEQ_INT_REQ        0xF
  47 #define SEQ2CORE_INT_RESP_BIT   3
  48
  49 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  50                 (void *)SOCFPGA_SDR_ADDRESS;
  51 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  52                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  53 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  54                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  55                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  56 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  57                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  58 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  59                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  60
  61 /* The following are the supported configurations */
  62 static u32 ddr_config[] = {
  63         /* Chip - Row - Bank - Column Style */
  64         /* All Types */
  65         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  66         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  67         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  68         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  69         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  70         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  71         /* LPDDR x16 */
  72         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  73         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  74         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  75         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  76         /* DDR4 Only */
  77         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  78         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  79         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  80         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  81         /* Chip - Bank - Row - Column Style */
  82         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  83         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  84         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  85         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  86         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  87         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  88         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  89         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  90         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  91         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  92         /* DDR4 Only */
  93         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  94         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  95         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  96         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  97 };
  98
  99 static int match_ddr_conf(u32 ddr_conf)
 100 {
 101         int i;
 102
 103         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
 104                 if (ddr_conf == ddr_config[i])
 105                         return i;
 106         }
 107         return 0;
 108 }
 109
 110 static int emif_clear(void)
 111 {
 112         writel(0, DDR_REG_CORE2SEQ);
 113
 114         return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 115                                 SEQ2CORE_MASK, 0, 1000, 0);
 116 }
 117
 118 static int emif_reset(void)
 119 {
 120         u32 c2s, s2c;
 121         int ret;
 122
 123         c2s = readl(DDR_REG_CORE2SEQ);
 124         s2c = readl(DDR_REG_SEQ2CORE);
 125
 126         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 127              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 128              readl(IO48_MMR_NIOS2_RESERVE1),
 129              readl(IO48_MMR_NIOS2_RESERVE2),
 130              readl(IO48_MMR_DRAMSTS));
 131
 132         if (s2c & SEQ2CORE_MASK) {
 133                 ret = emif_clear();
 134                 if (ret) {
 135                         debug("failed emif_clear()\n");
 136                         return -EPERM;
 137                 }
 138         }
 139
 140         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 141
 142         ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 143                                 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
 144         if (ret) {
 145                 debug("emif_reset failed to see interrupt acknowledge\n");
 146                 emif_clear();
 147                 return ret;
 148         }
 149
 150         mdelay(1);
 151
 152         ret = emif_clear();
 153         if (ret) {
 154                 debug("emif_clear() failed\n");
 155                 return -EPERM;
 156         }
 157         debug("emif_reset interrupt cleared\n");
 158
 159         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 160              readl(IO48_MMR_NIOS2_RESERVE0),
 161              readl(IO48_MMR_NIOS2_RESERVE1),
 162              readl(IO48_MMR_NIOS2_RESERVE2));
 163
 164         return 0;
 165 }
 166
 167 static int ddr_setup(void)
 168 {
 169         int i, ret;
 170
 171         /* Try 32 times to do a calibration */
 172         for (i = 0; i < 32; i++) {
 173                 mdelay(500);
 174                 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
 175                                         BIT(0), true, 500, false);
 176                 if (!ret)
 177                         return 0;
 178
 179                 ret = emif_reset();
 180                 if (ret)
 181                         puts("Error: Failed to reset EMIF\n");
 182         }
 183
 184         puts("Error: Could Not Calibrate SDRAM\n");
 185         return -EPERM;
 186 }
 187
 188 static int sdram_is_ecc_enabled(void)
 189 {
 190         return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
 191                   ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
 192 }
 193
 194 /* Initialize SDRAM ECC bits to avoid false DBE */
 195 static void sdram_init_ecc_bits(u32 size)
 196 {
 197         icache_enable();
 198
 199         memset(0, 0, 0x8000);
 200         gd->arch.tlb_addr = 0x4000;
 201         gd->arch.tlb_size = PGTABLE_SIZE;
 202
 203         dcache_enable();
 204
 205         printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
 206         memset((void *)0x8000, 0, size - 0x8000);
 207         flush_dcache_all();
 208         printf("DDRCAL: Scrubbing ECC RAM done.\n");
 209         dcache_disable();
 210 }
 211
 212 /* Function to startup the SDRAM*/
 213 static int sdram_startup(void)
 214 {
 215         /* Release NOC ddr scheduler from reset */
 216         socfpga_reset_deassert_noc_ddr_scheduler();
 217
 218         /* Bringup the DDR (calibration and configuration) */
 219         return ddr_setup();
 220 }
 221
 222 static u64 sdram_size_calc(void)
 223 {
 224         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 225
 226         u64 size = BIT(((dramaddrw &
 227                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 228                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 229                 ((dramaddrw &
 230                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 231                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 232                 ((dramaddrw &
 233                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 234                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 235                 ((dramaddrw &
 236                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 237                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 238                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 239
 240         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 241                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 242
 243         debug("SDRAM size=%llu\n", size);
 244
 245         return size;
 246 }
 247
 248 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 249 static void sdram_mmr_init(void)
 250 {
 251         u32 update_value, io48_value;
 252         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 253         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 254         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 255         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 256         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 257         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 258         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 259         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 260         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 261         u32 ddrioctl;
 262
 263         /*
 264          * Configure the DDR IO size [0xFFCFB008]
 265          * niosreserve0: Used to indicate DDR width &
 266          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 267          *      bit[8]   = 1 if user-mode OCT is present
 268          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 269          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 270          * niosreserve1: IP ADCDS version encoded as 16 bit value
 271          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 272          *                          3=EAP, 4-6 are reserved)
 273          *      bit[5:3] = Service Pack # (e.g. 1)
 274          *      bit[9:6] = Minor Release #
 275          *      bit[14:10] = Major Release #
 276          */
 277         if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 278                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 279                 writel(((update_value & 0xFF) >> 5),
 280                        &socfpga_ecc_hmc_base->ddrioctrl);
 281         }
 282
 283         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 284
 285         /* Set the DDR Configuration [0xFFD12400] */
 286         io48_value = ARRIA_DDR_CONFIG(
 287                         ((ctrlcfg1 &
 288                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 289                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 290                         ((dramaddrw &
 291                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 292                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 293                         ((dramaddrw &
 294                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 295                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 296                         (dramaddrw &
 297                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 298                         ((dramaddrw &
 299                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 300                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 301
 302         update_value = match_ddr_conf(io48_value);
 303         if (update_value)
 304                 writel(update_value,
 305                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 306
 307         /*
 308          * Configure DDR timing [0xFFD1240C]
 309          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 310          *  WRTOMISS = WL + tWR + tRP + tRCD and
 311          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 312          *  First part of equation is in memory clock units so divide by 2
 313          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 314          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 315          */
 316         u32 ctrlcfg0_cfg_ctrl_burst_len =
 317                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 318                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 319
 320         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 321                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 322
 323         u32 caltim0_cfg_act_to_act =
 324                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 325                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 326
 327         u32 caltim0_cfg_act_to_act_db =
 328                 (caltim0 &
 329                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 330                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 331
 332         u32 caltim1_cfg_rd_to_wr =
 333                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 334                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 335
 336         u32 caltim1_cfg_rd_to_rd_dc =
 337                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 338                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 339
 340         u32 caltim1_cfg_rd_to_wr_dc =
 341                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 342                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 343
 344         u32 caltim2_cfg_rd_to_pch =
 345                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 346                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 347
 348         u32 caltim3_cfg_wr_to_rd =
 349                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 350                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 351
 352         u32 caltim3_cfg_wr_to_rd_dc =
 353                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 354                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 355
 356         u32 caltim4_cfg_pch_to_valid =
 357                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 358                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 359
 360         u32 caltim9_cfg_4_act_to_act = caltim9 &
 361                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 362
 363         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 364                         caltim0_cfg_act_to_rdwr -
 365                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 366
 367         io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 368                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 369                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 370                       /* Up to here was in memory cycles so divide by 2 */
 371                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 372                       caltim4_cfg_pch_to_valid);
 373
 374         writel(((caltim0_cfg_act_to_act <<
 375                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 376                 (update_value <<
 377                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 378                 (io48_value <<
 379                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 380                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 381                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 382                 (caltim1_cfg_rd_to_wr <<
 383                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 384                 (caltim3_cfg_wr_to_rd <<
 385                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 386                 (((ddrioctl == 1) ? 1 : 0) <<
 387                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 388                 &socfpga_noc_ddr_scheduler_base->
 389                         ddr_t_main_scheduler_ddrtiming);
 390
 391         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 392         writel(((ddrioctl ? 0 : 1) <<
 393                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 394                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 395
 396         /* Configure the read latency [0xFFD12414] */
 397         writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 398                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 399                 DDR_READ_LATENCY_DELAY,
 400                 &socfpga_noc_ddr_scheduler_base->
 401                         ddr_t_main_scheduler_readlatency);
 402
 403         /*
 404          * Configuring timing values concerning activate commands
 405          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 406          */
 407         writel(((caltim0_cfg_act_to_act_db <<
 408                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 409                 (caltim9_cfg_4_act_to_act <<
 410                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 411                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 412                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 413                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 414
 415         /*
 416          * Configuring timing values concerning device to device data bus
 417          * ownership change [0xFFD1243C]
 418          */
 419         writel(((caltim1_cfg_rd_to_rd_dc <<
 420                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 421                 (caltim1_cfg_rd_to_wr_dc <<
 422                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 423                 (caltim3_cfg_wr_to_rd_dc <<
 424                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 425                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 426
 427         /* Enable or disable the SDRAM ECC */
 428         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 429                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 430                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 431                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 432                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 433                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 434                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 435                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 436                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 437                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 438                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 439         } else {
 440                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 441                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 442                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 443                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 444                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 445                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 446                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 447         }
 448 }
 449
 450 struct firewall_entry {
 451         const char *prop_name;
 452         const u32 cfg_addr;
 453         const u32 en_addr;
 454         const u32 en_bit;
 455 };
 456 #define FW_MPU_FPGA_ADDRESS \
 457         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 458         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 459
 460 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 461                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 462                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 463
 464 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 465                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 466                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 467
 468 const struct firewall_entry firewall_table[] = {
 469         {
 470                 "mpu0",
 471                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 472                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 473                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 474         },
 475         {
 476                 "mpu1",
 477                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 478                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 479                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 480                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 481         },
 482         {
 483                 "mpu2",
 484                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 485                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 486                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 487         },
 488         {
 489                 "mpu3",
 490                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 491                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 492                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 493         },
 494         {
 495                 "l3-0",
 496                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 497                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 498                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 499         },
 500         {
 501                 "l3-1",
 502                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 503                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 504                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 505         },
 506         {
 507                 "l3-2",
 508                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 509                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 510                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 511         },
 512         {
 513                 "l3-3",
 514                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 515                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 516                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 517         },
 518         {
 519                 "l3-4",
 520                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 521                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 522                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 523         },
 524         {
 525                 "l3-5",
 526                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 527                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 528                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 529         },
 530         {
 531                 "l3-6",
 532                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 533                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 534                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 535         },
 536         {
 537                 "l3-7",
 538                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 539                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 540                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 541         },
 542         {
 543                 "fpga2sdram0-0",
 544                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 545                 (fpga2sdram0region0addr),
 546                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 547                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 548         },
 549         {
 550                 "fpga2sdram0-1",
 551                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 552                 (fpga2sdram0region1addr),
 553                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 554                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 555         },
 556         {
 557                 "fpga2sdram0-2",
 558                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 559                 (fpga2sdram0region2addr),
 560                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 561                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 562         },
 563         {
 564                 "fpga2sdram0-3",
 565                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 566                 (fpga2sdram0region3addr),
 567                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 568                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 569         },
 570         {
 571                 "fpga2sdram1-0",
 572                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 573                 (fpga2sdram1region0addr),
 574                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 575                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 576         },
 577         {
 578                 "fpga2sdram1-1",
 579                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 580                 (fpga2sdram1region1addr),
 581                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 582                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 583         },
 584         {
 585                 "fpga2sdram1-2",
 586                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 587                 (fpga2sdram1region2addr),
 588                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 589                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 590         },
 591         {
 592                 "fpga2sdram1-3",
 593                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 594                 (fpga2sdram1region3addr),
 595                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 596                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 597         },
 598         {
 599                 "fpga2sdram2-0",
 600                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 601                 (fpga2sdram2region0addr),
 602                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 603                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 604         },
 605         {
 606                 "fpga2sdram2-1",
 607                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 608                 (fpga2sdram2region1addr),
 609                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 610                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 611         },
 612         {
 613                 "fpga2sdram2-2",
 614                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 615                 (fpga2sdram2region2addr),
 616                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 617                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 618         },
 619         {
 620                 "fpga2sdram2-3",
 621                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 622                 (fpga2sdram2region3addr),
 623                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 624                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 625         },
 626
 627 };
 628
 629 static int of_sdram_firewall_setup(const void *blob)
 630 {
 631         int child, i, node, ret;
 632         u32 start_end[2];
 633         char name[32];
 634
 635         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 636         if (node < 0)
 637                 return -ENXIO;
 638
 639         child = fdt_first_subnode(blob, node);
 640         if (child < 0)
 641                 return -ENXIO;
 642
 643         /* set to default state */
 644         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 645         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 646
 647
 648         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 649                 sprintf(name, "%s", firewall_table[i].prop_name);
 650                 ret = fdtdec_get_int_array(blob, child, name,
 651                                            start_end, 2);
 652                 if (ret) {
 653                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 654                         ret = fdtdec_get_int_array(blob, child, name,
 655                                                    start_end, 2);
 656                         if (ret)
 657                                 continue;
 658                 }
 659
 660                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 661                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 662                        firewall_table[i].cfg_addr);
 663                 setbits_le32(firewall_table[i].en_addr,
 664                              firewall_table[i].en_bit);
 665         }
 666
 667         return 0;
 668 }
 669
 670 int ddr_calibration_sequence(void)
 671 {
 672         WATCHDOG_RESET();
 673
 674         /* Check to see if SDRAM cal was success */
 675         if (sdram_startup()) {
 676                 puts("DDRCAL: Failed\n");
 677                 return -EPERM;
 678         }
 679
 680         puts("DDRCAL: Success\n");
 681
 682         WATCHDOG_RESET();
 683
 684         /* initialize the MMR register */
 685         sdram_mmr_init();
 686
 687         /* assigning the SDRAM size */
 688         u64 size = sdram_size_calc();
 689
 690         /*
 691          * If size is less than zero, this is invalid/weird value from
 692          * calculation, use default Config size.
 693          * Up to 2GB is supported, 2GB would be used if more than that.
 694          */
 695         if (size <= 0)
 696                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 697         else if (DDR_SIZE_2GB_HEX <= size)
 698                 gd->ram_size = DDR_SIZE_2GB_HEX;
 699         else
 700                 gd->ram_size = (u32)size;
 701
 702         /* setup the dram info within bd */
 703         dram_init_banksize();
 704
 705         if (of_sdram_firewall_setup(gd->fdt_blob))
 706                 puts("FW: Error Configuring Firewall\n");
 707
 708         if (sdram_is_ecc_enabled())
 709                 sdram_init_ecc_bits(gd->ram_size);
 710
 711         return 0;
 712 }