drivers/clk/sunxi/clk_a23.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions B.V.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <asm/arch/ccu.h>
  12 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  13 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  14
  15 static struct ccu_clk_gate a23_gates[] = {
  16         [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
  17         [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
  18         [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
  19         [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
  20         [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
  21         [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
  22         [CLK_BUS_EHCI]          = GATE(0x060, BIT(26)),
  23         [CLK_BUS_OHCI]          = GATE(0x060, BIT(29)),
  24
  25         [CLK_BUS_UART0]         = GATE(0x06c, BIT(16)),
  26         [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
  27         [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
  28         [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
  29         [CLK_BUS_UART4]         = GATE(0x06c, BIT(20)),
  30
  31         [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
  32         [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
  33
  34         [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
  35         [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
  36         [CLK_USB_HSIC]          = GATE(0x0cc, BIT(10)),
  37         [CLK_USB_HSIC_12M]      = GATE(0x0cc, BIT(11)),
  38         [CLK_USB_OHCI]          = GATE(0x0cc, BIT(16)),
  39 };
  40
  41 static struct ccu_reset a23_resets[] = {
  42         [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
  43         [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
  44         [RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
  45
  46         [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
  47         [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
  48         [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
  49         [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
  50         [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
  51         [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
  52         [RST_BUS_EHCI]          = RESET(0x2c0, BIT(26)),
  53         [RST_BUS_OHCI]          = RESET(0x2c0, BIT(29)),
  54
  55         [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
  56         [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
  57         [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),
  58         [RST_BUS_UART3]         = RESET(0x2d8, BIT(19)),
  59         [RST_BUS_UART4]         = RESET(0x2d8, BIT(20)),
  60 };
  61
  62 static const struct ccu_desc a23_ccu_desc = {
  63         .gates = a23_gates,
  64         .resets = a23_resets,
  65 };
  66
  67 static int a23_clk_bind(struct udevice *dev)
  68 {
  69         return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
  70 }
  71
  72 static const struct udevice_id a23_clk_ids[] = {
  73         { .compatible = "allwinner,sun8i-a23-ccu",
  74           .data = (ulong)&a23_ccu_desc },
  75         { .compatible = "allwinner,sun8i-a33-ccu",
  76           .data = (ulong)&a23_ccu_desc },
  77         { }
  78 };
  79
  80 U_BOOT_DRIVER(clk_sun8i_a23) = {
  81         .name           = "sun8i_a23_ccu",
  82         .id             = UCLASS_CLK,
  83         .of_match       = a23_clk_ids,
  84         .priv_auto_alloc_size   = sizeof(struct ccu_priv),
  85         .ops            = &sunxi_clk_ops,
  86         .probe          = sunxi_clk_probe,
  87         .bind           = a23_clk_bind,
  88 };