drivers/clk/rockchip/clk_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <mapmem.h>
  15 #include <syscon.h>
  16 #include <bitfield.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/hardware.h>
  21 #include <dm/lists.h>
  22 #include <dt-bindings/clock/rk3399-cru.h>
  23
  24 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  25 struct rk3399_clk_plat {
  26         struct dtd_rockchip_rk3399_cru dtd;
  27 };
  28
  29 struct rk3399_pmuclk_plat {
  30         struct dtd_rockchip_rk3399_pmucru dtd;
  31 };
  32 #endif
  33
  34 struct pll_div {
  35         u32 refdiv;
  36         u32 fbdiv;
  37         u32 postdiv1;
  38         u32 postdiv2;
  39         u32 frac;
  40 };
  41
  42 #define RATE_TO_DIV(input_rate, output_rate) \
  43         ((input_rate) / (output_rate) - 1)
  44 #define DIV_TO_RATE(input_rate, div)            ((input_rate) / ((div) + 1))
  45
  46 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  47         .refdiv = _refdiv,\
  48         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  49         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  50
  51 #if defined(CONFIG_SPL_BUILD)
  52 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  53 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  54 #else
  55 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  56 #endif
  57
  58 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
  59 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  60
  61 static const struct pll_div *apll_l_cfgs[] = {
  62         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  63         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  64 };
  65
  66 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
  67 static const struct pll_div *apll_b_cfgs[] = {
  68         [APLL_B_600_MHZ] = &apll_b_600_cfg,
  69 };
  70
  71 enum {
  72         /* PLL_CON0 */
  73         PLL_FBDIV_MASK                  = 0xfff,
  74         PLL_FBDIV_SHIFT                 = 0,
  75
  76         /* PLL_CON1 */
  77         PLL_POSTDIV2_SHIFT              = 12,
  78         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  79         PLL_POSTDIV1_SHIFT              = 8,
  80         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  81         PLL_REFDIV_MASK                 = 0x3f,
  82         PLL_REFDIV_SHIFT                = 0,
  83
  84         /* PLL_CON2 */
  85         PLL_LOCK_STATUS_SHIFT           = 31,
  86         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  87         PLL_FRACDIV_MASK                = 0xffffff,
  88         PLL_FRACDIV_SHIFT               = 0,
  89
  90         /* PLL_CON3 */
  91         PLL_MODE_SHIFT                  = 8,
  92         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  93         PLL_MODE_SLOW                   = 0,
  94         PLL_MODE_NORM,
  95         PLL_MODE_DEEP,
  96         PLL_DSMPD_SHIFT                 = 3,
  97         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
  98         PLL_INTEGER_MODE                = 1,
  99
 100         /* PMUCRU_CLKSEL_CON0 */
 101         PMU_PCLK_DIV_CON_MASK           = 0x1f,
 102         PMU_PCLK_DIV_CON_SHIFT          = 0,
 103
 104         /* PMUCRU_CLKSEL_CON1 */
 105         SPI3_PLL_SEL_SHIFT              = 7,
 106         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 107         SPI3_PLL_SEL_24M                = 0,
 108         SPI3_PLL_SEL_PPLL               = 1,
 109         SPI3_DIV_CON_SHIFT              = 0x0,
 110         SPI3_DIV_CON_MASK               = 0x7f,
 111
 112         /* PMUCRU_CLKSEL_CON2 */
 113         I2C_DIV_CON_MASK                = 0x7f,
 114         CLK_I2C8_DIV_CON_SHIFT          = 8,
 115         CLK_I2C0_DIV_CON_SHIFT          = 0,
 116
 117         /* PMUCRU_CLKSEL_CON3 */
 118         CLK_I2C4_DIV_CON_SHIFT          = 0,
 119
 120         /* CLKSEL_CON0 */
 121         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 122         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 123         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 124         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 125         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 126         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 127         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 128         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 129         CLK_CORE_L_DIV_MASK             = 0x1f,
 130         CLK_CORE_L_DIV_SHIFT            = 0,
 131
 132         /* CLKSEL_CON1 */
 133         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 134         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 135         ATCLK_CORE_L_DIV_SHIFT          = 0,
 136         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 137
 138         /* CLKSEL_CON2 */
 139         ACLKM_CORE_B_DIV_CON_SHIFT      = 8,
 140         ACLKM_CORE_B_DIV_CON_MASK       = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
 141         CLK_CORE_B_PLL_SEL_SHIFT        = 6,
 142         CLK_CORE_B_PLL_SEL_MASK         = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
 143         CLK_CORE_B_PLL_SEL_ALPLL        = 0x0,
 144         CLK_CORE_B_PLL_SEL_ABPLL        = 0x1,
 145         CLK_CORE_B_PLL_SEL_DPLL         = 0x10,
 146         CLK_CORE_B_PLL_SEL_GPLL         = 0x11,
 147         CLK_CORE_B_DIV_MASK             = 0x1f,
 148         CLK_CORE_B_DIV_SHIFT            = 0,
 149
 150         /* CLKSEL_CON3 */
 151         PCLK_DBG_B_DIV_SHIFT            = 0x8,
 152         PCLK_DBG_B_DIV_MASK             = 0x1f << PCLK_DBG_B_DIV_SHIFT,
 153         ATCLK_CORE_B_DIV_SHIFT          = 0,
 154         ATCLK_CORE_B_DIV_MASK           = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
 155
 156         /* CLKSEL_CON14 */
 157         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 158         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 159         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 160         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 161         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 162         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 163         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 164         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 165         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 166         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 167
 168         /* CLKSEL_CON21 */
 169         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 170         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 171         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 172         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 173         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 174
 175         /* CLKSEL_CON22 */
 176         CLK_EMMC_PLL_SHIFT              = 8,
 177         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 178         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 179         CLK_EMMC_PLL_SEL_24M            = 0x5,
 180         CLK_EMMC_DIV_CON_SHIFT          = 0,
 181         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 182
 183         /* CLKSEL_CON23 */
 184         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 185         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 186         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 187         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 188         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 189         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 190         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 191         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 192         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 193         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 194
 195         /* CLKSEL_CON25 */
 196         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 197         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 198         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 199         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 200         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 201         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 202         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 203         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 204
 205         /* CLKSEL_CON26 */
 206         CLK_SARADC_DIV_CON_SHIFT        = 8,
 207         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 208         CLK_SARADC_DIV_CON_WIDTH        = 8,
 209
 210         /* CLKSEL_CON27 */
 211         CLK_TSADC_SEL_X24M              = 0x0,
 212         CLK_TSADC_SEL_SHIFT             = 15,
 213         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 214         CLK_TSADC_DIV_CON_SHIFT         = 0,
 215         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 216
 217         /* CLKSEL_CON47 & CLKSEL_CON48 */
 218         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 219         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 220         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 221         ACLK_VOP_DIV_CON_SHIFT          = 0,
 222         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 223
 224         /* CLKSEL_CON49 & CLKSEL_CON50 */
 225         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 226         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 227         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 228         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 229         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 230         DCLK_VOP_PLL_SEL_VPLL           = 0,
 231         DCLK_VOP_DIV_CON_MASK           = 0xff,
 232         DCLK_VOP_DIV_CON_SHIFT          = 0,
 233
 234         /* CLKSEL_CON58 */
 235         CLK_SPI_PLL_SEL_WIDTH = 1,
 236         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 237         CLK_SPI_PLL_SEL_CPLL = 0,
 238         CLK_SPI_PLL_SEL_GPLL = 1,
 239         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 240         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 241
 242         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 243         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 244
 245         /* CLKSEL_CON59 */
 246         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 247         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 248         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 249         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 250
 251         /* CLKSEL_CON60 */
 252         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 253         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 254         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 255         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 256
 257         /* CLKSEL_CON61 */
 258         CLK_I2C_PLL_SEL_MASK            = 1,
 259         CLK_I2C_PLL_SEL_CPLL            = 0,
 260         CLK_I2C_PLL_SEL_GPLL            = 1,
 261         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 262         CLK_I2C5_DIV_CON_SHIFT          = 8,
 263         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 264         CLK_I2C1_DIV_CON_SHIFT          = 0,
 265
 266         /* CLKSEL_CON62 */
 267         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 268         CLK_I2C6_DIV_CON_SHIFT          = 8,
 269         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 270         CLK_I2C2_DIV_CON_SHIFT          = 0,
 271
 272         /* CLKSEL_CON63 */
 273         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 274         CLK_I2C7_DIV_CON_SHIFT          = 8,
 275         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 276         CLK_I2C3_DIV_CON_SHIFT          = 0,
 277
 278         /* CRU_SOFTRST_CON4 */
 279         RESETN_DDR0_REQ_SHIFT           = 8,
 280         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 281         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 282         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 283         RESETN_DDR1_REQ_SHIFT           = 12,
 284         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 285         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 286         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 287 };
 288
 289 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 290 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 291 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 292 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 293
 294 /*
 295  *  the div restructions of pll in integer mode, these are defined in
 296  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 297  */
 298 #define PLL_DIV_MIN     16
 299 #define PLL_DIV_MAX     3200
 300
 301 /*
 302  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 303  * Formulas also embedded within the Fractional PLL Verilog model:
 304  * If DSMPD = 1 (DSM is disabled, "integer mode")
 305  * FOUTVCO = FREF / REFDIV * FBDIV
 306  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 307  * Where:
 308  * FOUTVCO = Fractional PLL non-divided output frequency
 309  * FOUTPOSTDIV = Fractional PLL divided output frequency
 310  *               (output of second post divider)
 311  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 312  * REFDIV = Fractional PLL input reference clock divider
 313  * FBDIV = Integer value programmed into feedback divide
 314  *
 315  */
 316 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 317 {
 318         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 319         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 320         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 321
 322         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 323                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 324                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 325                            div->postdiv2, vco_khz, output_khz);
 326         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 327                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 328                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 329
 330         /*
 331          * When power on or changing PLL setting,
 332          * we must force PLL into slow mode to ensure output stable clock.
 333          */
 334         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 335                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 336
 337         /* use integer mode */
 338         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 339                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 340
 341         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 342                      div->fbdiv << PLL_FBDIV_SHIFT);
 343         rk_clrsetreg(&pll_con[1],
 344                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 345                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 346                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 347                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 348                      (div->refdiv << PLL_REFDIV_SHIFT));
 349
 350         /* waiting for pll lock */
 351         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 352                 udelay(1);
 353
 354         /* pll enter normal mode */
 355         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 356                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 357 }
 358
 359 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 360 {
 361         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 362         u32 postdiv1, postdiv2 = 1;
 363         u32 fref_khz;
 364         u32 diff_khz, best_diff_khz;
 365         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 366         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 367         u32 vco_khz;
 368         u32 freq_khz = freq_hz / KHz;
 369
 370         if (!freq_hz) {
 371                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 372                 return -1;
 373         }
 374
 375         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 376         if (postdiv1 > max_postdiv1) {
 377                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 378                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 379         }
 380
 381         vco_khz = freq_khz * postdiv1 * postdiv2;
 382
 383         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 384             postdiv2 > max_postdiv2) {
 385                 printf("%s: Cannot find out a supported VCO"
 386                        " for Frequency (%uHz).\n", __func__, freq_hz);
 387                 return -1;
 388         }
 389
 390         div->postdiv1 = postdiv1;
 391         div->postdiv2 = postdiv2;
 392
 393         best_diff_khz = vco_khz;
 394         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 395                 fref_khz = ref_khz / refdiv;
 396
 397                 fbdiv = vco_khz / fref_khz;
 398                 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
 399                         continue;
 400                 diff_khz = vco_khz - fbdiv * fref_khz;
 401                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 402                         fbdiv++;
 403                         diff_khz = fref_khz - diff_khz;
 404                 }
 405
 406                 if (diff_khz >= best_diff_khz)
 407                         continue;
 408
 409                 best_diff_khz = diff_khz;
 410                 div->refdiv = refdiv;
 411                 div->fbdiv = fbdiv;
 412         }
 413
 414         if (best_diff_khz > 4 * (MHz / KHz)) {
 415                 printf("%s: Failed to match output frequency %u, "
 416                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 417                        best_diff_khz * KHz);
 418                 return -1;
 419         }
 420         return 0;
 421 }
 422
 423 void rk3399_configure_cpu_l(struct rockchip_cru *cru,
 424                             enum apll_l_frequencies apll_l_freq)
 425 {
 426         u32 aclkm_div;
 427         u32 pclk_dbg_div;
 428         u32 atclk_div;
 429
 430         /* Setup cluster L */
 431         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 432
 433         aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
 434         assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
 435                aclkm_div < 0x1f);
 436
 437         pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
 438         assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
 439                pclk_dbg_div < 0x1f);
 440
 441         atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
 442         assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
 443                atclk_div < 0x1f);
 444
 445         rk_clrsetreg(&cru->clksel_con[0],
 446                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 447                      CLK_CORE_L_DIV_MASK,
 448                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 449                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 450                      0 << CLK_CORE_L_DIV_SHIFT);
 451
 452         rk_clrsetreg(&cru->clksel_con[1],
 453                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 454                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 455                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 456 }
 457
 458 void rk3399_configure_cpu_b(struct rockchip_cru *cru,
 459                             enum apll_b_frequencies apll_b_freq)
 460 {
 461         u32 aclkm_div;
 462         u32 pclk_dbg_div;
 463         u32 atclk_div;
 464
 465         /* Setup cluster B */
 466         rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
 467
 468         aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
 469         assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
 470                aclkm_div < 0x1f);
 471
 472         pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
 473         assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
 474                pclk_dbg_div < 0x1f);
 475
 476         atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
 477         assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
 478                atclk_div < 0x1f);
 479
 480         rk_clrsetreg(&cru->clksel_con[2],
 481                      ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
 482                      CLK_CORE_B_DIV_MASK,
 483                      aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
 484                      CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
 485                      0 << CLK_CORE_B_DIV_SHIFT);
 486
 487         rk_clrsetreg(&cru->clksel_con[3],
 488                      PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
 489                      pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
 490                      atclk_div << ATCLK_CORE_B_DIV_SHIFT);
 491 }
 492
 493 #define I2C_CLK_REG_MASK(bus) \
 494         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 495          CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 496
 497 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 498         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
 499          CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
 500
 501 #define I2C_CLK_DIV_VALUE(con, bus) \
 502         ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
 503
 504 #define I2C_PMUCLK_REG_MASK(bus) \
 505         (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
 506
 507 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 508         ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
 509
 510 static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
 511 {
 512         u32 div, con;
 513
 514         switch (clk_id) {
 515         case SCLK_I2C1:
 516                 con = readl(&cru->clksel_con[61]);
 517                 div = I2C_CLK_DIV_VALUE(con, 1);
 518                 break;
 519         case SCLK_I2C2:
 520                 con = readl(&cru->clksel_con[62]);
 521                 div = I2C_CLK_DIV_VALUE(con, 2);
 522                 break;
 523         case SCLK_I2C3:
 524                 con = readl(&cru->clksel_con[63]);
 525                 div = I2C_CLK_DIV_VALUE(con, 3);
 526                 break;
 527         case SCLK_I2C5:
 528                 con = readl(&cru->clksel_con[61]);
 529                 div = I2C_CLK_DIV_VALUE(con, 5);
 530                 break;
 531         case SCLK_I2C6:
 532                 con = readl(&cru->clksel_con[62]);
 533                 div = I2C_CLK_DIV_VALUE(con, 6);
 534                 break;
 535         case SCLK_I2C7:
 536                 con = readl(&cru->clksel_con[63]);
 537                 div = I2C_CLK_DIV_VALUE(con, 7);
 538                 break;
 539         default:
 540                 printf("do not support this i2c bus\n");
 541                 return -EINVAL;
 542         }
 543
 544         return DIV_TO_RATE(GPLL_HZ, div);
 545 }
 546
 547 static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 548 {
 549         int src_clk_div;
 550
 551         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 552         src_clk_div = GPLL_HZ / hz;
 553         assert(src_clk_div - 1 < 127);
 554
 555         switch (clk_id) {
 556         case SCLK_I2C1:
 557                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 558                              I2C_CLK_REG_VALUE(1, src_clk_div));
 559                 break;
 560         case SCLK_I2C2:
 561                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 562                              I2C_CLK_REG_VALUE(2, src_clk_div));
 563                 break;
 564         case SCLK_I2C3:
 565                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 566                              I2C_CLK_REG_VALUE(3, src_clk_div));
 567                 break;
 568         case SCLK_I2C5:
 569                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 570                              I2C_CLK_REG_VALUE(5, src_clk_div));
 571                 break;
 572         case SCLK_I2C6:
 573                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 574                              I2C_CLK_REG_VALUE(6, src_clk_div));
 575                 break;
 576         case SCLK_I2C7:
 577                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 578                              I2C_CLK_REG_VALUE(7, src_clk_div));
 579                 break;
 580         default:
 581                 printf("do not support this i2c bus\n");
 582                 return -EINVAL;
 583         }
 584
 585         return rk3399_i2c_get_clk(cru, clk_id);
 586 }
 587
 588 /*
 589  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 590  * to select either CPLL or GPLL as the clock-parent. The location within
 591  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 592  */
 593
 594 struct spi_clkreg {
 595         u8 reg;  /* CLKSEL_CON[reg] register in CRU */
 596         u8 div_shift;
 597         u8 sel_shift;
 598 };
 599
 600 /*
 601  * The entries are numbered relative to their offset from SCLK_SPI0.
 602  *
 603  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 604  * logic is not supported).
 605  */
 606 static const struct spi_clkreg spi_clkregs[] = {
 607         [0] = { .reg = 59,
 608                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 609                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 610         [1] = { .reg = 59,
 611                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 612                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 613         [2] = { .reg = 60,
 614                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 615                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 616         [3] = { .reg = 60,
 617                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 618                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 619         [4] = { .reg = 58,
 620                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 621                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 622 };
 623
 624 static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
 625 {
 626         const struct spi_clkreg *spiclk = NULL;
 627         u32 div, val;
 628
 629         switch (clk_id) {
 630         case SCLK_SPI0 ... SCLK_SPI5:
 631                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 632                 break;
 633
 634         default:
 635                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 636                 return -EINVAL;
 637         }
 638
 639         val = readl(&cru->clksel_con[spiclk->reg]);
 640         div = bitfield_extract(val, spiclk->div_shift,
 641                                CLK_SPI_PLL_DIV_CON_WIDTH);
 642
 643         return DIV_TO_RATE(GPLL_HZ, div);
 644 }
 645
 646 static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
 647 {
 648         const struct spi_clkreg *spiclk = NULL;
 649         int src_clk_div;
 650
 651         src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
 652         assert(src_clk_div < 128);
 653
 654         switch (clk_id) {
 655         case SCLK_SPI1 ... SCLK_SPI5:
 656                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 657                 break;
 658
 659         default:
 660                 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 661                 return -EINVAL;
 662         }
 663
 664         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 665                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 666                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 667                      ((src_clk_div << spiclk->div_shift) |
 668                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 669
 670         return rk3399_spi_get_clk(cru, clk_id);
 671 }
 672
 673 static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
 674 {
 675         struct pll_div vpll_config = {0};
 676         int aclk_vop = 198 * MHz;
 677         void *aclkreg_addr, *dclkreg_addr;
 678         u32 div;
 679
 680         switch (clk_id) {
 681         case DCLK_VOP0:
 682                 aclkreg_addr = &cru->clksel_con[47];
 683                 dclkreg_addr = &cru->clksel_con[49];
 684                 break;
 685         case DCLK_VOP1:
 686                 aclkreg_addr = &cru->clksel_con[48];
 687                 dclkreg_addr = &cru->clksel_con[50];
 688                 break;
 689         default:
 690                 return -EINVAL;
 691         }
 692         /* vop aclk source clk: cpll */
 693         div = CPLL_HZ / aclk_vop;
 694         assert(div - 1 < 32);
 695
 696         rk_clrsetreg(aclkreg_addr,
 697                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 698                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 699                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 700
 701         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 702         if (pll_para_config(hz, &vpll_config))
 703                 return -1;
 704
 705         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 706
 707         rk_clrsetreg(dclkreg_addr,
 708                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 709                      DCLK_VOP_DIV_CON_MASK,
 710                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 711                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 712                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 713
 714         return hz;
 715 }
 716
 717 static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
 718 {
 719         u32 div, con;
 720
 721         switch (clk_id) {
 722         case HCLK_SDMMC:
 723         case SCLK_SDMMC:
 724                 con = readl(&cru->clksel_con[16]);
 725                 /* dwmmc controller have internal div 2 */
 726                 div = 2;
 727                 break;
 728         case SCLK_EMMC:
 729                 con = readl(&cru->clksel_con[21]);
 730                 div = 1;
 731                 break;
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 737         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 738                         == CLK_EMMC_PLL_SEL_24M)
 739                 return DIV_TO_RATE(OSC_HZ, div);
 740         else
 741                 return DIV_TO_RATE(GPLL_HZ, div);
 742 }
 743
 744 static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
 745                                 ulong clk_id, ulong set_rate)
 746 {
 747         int src_clk_div;
 748         int aclk_emmc = 198 * MHz;
 749
 750         switch (clk_id) {
 751         case HCLK_SDMMC:
 752         case SCLK_SDMMC:
 753                 /* Select clk_sdmmc source from GPLL by default */
 754                 /* mmc clock defaulg div 2 internal, provide double in cru */
 755                 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 756
 757                 if (src_clk_div > 128) {
 758                         /* use 24MHz source for 400KHz clock */
 759                         src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 760                         assert(src_clk_div - 1 < 128);
 761                         rk_clrsetreg(&cru->clksel_con[16],
 762                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 763                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 764                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 765                 } else {
 766                         rk_clrsetreg(&cru->clksel_con[16],
 767                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 768                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 769                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 770                 }
 771                 break;
 772         case SCLK_EMMC:
 773                 /* Select aclk_emmc source from GPLL */
 774                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
 775                 assert(src_clk_div - 1 < 32);
 776
 777                 rk_clrsetreg(&cru->clksel_con[21],
 778                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 779                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 780                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 781
 782                 /* Select clk_emmc source from GPLL too */
 783                 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
 784                 assert(src_clk_div - 1 < 128);
 785
 786                 rk_clrsetreg(&cru->clksel_con[22],
 787                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 788                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 789                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 790                 break;
 791         default:
 792                 return -EINVAL;
 793         }
 794         return rk3399_mmc_get_clk(cru, clk_id);
 795 }
 796
 797 static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
 798 {
 799         ulong ret;
 800
 801         /*
 802          * The RGMII CLK can be derived either from an external "clkin"
 803          * or can be generated from internally by a divider from SCLK_MAC.
 804          */
 805         if (readl(&cru->clksel_con[19]) & BIT(4)) {
 806                 /* An external clock will always generate the right rate... */
 807                 ret = rate;
 808         } else {
 809                 /*
 810                  * No platform uses an internal clock to date.
 811                  * Implement this once it becomes necessary and print an error
 812                  * if someone tries to use it (while it remains unimplemented).
 813                  */
 814                 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
 815                 ret = 0;
 816         }
 817
 818         return ret;
 819 }
 820
 821 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 822 static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
 823                                 ulong set_rate)
 824 {
 825         struct pll_div dpll_cfg;
 826
 827         /*  IC ECO bug, need to set this register */
 828         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 829
 830         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 831         switch (set_rate) {
 832         case 50 * MHz:
 833                 dpll_cfg = (struct pll_div)
 834                 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
 835                 break;
 836         case 200 * MHz:
 837                 dpll_cfg = (struct pll_div)
 838                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 839                 break;
 840         case 300 * MHz:
 841                 dpll_cfg = (struct pll_div)
 842                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 843                 break;
 844         case 400 * MHz:
 845                 dpll_cfg = (struct pll_div)
 846                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
 847                 break;
 848         case 666 * MHz:
 849                 dpll_cfg = (struct pll_div)
 850                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 851                 break;
 852         case 800 * MHz:
 853                 dpll_cfg = (struct pll_div)
 854                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 855                 break;
 856         case 933 * MHz:
 857                 dpll_cfg = (struct pll_div)
 858                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 859                 break;
 860         default:
 861                 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
 862         }
 863         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 864
 865         return set_rate;
 866 }
 867
 868 static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
 869 {
 870         u32 div, val;
 871
 872         val = readl(&cru->clksel_con[26]);
 873         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 874                                CLK_SARADC_DIV_CON_WIDTH);
 875
 876         return DIV_TO_RATE(OSC_HZ, div);
 877 }
 878
 879 static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 880 {
 881         int src_clk_div;
 882
 883         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 884         assert(src_clk_div < 128);
 885
 886         rk_clrsetreg(&cru->clksel_con[26],
 887                      CLK_SARADC_DIV_CON_MASK,
 888                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 889
 890         return rk3399_saradc_get_clk(cru);
 891 }
 892
 893 static ulong rk3399_clk_get_rate(struct clk *clk)
 894 {
 895         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 896         ulong rate = 0;
 897
 898         switch (clk->id) {
 899         case 0 ... 63:
 900                 return 0;
 901         case HCLK_SDMMC:
 902         case SCLK_SDMMC:
 903         case SCLK_EMMC:
 904                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 905                 break;
 906         case SCLK_I2C1:
 907         case SCLK_I2C2:
 908         case SCLK_I2C3:
 909         case SCLK_I2C5:
 910         case SCLK_I2C6:
 911         case SCLK_I2C7:
 912                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 913                 break;
 914         case SCLK_SPI0...SCLK_SPI5:
 915                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 916                 break;
 917         case SCLK_UART0:
 918         case SCLK_UART1:
 919         case SCLK_UART2:
 920         case SCLK_UART3:
 921                 return 24000000;
 922         case PCLK_HDMI_CTRL:
 923                 break;
 924         case DCLK_VOP0:
 925         case DCLK_VOP1:
 926                 break;
 927         case PCLK_EFUSE1024NS:
 928                 break;
 929         case SCLK_SARADC:
 930                 rate = rk3399_saradc_get_clk(priv->cru);
 931                 break;
 932         case ACLK_VIO:
 933         case ACLK_HDCP:
 934         case ACLK_GIC_PRE:
 935         case PCLK_DDR:
 936                 break;
 937         default:
 938                 log_debug("Unknown clock %lu\n", clk->id);
 939                 return -ENOENT;
 940         }
 941
 942         return rate;
 943 }
 944
 945 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 946 {
 947         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 948         ulong ret = 0;
 949
 950         switch (clk->id) {
 951         case 0 ... 63:
 952                 return 0;
 953
 954         case ACLK_PERIHP:
 955         case HCLK_PERIHP:
 956         case PCLK_PERIHP:
 957                 return 0;
 958
 959         case ACLK_PERILP0:
 960         case HCLK_PERILP0:
 961         case PCLK_PERILP0:
 962                 return 0;
 963
 964         case ACLK_CCI:
 965                 return 0;
 966
 967         case HCLK_PERILP1:
 968         case PCLK_PERILP1:
 969                 return 0;
 970
 971         case HCLK_SDMMC:
 972         case SCLK_SDMMC:
 973         case SCLK_EMMC:
 974                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 975                 break;
 976         case SCLK_MAC:
 977                 ret = rk3399_gmac_set_clk(priv->cru, rate);
 978                 break;
 979         case SCLK_I2C1:
 980         case SCLK_I2C2:
 981         case SCLK_I2C3:
 982         case SCLK_I2C5:
 983         case SCLK_I2C6:
 984         case SCLK_I2C7:
 985                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
 986                 break;
 987         case SCLK_SPI0...SCLK_SPI5:
 988                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
 989                 break;
 990         case PCLK_HDMI_CTRL:
 991         case PCLK_VIO_GRF:
 992                 /* the PCLK gates for video are enabled by default */
 993                 break;
 994         case DCLK_VOP0:
 995         case DCLK_VOP1:
 996                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
 997                 break;
 998         case ACLK_VOP1:
 999         case HCLK_VOP1:
1000         case HCLK_SD:
1001                 /**
1002                  * assigned-clocks handling won't require for vopl, so
1003                  * return 0 to satisfy clk_set_defaults during device probe.
1004                  */
1005                 return 0;
1006         case SCLK_DDRCLK:
1007                 ret = rk3399_ddr_set_clk(priv->cru, rate);
1008                 break;
1009         case PCLK_EFUSE1024NS:
1010                 break;
1011         case SCLK_SARADC:
1012                 ret = rk3399_saradc_set_clk(priv->cru, rate);
1013                 break;
1014         case ACLK_VIO:
1015         case ACLK_HDCP:
1016         case ACLK_GIC_PRE:
1017         case PCLK_DDR:
1018                 return 0;
1019         default:
1020                 log_debug("Unknown clock %lu\n", clk->id);
1021                 return -ENOENT;
1022         }
1023
1024         return ret;
1025 }
1026
1027 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1028                                                  struct clk *parent)
1029 {
1030         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1031         const char *clock_output_name;
1032         int ret;
1033
1034         /*
1035          * If the requested parent is in the same clock-controller and
1036          * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1037          */
1038         if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
1039                 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1040                 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1041                 return 0;
1042         }
1043
1044         /*
1045          * Otherwise, we need to check the clock-output-names of the
1046          * requested parent to see if the requested id is "clkin_gmac".
1047          */
1048         ret = dev_read_string_index(parent->dev, "clock-output-names",
1049                                     parent->id, &clock_output_name);
1050         if (ret < 0)
1051                 return -ENODATA;
1052
1053         /* If this is "clkin_gmac", switch to the external clock input */
1054         if (!strcmp(clock_output_name, "clkin_gmac")) {
1055                 debug("%s: switching RGMII to CLKIN\n", __func__);
1056                 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1057                 return 0;
1058         }
1059
1060         return -EINVAL;
1061 }
1062
1063 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1064                                                 struct clk *parent)
1065 {
1066         switch (clk->id) {
1067         case SCLK_RMII_SRC:
1068                 return rk3399_gmac_set_parent(clk, parent);
1069         }
1070
1071         debug("%s: unsupported clk %ld\n", __func__, clk->id);
1072         return -ENOENT;
1073 }
1074
1075 static struct clk_ops rk3399_clk_ops = {
1076         .get_rate = rk3399_clk_get_rate,
1077         .set_rate = rk3399_clk_set_rate,
1078 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1079         .set_parent = rk3399_clk_set_parent,
1080 #endif
1081 };
1082
1083 #ifdef CONFIG_SPL_BUILD
1084 static void rkclk_init(struct rockchip_cru *cru)
1085 {
1086         u32 aclk_div;
1087         u32 hclk_div;
1088         u32 pclk_div;
1089
1090         rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1091         rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
1092         /*
1093          * some cru registers changed by bootrom, we'd better reset them to
1094          * reset/default values described in TRM to avoid confusion in kernel.
1095          * Please consider these three lines as a fix of bootrom bug.
1096          */
1097         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1098         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1099         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1100
1101         /* configure gpll cpll */
1102         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1103         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1104
1105         /* configure perihp aclk, hclk, pclk */
1106         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1107         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1108
1109         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1110         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1111                PERIHP_ACLK_HZ && (hclk_div < 0x4));
1112
1113         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1114         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1115                PERIHP_ACLK_HZ && (pclk_div < 0x7));
1116
1117         rk_clrsetreg(&cru->clksel_con[14],
1118                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1119                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1120                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1121                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1122                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1123                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1124
1125         /* configure perilp0 aclk, hclk, pclk */
1126         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1127         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1128
1129         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1130         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1131                PERILP0_ACLK_HZ && (hclk_div < 0x4));
1132
1133         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1134         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1135                PERILP0_ACLK_HZ && (pclk_div < 0x7));
1136
1137         rk_clrsetreg(&cru->clksel_con[23],
1138                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1139                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1140                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1141                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1142                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1143                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1144
1145         /* perilp1 hclk select gpll as source */
1146         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1147         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1148                GPLL_HZ && (hclk_div < 0x1f));
1149
1150         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1151         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1152                PERILP1_HCLK_HZ && (hclk_div < 0x7));
1153
1154         rk_clrsetreg(&cru->clksel_con[25],
1155                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1156                      HCLK_PERILP1_PLL_SEL_MASK,
1157                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1158                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1159                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1160 }
1161 #endif
1162
1163 static int rk3399_clk_probe(struct udevice *dev)
1164 {
1165 #ifdef CONFIG_SPL_BUILD
1166         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1167
1168 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1169         struct rk3399_clk_plat *plat = dev_get_platdata(dev);
1170
1171         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1172 #endif
1173         rkclk_init(priv->cru);
1174 #endif
1175         return 0;
1176 }
1177
1178 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1179 {
1180 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1181         struct rk3399_clk_priv *priv = dev_get_priv(dev);
1182
1183         priv->cru = dev_read_addr_ptr(dev);
1184 #endif
1185         return 0;
1186 }
1187
1188 static int rk3399_clk_bind(struct udevice *dev)
1189 {
1190         int ret;
1191         struct udevice *sys_child;
1192         struct sysreset_reg *priv;
1193
1194         /* The reset driver does not have a device node, so bind it here */
1195         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1196                                  &sys_child);
1197         if (ret) {
1198                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1199         } else {
1200                 priv = malloc(sizeof(struct sysreset_reg));
1201                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1202                                                     glb_srst_fst_value);
1203                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1204                                                     glb_srst_snd_value);
1205                 sys_child->priv = priv;
1206         }
1207
1208 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1209         ret = offsetof(struct rockchip_cru, softrst_con[0]);
1210         ret = rockchip_reset_bind(dev, ret, 21);
1211         if (ret)
1212                 debug("Warning: software reset driver bind faile\n");
1213 #endif
1214
1215         return 0;
1216 }
1217
1218 static const struct udevice_id rk3399_clk_ids[] = {
1219         { .compatible = "rockchip,rk3399-cru" },
1220         { }
1221 };
1222
1223 U_BOOT_DRIVER(clk_rk3399) = {
1224         .name           = "rockchip_rk3399_cru",
1225         .id             = UCLASS_CLK,
1226         .of_match       = rk3399_clk_ids,
1227         .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1228         .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1229         .ops            = &rk3399_clk_ops,
1230         .bind           = rk3399_clk_bind,
1231         .probe          = rk3399_clk_probe,
1232 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1233         .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1234 #endif
1235 };
1236
1237 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1238 {
1239         u32 div, con;
1240
1241         switch (clk_id) {
1242         case SCLK_I2C0_PMU:
1243                 con = readl(&pmucru->pmucru_clksel[2]);
1244                 div = I2C_CLK_DIV_VALUE(con, 0);
1245                 break;
1246         case SCLK_I2C4_PMU:
1247                 con = readl(&pmucru->pmucru_clksel[3]);
1248                 div = I2C_CLK_DIV_VALUE(con, 4);
1249                 break;
1250         case SCLK_I2C8_PMU:
1251                 con = readl(&pmucru->pmucru_clksel[2]);
1252                 div = I2C_CLK_DIV_VALUE(con, 8);
1253                 break;
1254         default:
1255                 printf("do not support this i2c bus\n");
1256                 return -EINVAL;
1257         }
1258
1259         return DIV_TO_RATE(PPLL_HZ, div);
1260 }
1261
1262 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1263                                    uint hz)
1264 {
1265         int src_clk_div;
1266
1267         src_clk_div = PPLL_HZ / hz;
1268         assert(src_clk_div - 1 < 127);
1269
1270         switch (clk_id) {
1271         case SCLK_I2C0_PMU:
1272                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1273                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1274                 break;
1275         case SCLK_I2C4_PMU:
1276                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1277                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1278                 break;
1279         case SCLK_I2C8_PMU:
1280                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1281                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1282                 break;
1283         default:
1284                 printf("do not support this i2c bus\n");
1285                 return -EINVAL;
1286         }
1287
1288         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1289 }
1290
1291 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1292 {
1293         u32 div, con;
1294
1295         /* PWM closk rate is same as pclk_pmu */
1296         con = readl(&pmucru->pmucru_clksel[0]);
1297         div = con & PMU_PCLK_DIV_CON_MASK;
1298
1299         return DIV_TO_RATE(PPLL_HZ, div);
1300 }
1301
1302 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1303 {
1304         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1305         ulong rate = 0;
1306
1307         switch (clk->id) {
1308         case PLL_PPLL:
1309                 return PPLL_HZ;
1310         case PCLK_RKPWM_PMU:
1311                 rate = rk3399_pwm_get_clk(priv->pmucru);
1312                 break;
1313         case SCLK_I2C0_PMU:
1314         case SCLK_I2C4_PMU:
1315         case SCLK_I2C8_PMU:
1316                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1317                 break;
1318         default:
1319                 return -ENOENT;
1320         }
1321
1322         return rate;
1323 }
1324
1325 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1326 {
1327         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1328         ulong ret = 0;
1329
1330         switch (clk->id) {
1331         case PLL_PPLL:
1332                 /*
1333                  * This has already been set up and we don't want/need
1334                  * to change it here.  Accept the request though, as the
1335                  * device-tree has this in an 'assigned-clocks' list.
1336                  */
1337                 return PPLL_HZ;
1338         case SCLK_I2C0_PMU:
1339         case SCLK_I2C4_PMU:
1340         case SCLK_I2C8_PMU:
1341                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1342                 break;
1343         default:
1344                 return -ENOENT;
1345         }
1346
1347         return ret;
1348 }
1349
1350 static struct clk_ops rk3399_pmuclk_ops = {
1351         .get_rate = rk3399_pmuclk_get_rate,
1352         .set_rate = rk3399_pmuclk_set_rate,
1353 };
1354
1355 #ifndef CONFIG_SPL_BUILD
1356 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1357 {
1358         u32 pclk_div;
1359
1360         /*  configure pmu pll(ppll) */
1361         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1362
1363         /*  configure pmu pclk */
1364         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1365         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1366                      PMU_PCLK_DIV_CON_MASK,
1367                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1368 }
1369 #endif
1370
1371 static int rk3399_pmuclk_probe(struct udevice *dev)
1372 {
1373 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1374         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1375 #endif
1376
1377 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1378         struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1379
1380         priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1381 #endif
1382
1383 #ifndef CONFIG_SPL_BUILD
1384         pmuclk_init(priv->pmucru);
1385 #endif
1386         return 0;
1387 }
1388
1389 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1390 {
1391 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1392         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1393
1394         priv->pmucru = dev_read_addr_ptr(dev);
1395 #endif
1396         return 0;
1397 }
1398
1399 static int rk3399_pmuclk_bind(struct udevice *dev)
1400 {
1401 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1402         int ret;
1403
1404         ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1405         ret = rockchip_reset_bind(dev, ret, 2);
1406         if (ret)
1407                 debug("Warning: software reset driver bind faile\n");
1408 #endif
1409         return 0;
1410 }
1411
1412 static const struct udevice_id rk3399_pmuclk_ids[] = {
1413         { .compatible = "rockchip,rk3399-pmucru" },
1414         { }
1415 };
1416
1417 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1418         .name           = "rockchip_rk3399_pmucru",
1419         .id             = UCLASS_CLK,
1420         .of_match       = rk3399_pmuclk_ids,
1421         .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1422         .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1423         .ops            = &rk3399_pmuclk_ops,
1424         .probe          = rk3399_pmuclk_probe,
1425         .bind           = rk3399_pmuclk_bind,
1426 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1427         .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1428 #endif
1429 };