1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
8 #include <clk-uclass.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk3328.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <asm/arch-rockchip/grf_rk3328.h>
20 #include <dt-bindings/clock/rk3328-cru.h>
21 #include <linux/delay.h>
31 #define RATE_TO_DIV(input_rate, output_rate) \
32 ((input_rate) / (output_rate) - 1);
33 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
35 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
37 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
38 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
40 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
41 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
43 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
44 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
46 static const struct pll_div *apll_cfgs[] = {
47 [APLL_816_MHZ] = &apll_816_cfg,
48 [APLL_600_MHZ] = &apll_600_cfg,
53 PLL_POSTDIV1_SHIFT = 12,
54 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
56 PLL_FBDIV_MASK = 0xfff,
60 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
62 PLL_LOCK_STATUS_SHIFT = 10,
63 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
64 PLL_POSTDIV2_SHIFT = 6,
65 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
67 PLL_REFDIV_MASK = 0x3f,
70 PLL_FRACDIV_SHIFT = 0,
71 PLL_FRACDIV_MASK = 0xffffff,
83 CLK_CORE_PLL_SEL_APLL = 0,
84 CLK_CORE_PLL_SEL_GPLL,
85 CLK_CORE_PLL_SEL_DPLL,
86 CLK_CORE_PLL_SEL_NPLL,
87 CLK_CORE_PLL_SEL_SHIFT = 6,
88 CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
89 CLK_CORE_DIV_SHIFT = 0,
90 CLK_CORE_DIV_MASK = 0x1f,
93 ACLKM_CORE_DIV_SHIFT = 4,
94 ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
95 PCLK_DBG_DIV_SHIFT = 0,
96 PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
99 GMAC2IO_PLL_SEL_SHIFT = 7,
100 GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
101 GMAC2IO_PLL_SEL_CPLL = 0,
102 GMAC2IO_PLL_SEL_GPLL = 1,
103 GMAC2IO_CLK_DIV_MASK = 0x1f,
104 GMAC2IO_CLK_DIV_SHIFT = 0,
107 ACLK_PERIHP_PLL_SEL_CPLL = 0,
108 ACLK_PERIHP_PLL_SEL_GPLL,
109 ACLK_PERIHP_PLL_SEL_HDMIPHY,
110 ACLK_PERIHP_PLL_SEL_SHIFT = 6,
111 ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
112 ACLK_PERIHP_DIV_CON_SHIFT = 0,
113 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
116 PCLK_PERIHP_DIV_CON_SHIFT = 4,
117 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
118 HCLK_PERIHP_DIV_CON_SHIFT = 0,
119 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
122 CLK_TSADC_DIV_CON_SHIFT = 0,
123 CLK_TSADC_DIV_CON_MASK = 0x3ff,
126 CLK_SARADC_DIV_CON_SHIFT = 0,
127 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
128 CLK_SARADC_DIV_CON_WIDTH = 10,
131 CLK_PWM_PLL_SEL_CPLL = 0,
132 CLK_PWM_PLL_SEL_GPLL,
133 CLK_PWM_PLL_SEL_SHIFT = 15,
134 CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
135 CLK_PWM_DIV_CON_SHIFT = 8,
136 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
138 CLK_SPI_PLL_SEL_CPLL = 0,
139 CLK_SPI_PLL_SEL_GPLL,
140 CLK_SPI_PLL_SEL_SHIFT = 7,
141 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
142 CLK_SPI_DIV_CON_SHIFT = 0,
143 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
146 CLK_SDMMC_PLL_SEL_CPLL = 0,
147 CLK_SDMMC_PLL_SEL_GPLL,
148 CLK_SDMMC_PLL_SEL_24M,
149 CLK_SDMMC_PLL_SEL_USBPHY,
150 CLK_SDMMC_PLL_SHIFT = 8,
151 CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
152 CLK_SDMMC_DIV_CON_SHIFT = 0,
153 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
156 CLK_EMMC_PLL_SEL_CPLL = 0,
157 CLK_EMMC_PLL_SEL_GPLL,
158 CLK_EMMC_PLL_SEL_24M,
159 CLK_EMMC_PLL_SEL_USBPHY,
160 CLK_EMMC_PLL_SHIFT = 8,
161 CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
162 CLK_EMMC_DIV_CON_SHIFT = 0,
163 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
166 CLK_I2C_PLL_SEL_CPLL = 0,
167 CLK_I2C_PLL_SEL_GPLL,
168 CLK_I2C_DIV_CON_MASK = 0x7f,
169 CLK_I2C_PLL_SEL_MASK = 1,
170 CLK_I2C1_PLL_SEL_SHIFT = 15,
171 CLK_I2C1_DIV_CON_SHIFT = 8,
172 CLK_I2C0_PLL_SEL_SHIFT = 7,
173 CLK_I2C0_DIV_CON_SHIFT = 0,
176 CLK_I2C3_PLL_SEL_SHIFT = 15,
177 CLK_I2C3_DIV_CON_SHIFT = 8,
178 CLK_I2C2_PLL_SEL_SHIFT = 7,
179 CLK_I2C2_DIV_CON_SHIFT = 0,
182 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
183 #define VCO_MIN_KHZ (800 * (MHz / KHz))
184 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
185 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
188 * the div restructions of pll in integer mode, these are defined in
189 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
191 #define PLL_DIV_MIN 16
192 #define PLL_DIV_MAX 3200
195 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
196 * Formulas also embedded within the Fractional PLL Verilog model:
197 * If DSMPD = 1 (DSM is disabled, "integer mode")
198 * FOUTVCO = FREF / REFDIV * FBDIV
199 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
201 * FOUTVCO = Fractional PLL non-divided output frequency
202 * FOUTPOSTDIV = Fractional PLL divided output frequency
203 * (output of second post divider)
204 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
205 * REFDIV = Fractional PLL input reference clock divider
206 * FBDIV = Integer value programmed into feedback divide
209 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
210 const struct pll_div *div)
213 u32 mode_shift, mode_mask;
219 pll_con = cru->apll_con;
220 mode_shift = APLL_MODE_SHIFT;
223 pll_con = cru->dpll_con;
224 mode_shift = DPLL_MODE_SHIFT;
227 pll_con = cru->cpll_con;
228 mode_shift = CPLL_MODE_SHIFT;
231 pll_con = cru->gpll_con;
232 mode_shift = GPLL_MODE_SHIFT;
235 pll_con = cru->npll_con;
236 mode_shift = NPLL_MODE_SHIFT;
241 mode_mask = 1 << mode_shift;
243 /* All 8 PLLs have same VCO and output frequency range restrictions. */
244 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
245 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
247 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
248 postdiv2=%d, vco=%u khz, output=%u khz\n",
249 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
250 div->postdiv2, vco_khz, output_khz);
251 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
252 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
253 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
256 * When power on or changing PLL setting,
257 * we must force PLL into slow mode to ensure output stable clock.
259 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
261 /* use integer mode */
262 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
263 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
265 rk_clrsetreg(&pll_con[0],
266 PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
267 (div->fbdiv << PLL_FBDIV_SHIFT) |
268 (div->postdiv1 << PLL_POSTDIV1_SHIFT));
269 rk_clrsetreg(&pll_con[1],
270 PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
271 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
272 (div->refdiv << PLL_REFDIV_SHIFT));
274 /* waiting for pll lock */
275 while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
278 /* pll enter normal mode */
279 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
282 static void rkclk_init(struct rk3328_cru *cru)
288 rk3328_configure_cpu(cru, APLL_600_MHZ);
290 /* configure gpll cpll */
291 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
292 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
294 /* configure perihp aclk, hclk, pclk */
295 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
296 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
297 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
299 rk_clrsetreg(&cru->clksel_con[28],
300 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
301 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
302 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
303 rk_clrsetreg(&cru->clksel_con[29],
304 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
305 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
306 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
309 void rk3328_configure_cpu(struct rk3328_cru *cru,
310 enum apll_frequencies apll_freq)
316 rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
318 clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
319 aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
320 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
322 rk_clrsetreg(&cru->clksel_con[0],
323 CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
324 CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
325 clk_core_div << CLK_CORE_DIV_SHIFT);
327 rk_clrsetreg(&cru->clksel_con[1],
328 PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
329 pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
330 aclkm_div << ACLKM_CORE_DIV_SHIFT);
334 static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
340 con = readl(&cru->clksel_con[34]);
341 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
344 con = readl(&cru->clksel_con[34]);
345 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
348 con = readl(&cru->clksel_con[35]);
349 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
352 con = readl(&cru->clksel_con[35]);
353 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
356 printf("do not support this i2c bus\n");
360 return DIV_TO_RATE(GPLL_HZ, div);
363 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
367 src_clk_div = GPLL_HZ / hz;
368 assert(src_clk_div - 1 < 127);
372 rk_clrsetreg(&cru->clksel_con[34],
373 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
374 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
375 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
376 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
379 rk_clrsetreg(&cru->clksel_con[34],
380 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
381 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
382 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
383 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
386 rk_clrsetreg(&cru->clksel_con[35],
387 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
388 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
389 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
390 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
393 rk_clrsetreg(&cru->clksel_con[35],
394 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
395 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
396 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
397 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
400 printf("do not support this i2c bus\n");
404 return DIV_TO_RATE(GPLL_HZ, src_clk_div);
407 static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
409 struct rk3328_grf_regs *grf;
412 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
415 * The RGMII CLK can be derived either from an external "clkin"
416 * or can be generated from internally by a divider from SCLK_MAC.
418 if (readl(&grf->mac_con[1]) & BIT(10) &&
419 readl(&grf->soc_con[4]) & BIT(14)) {
420 /* An external clock will always generate the right rate... */
423 u32 con = readl(&cru->clksel_con[27]);
427 if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
432 div = DIV_ROUND_UP(pll_rate, rate) - 1;
434 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
435 div << GMAC2IO_CLK_DIV_SHIFT);
437 debug("Unsupported div for gmac:%d\n", div);
439 return DIV_TO_RATE(pll_rate, div);
445 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
447 u32 div, con, con_id;
461 con = readl(&cru->clksel_con[con_id]);
462 div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
464 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
465 == CLK_EMMC_PLL_SEL_24M)
466 return DIV_TO_RATE(OSC_HZ, div) / 2;
468 return DIV_TO_RATE(GPLL_HZ, div) / 2;
471 static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
472 ulong clk_id, ulong set_rate)
489 /* Select clk_sdmmc/emmc source from GPLL by default */
490 /* mmc clock defaulg div 2 internal, need provide double in cru */
491 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
493 if (src_clk_div > 127) {
494 /* use 24MHz source for 400KHz clock */
495 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
496 rk_clrsetreg(&cru->clksel_con[con_id],
497 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
498 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
499 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
501 rk_clrsetreg(&cru->clksel_con[con_id],
502 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
503 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
504 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
507 return rk3328_mmc_get_clk(cru, clk_id);
510 static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
514 con = readl(&cru->clksel_con[24]);
515 div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
517 return DIV_TO_RATE(GPLL_HZ, div);
520 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
522 u32 div = GPLL_HZ / hz;
524 rk_clrsetreg(&cru->clksel_con[24],
525 CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
526 CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
527 (div - 1) << CLK_PWM_DIV_CON_SHIFT);
529 return DIV_TO_RATE(GPLL_HZ, div);
532 static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
536 val = readl(&cru->clksel_con[23]);
537 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
538 CLK_SARADC_DIV_CON_WIDTH);
540 return DIV_TO_RATE(OSC_HZ, div);
543 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
547 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
548 assert(src_clk_div < 128);
550 rk_clrsetreg(&cru->clksel_con[23],
551 CLK_SARADC_DIV_CON_MASK,
552 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
554 return rk3328_saradc_get_clk(cru);
557 static ulong rk3328_clk_get_rate(struct clk *clk)
559 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
569 rate = rk3328_mmc_get_clk(priv->cru, clk->id);
575 rate = rk3328_i2c_get_clk(priv->cru, clk->id);
578 rate = rk3328_pwm_get_clk(priv->cru);
581 rate = rk3328_saradc_get_clk(priv->cru);
590 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
592 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
602 ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
608 ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
611 ret = rk3328_gmac2io_set_clk(priv->cru, rate);
614 ret = rk3328_pwm_set_clk(priv->cru, rate);
617 ret = rk3328_saradc_set_clk(priv->cru, rate);
639 case ACLK_RKVDEC_PRE:
642 case SCLK_VDEC_CABAC:
650 case SCLK_USB3OTG_SUSPEND:
659 static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
661 struct rk3328_grf_regs *grf;
662 const char *clock_output_name;
665 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
668 * If the requested parent is in the same clock-controller and the id
669 * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
671 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
672 debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
673 rk_clrreg(&grf->mac_con[1], BIT(10));
678 * Otherwise, we need to check the clock-output-names of the
679 * requested parent to see if the requested id is "gmac_clkin".
681 ret = dev_read_string_index(parent->dev, "clock-output-names",
682 parent->id, &clock_output_name);
686 /* If this is "gmac_clkin", switch to the external clock input */
687 if (!strcmp(clock_output_name, "gmac_clkin")) {
688 debug("%s: switching RGMII to CLKIN\n", __func__);
689 rk_setreg(&grf->mac_con[1], BIT(10));
696 static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
698 struct rk3328_grf_regs *grf;
699 const char *clock_output_name;
702 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
705 * If the requested parent is in the same clock-controller and the id
706 * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
708 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
709 debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
710 rk_clrreg(&grf->soc_con[4], BIT(14));
715 * Otherwise, we need to check the clock-output-names of the
716 * requested parent to see if the requested id is "gmac_clkin".
718 ret = dev_read_string_index(parent->dev, "clock-output-names",
719 parent->id, &clock_output_name);
723 /* If this is "gmac_clkin", switch to the external clock input */
724 if (!strcmp(clock_output_name, "gmac_clkin")) {
725 debug("%s: switching RGMII to CLKIN\n", __func__);
726 rk_setreg(&grf->soc_con[4], BIT(14));
733 static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
737 return rk3328_gmac2io_set_parent(clk, parent);
738 case SCLK_MAC2IO_EXT:
739 return rk3328_gmac2io_ext_set_parent(clk, parent);
749 debug("%s: unsupported clk %ld\n", __func__, clk->id);
753 static struct clk_ops rk3328_clk_ops = {
754 .get_rate = rk3328_clk_get_rate,
755 .set_rate = rk3328_clk_set_rate,
756 .set_parent = rk3328_clk_set_parent,
759 static int rk3328_clk_probe(struct udevice *dev)
761 struct rk3328_clk_priv *priv = dev_get_priv(dev);
763 rkclk_init(priv->cru);
768 static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
770 struct rk3328_clk_priv *priv = dev_get_priv(dev);
772 priv->cru = dev_read_addr_ptr(dev);
777 static int rk3328_clk_bind(struct udevice *dev)
780 struct udevice *sys_child;
781 struct sysreset_reg *priv;
783 /* The reset driver does not have a device node, so bind it here */
784 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
787 debug("Warning: No sysreset driver: ret=%d\n", ret);
789 priv = malloc(sizeof(struct sysreset_reg));
790 priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
792 priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
794 sys_child->priv = priv;
797 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
798 ret = offsetof(struct rk3328_cru, softrst_con[0]);
799 ret = rockchip_reset_bind(dev, ret, 12);
801 debug("Warning: software reset driver bind faile\n");
807 static const struct udevice_id rk3328_clk_ids[] = {
808 { .compatible = "rockchip,rk3328-cru" },
812 U_BOOT_DRIVER(rockchip_rk3328_cru) = {
813 .name = "rockchip_rk3328_cru",
815 .of_match = rk3328_clk_ids,
816 .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
817 .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
818 .ops = &rk3328_clk_ops,
819 .bind = rk3328_clk_bind,
820 .probe = rk3328_clk_probe,