drivers/clk/rockchip/clk_rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <bitfield.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <syscon.h>
  14 #include <asm/arch-rockchip/clock.h>
  15 #include <asm/arch-rockchip/cru_rk3328.h>
  16 #include <asm/arch-rockchip/hardware.h>
  17 #include <asm/arch-rockchip/grf_rk3328.h>
  18 #include <asm/io.h>
  19 #include <dm/lists.h>
  20 #include <dt-bindings/clock/rk3328-cru.h>
  21
  22 struct pll_div {
  23         u32 refdiv;
  24         u32 fbdiv;
  25         u32 postdiv1;
  26         u32 postdiv2;
  27         u32 frac;
  28 };
  29
  30 #define RATE_TO_DIV(input_rate, output_rate) \
  31         ((input_rate) / (output_rate) - 1);
  32 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  33
  34 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  35         .refdiv = _refdiv,\
  36         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  37         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  38
  39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
  40 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
  41
  42 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
  43 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
  44
  45 static const struct pll_div *apll_cfgs[] = {
  46         [APLL_816_MHZ] = &apll_816_cfg,
  47         [APLL_600_MHZ] = &apll_600_cfg,
  48 };
  49
  50 enum {
  51         /* PLL_CON0 */
  52         PLL_POSTDIV1_SHIFT              = 12,
  53         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  54         PLL_FBDIV_SHIFT                 = 0,
  55         PLL_FBDIV_MASK                  = 0xfff,
  56
  57         /* PLL_CON1 */
  58         PLL_DSMPD_SHIFT                 = 12,
  59         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
  60         PLL_INTEGER_MODE                = 1,
  61         PLL_LOCK_STATUS_SHIFT           = 10,
  62         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  63         PLL_POSTDIV2_SHIFT              = 6,
  64         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  65         PLL_REFDIV_SHIFT                = 0,
  66         PLL_REFDIV_MASK                 = 0x3f,
  67
  68         /* PLL_CON2 */
  69         PLL_FRACDIV_SHIFT               = 0,
  70         PLL_FRACDIV_MASK                = 0xffffff,
  71
  72         /* MODE_CON */
  73         APLL_MODE_SHIFT                 = 0,
  74         NPLL_MODE_SHIFT                 = 1,
  75         DPLL_MODE_SHIFT                 = 4,
  76         CPLL_MODE_SHIFT                 = 8,
  77         GPLL_MODE_SHIFT                 = 12,
  78         PLL_MODE_SLOW                   = 0,
  79         PLL_MODE_NORM,
  80
  81         /* CLKSEL_CON0 */
  82         CLK_CORE_PLL_SEL_APLL           = 0,
  83         CLK_CORE_PLL_SEL_GPLL,
  84         CLK_CORE_PLL_SEL_DPLL,
  85         CLK_CORE_PLL_SEL_NPLL,
  86         CLK_CORE_PLL_SEL_SHIFT          = 6,
  87         CLK_CORE_PLL_SEL_MASK           = 3 << CLK_CORE_PLL_SEL_SHIFT,
  88         CLK_CORE_DIV_SHIFT              = 0,
  89         CLK_CORE_DIV_MASK               = 0x1f,
  90
  91         /* CLKSEL_CON1 */
  92         ACLKM_CORE_DIV_SHIFT            = 4,
  93         ACLKM_CORE_DIV_MASK             = 0x7 << ACLKM_CORE_DIV_SHIFT,
  94         PCLK_DBG_DIV_SHIFT              = 0,
  95         PCLK_DBG_DIV_MASK               = 0xF << PCLK_DBG_DIV_SHIFT,
  96
  97         /* CLKSEL_CON27 */
  98         GMAC2IO_PLL_SEL_SHIFT           = 7,
  99         GMAC2IO_PLL_SEL_MASK            = 1 << GMAC2IO_PLL_SEL_SHIFT,
 100         GMAC2IO_PLL_SEL_CPLL            = 0,
 101         GMAC2IO_PLL_SEL_GPLL            = 1,
 102         GMAC2IO_CLK_DIV_MASK            = 0x1f,
 103         GMAC2IO_CLK_DIV_SHIFT           = 0,
 104
 105         /* CLKSEL_CON28 */
 106         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 107         ACLK_PERIHP_PLL_SEL_GPLL,
 108         ACLK_PERIHP_PLL_SEL_HDMIPHY,
 109         ACLK_PERIHP_PLL_SEL_SHIFT       = 6,
 110         ACLK_PERIHP_PLL_SEL_MASK        = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
 111         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 112         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 113
 114         /* CLKSEL_CON29 */
 115         PCLK_PERIHP_DIV_CON_SHIFT       = 4,
 116         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 117         HCLK_PERIHP_DIV_CON_SHIFT       = 0,
 118         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 119
 120         /* CLKSEL_CON22 */
 121         CLK_TSADC_DIV_CON_SHIFT         = 0,
 122         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 123
 124         /* CLKSEL_CON23 */
 125         CLK_SARADC_DIV_CON_SHIFT        = 0,
 126         CLK_SARADC_DIV_CON_MASK         = GENMASK(9, 0),
 127         CLK_SARADC_DIV_CON_WIDTH        = 10,
 128
 129         /* CLKSEL_CON24 */
 130         CLK_PWM_PLL_SEL_CPLL            = 0,
 131         CLK_PWM_PLL_SEL_GPLL,
 132         CLK_PWM_PLL_SEL_SHIFT           = 15,
 133         CLK_PWM_PLL_SEL_MASK            = 1 << CLK_PWM_PLL_SEL_SHIFT,
 134         CLK_PWM_DIV_CON_SHIFT           = 8,
 135         CLK_PWM_DIV_CON_MASK            = 0x7f << CLK_PWM_DIV_CON_SHIFT,
 136
 137         CLK_SPI_PLL_SEL_CPLL            = 0,
 138         CLK_SPI_PLL_SEL_GPLL,
 139         CLK_SPI_PLL_SEL_SHIFT           = 7,
 140         CLK_SPI_PLL_SEL_MASK            = 1 << CLK_SPI_PLL_SEL_SHIFT,
 141         CLK_SPI_DIV_CON_SHIFT           = 0,
 142         CLK_SPI_DIV_CON_MASK            = 0x7f << CLK_SPI_DIV_CON_SHIFT,
 143
 144         /* CLKSEL_CON30 */
 145         CLK_SDMMC_PLL_SEL_CPLL          = 0,
 146         CLK_SDMMC_PLL_SEL_GPLL,
 147         CLK_SDMMC_PLL_SEL_24M,
 148         CLK_SDMMC_PLL_SEL_USBPHY,
 149         CLK_SDMMC_PLL_SHIFT             = 8,
 150         CLK_SDMMC_PLL_MASK              = 0x3 << CLK_SDMMC_PLL_SHIFT,
 151         CLK_SDMMC_DIV_CON_SHIFT          = 0,
 152         CLK_SDMMC_DIV_CON_MASK           = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
 153
 154         /* CLKSEL_CON32 */
 155         CLK_EMMC_PLL_SEL_CPLL           = 0,
 156         CLK_EMMC_PLL_SEL_GPLL,
 157         CLK_EMMC_PLL_SEL_24M,
 158         CLK_EMMC_PLL_SEL_USBPHY,
 159         CLK_EMMC_PLL_SHIFT              = 8,
 160         CLK_EMMC_PLL_MASK               = 0x3 << CLK_EMMC_PLL_SHIFT,
 161         CLK_EMMC_DIV_CON_SHIFT          = 0,
 162         CLK_EMMC_DIV_CON_MASK           = 0xff << CLK_EMMC_DIV_CON_SHIFT,
 163
 164         /* CLKSEL_CON34 */
 165         CLK_I2C_PLL_SEL_CPLL            = 0,
 166         CLK_I2C_PLL_SEL_GPLL,
 167         CLK_I2C_DIV_CON_MASK            = 0x7f,
 168         CLK_I2C_PLL_SEL_MASK            = 1,
 169         CLK_I2C1_PLL_SEL_SHIFT          = 15,
 170         CLK_I2C1_DIV_CON_SHIFT          = 8,
 171         CLK_I2C0_PLL_SEL_SHIFT          = 7,
 172         CLK_I2C0_DIV_CON_SHIFT          = 0,
 173
 174         /* CLKSEL_CON35 */
 175         CLK_I2C3_PLL_SEL_SHIFT          = 15,
 176         CLK_I2C3_DIV_CON_SHIFT          = 8,
 177         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 178         CLK_I2C2_DIV_CON_SHIFT          = 0,
 179 };
 180
 181 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 182 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 183 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 184 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 185
 186 /*
 187  *  the div restructions of pll in integer mode, these are defined in
 188  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 189  */
 190 #define PLL_DIV_MIN     16
 191 #define PLL_DIV_MAX     3200
 192
 193 /*
 194  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 195  * Formulas also embedded within the Fractional PLL Verilog model:
 196  * If DSMPD = 1 (DSM is disabled, "integer mode")
 197  * FOUTVCO = FREF / REFDIV * FBDIV
 198  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 199  * Where:
 200  * FOUTVCO = Fractional PLL non-divided output frequency
 201  * FOUTPOSTDIV = Fractional PLL divided output frequency
 202  *               (output of second post divider)
 203  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 204  * REFDIV = Fractional PLL input reference clock divider
 205  * FBDIV = Integer value programmed into feedback divide
 206  *
 207  */
 208 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
 209                         const struct pll_div *div)
 210 {
 211         u32 *pll_con;
 212         u32 mode_shift, mode_mask;
 213
 214         pll_con = NULL;
 215         mode_shift = 0;
 216         switch (clk_id) {
 217         case CLK_ARM:
 218                 pll_con = cru->apll_con;
 219                 mode_shift = APLL_MODE_SHIFT;
 220                 break;
 221         case CLK_DDR:
 222                 pll_con = cru->dpll_con;
 223                 mode_shift = DPLL_MODE_SHIFT;
 224                 break;
 225         case CLK_CODEC:
 226                 pll_con = cru->cpll_con;
 227                 mode_shift = CPLL_MODE_SHIFT;
 228                 break;
 229         case CLK_GENERAL:
 230                 pll_con = cru->gpll_con;
 231                 mode_shift = GPLL_MODE_SHIFT;
 232                 break;
 233         case CLK_NEW:
 234                 pll_con = cru->npll_con;
 235                 mode_shift = NPLL_MODE_SHIFT;
 236                 break;
 237         default:
 238                 break;
 239         }
 240         mode_mask = 1 << mode_shift;
 241
 242         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 243         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 244         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 245
 246         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
 247               postdiv2=%d, vco=%u khz, output=%u khz\n",
 248               pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 249               div->postdiv2, vco_khz, output_khz);
 250         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 251                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 252                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 253
 254         /*
 255          * When power on or changing PLL setting,
 256          * we must force PLL into slow mode to ensure output stable clock.
 257          */
 258         rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
 259
 260         /* use integer mode */
 261         rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
 262                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 263
 264         rk_clrsetreg(&pll_con[0],
 265                      PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
 266                      (div->fbdiv << PLL_FBDIV_SHIFT) |
 267                      (div->postdiv1 << PLL_POSTDIV1_SHIFT));
 268         rk_clrsetreg(&pll_con[1],
 269                      PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
 270                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 271                      (div->refdiv << PLL_REFDIV_SHIFT));
 272
 273         /* waiting for pll lock */
 274         while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 275                 udelay(1);
 276
 277         /* pll enter normal mode */
 278         rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
 279 }
 280
 281 static void rkclk_init(struct rk3328_cru *cru)
 282 {
 283         u32 aclk_div;
 284         u32 hclk_div;
 285         u32 pclk_div;
 286
 287         rk3328_configure_cpu(cru, APLL_600_MHZ);
 288
 289         /* configure gpll cpll */
 290         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 291         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 292
 293         /* configure perihp aclk, hclk, pclk */
 294         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
 295         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
 296         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
 297
 298         rk_clrsetreg(&cru->clksel_con[28],
 299                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
 300                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
 301                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
 302         rk_clrsetreg(&cru->clksel_con[29],
 303                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
 304                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
 305                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
 306 }
 307
 308 void rk3328_configure_cpu(struct rk3328_cru *cru,
 309                           enum apll_frequencies apll_freq)
 310 {
 311         u32 clk_core_div;
 312         u32 aclkm_div;
 313         u32 pclk_dbg_div;
 314
 315         rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
 316
 317         clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
 318         aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
 319         pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
 320
 321         rk_clrsetreg(&cru->clksel_con[0],
 322                      CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
 323                      CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
 324                      clk_core_div << CLK_CORE_DIV_SHIFT);
 325
 326         rk_clrsetreg(&cru->clksel_con[1],
 327                      PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
 328                      pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
 329                      aclkm_div << ACLKM_CORE_DIV_SHIFT);
 330 }
 331
 332
 333 static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
 334 {
 335         u32 div, con;
 336
 337         switch (clk_id) {
 338         case SCLK_I2C0:
 339                 con = readl(&cru->clksel_con[34]);
 340                 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 341                 break;
 342         case SCLK_I2C1:
 343                 con = readl(&cru->clksel_con[34]);
 344                 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 345                 break;
 346         case SCLK_I2C2:
 347                 con = readl(&cru->clksel_con[35]);
 348                 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 349                 break;
 350         case SCLK_I2C3:
 351                 con = readl(&cru->clksel_con[35]);
 352                 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 353                 break;
 354         default:
 355                 printf("do not support this i2c bus\n");
 356                 return -EINVAL;
 357         }
 358
 359         return DIV_TO_RATE(GPLL_HZ, div);
 360 }
 361
 362 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
 363 {
 364         int src_clk_div;
 365
 366         src_clk_div = GPLL_HZ / hz;
 367         assert(src_clk_div - 1 < 127);
 368
 369         switch (clk_id) {
 370         case SCLK_I2C0:
 371                 rk_clrsetreg(&cru->clksel_con[34],
 372                              CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
 373                              CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
 374                              (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
 375                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
 376                 break;
 377         case SCLK_I2C1:
 378                 rk_clrsetreg(&cru->clksel_con[34],
 379                              CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
 380                              CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
 381                              (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
 382                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
 383                 break;
 384         case SCLK_I2C2:
 385                 rk_clrsetreg(&cru->clksel_con[35],
 386                              CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
 387                              CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
 388                              (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
 389                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
 390                 break;
 391         case SCLK_I2C3:
 392                 rk_clrsetreg(&cru->clksel_con[35],
 393                              CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
 394                              CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
 395                              (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
 396                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
 397                 break;
 398         default:
 399                 printf("do not support this i2c bus\n");
 400                 return -EINVAL;
 401         }
 402
 403         return DIV_TO_RATE(GPLL_HZ, src_clk_div);
 404 }
 405
 406 static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
 407 {
 408         struct rk3328_grf_regs *grf;
 409         ulong ret;
 410
 411         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 412
 413         /*
 414          * The RGMII CLK can be derived either from an external "clkin"
 415          * or can be generated from internally by a divider from SCLK_MAC.
 416          */
 417         if (readl(&grf->mac_con[1]) & BIT(10) &&
 418             readl(&grf->soc_con[4]) & BIT(14)) {
 419                 /* An external clock will always generate the right rate... */
 420                 ret = rate;
 421         } else {
 422                 u32 con = readl(&cru->clksel_con[27]);
 423                 ulong pll_rate;
 424                 u8 div;
 425
 426                 if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
 427                         pll_rate = GPLL_HZ;
 428                 else
 429                         pll_rate = CPLL_HZ;
 430
 431                 div = DIV_ROUND_UP(pll_rate, rate) - 1;
 432                 if (div <= 0x1f)
 433                         rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
 434                                      div << GMAC2IO_CLK_DIV_SHIFT);
 435                 else
 436                         debug("Unsupported div for gmac:%d\n", div);
 437
 438                 return DIV_TO_RATE(pll_rate, div);
 439         }
 440
 441         return ret;
 442 }
 443
 444 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
 445 {
 446         u32 div, con, con_id;
 447
 448         switch (clk_id) {
 449         case HCLK_SDMMC:
 450         case SCLK_SDMMC:
 451                 con_id = 30;
 452                 break;
 453         case HCLK_EMMC:
 454         case SCLK_EMMC:
 455                 con_id = 32;
 456                 break;
 457         default:
 458                 return -EINVAL;
 459         }
 460         con = readl(&cru->clksel_con[con_id]);
 461         div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 462
 463         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 464             == CLK_EMMC_PLL_SEL_24M)
 465                 return DIV_TO_RATE(OSC_HZ, div) / 2;
 466         else
 467                 return DIV_TO_RATE(GPLL_HZ, div) / 2;
 468 }
 469
 470 static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
 471                                 ulong clk_id, ulong set_rate)
 472 {
 473         int src_clk_div;
 474         u32 con_id;
 475
 476         switch (clk_id) {
 477         case HCLK_SDMMC:
 478         case SCLK_SDMMC:
 479                 con_id = 30;
 480                 break;
 481         case HCLK_EMMC:
 482         case SCLK_EMMC:
 483                 con_id = 32;
 484                 break;
 485         default:
 486                 return -EINVAL;
 487         }
 488         /* Select clk_sdmmc/emmc source from GPLL by default */
 489         /* mmc clock defaulg div 2 internal, need provide double in cru */
 490         src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 491
 492         if (src_clk_div > 127) {
 493                 /* use 24MHz source for 400KHz clock */
 494                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 495                 rk_clrsetreg(&cru->clksel_con[con_id],
 496                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 497                              CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 498                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 499         } else {
 500                 rk_clrsetreg(&cru->clksel_con[con_id],
 501                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 502                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 503                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 504         }
 505
 506         return rk3328_mmc_get_clk(cru, clk_id);
 507 }
 508
 509 static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
 510 {
 511         u32 div, con;
 512
 513         con = readl(&cru->clksel_con[24]);
 514         div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
 515
 516         return DIV_TO_RATE(GPLL_HZ, div);
 517 }
 518
 519 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
 520 {
 521         u32 div = GPLL_HZ / hz;
 522
 523         rk_clrsetreg(&cru->clksel_con[24],
 524                      CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
 525                      CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
 526                      (div - 1) << CLK_PWM_DIV_CON_SHIFT);
 527
 528         return DIV_TO_RATE(GPLL_HZ, div);
 529 }
 530
 531 static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
 532 {
 533         u32 div, val;
 534
 535         val = readl(&cru->clksel_con[23]);
 536         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 537                                CLK_SARADC_DIV_CON_WIDTH);
 538
 539         return DIV_TO_RATE(OSC_HZ, div);
 540 }
 541
 542 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
 543 {
 544         int src_clk_div;
 545
 546         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 547         assert(src_clk_div < 128);
 548
 549         rk_clrsetreg(&cru->clksel_con[23],
 550                      CLK_SARADC_DIV_CON_MASK,
 551                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 552
 553         return rk3328_saradc_get_clk(cru);
 554 }
 555
 556 static ulong rk3328_clk_get_rate(struct clk *clk)
 557 {
 558         struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
 559         ulong rate = 0;
 560
 561         switch (clk->id) {
 562         case 0 ... 29:
 563                 return 0;
 564         case HCLK_SDMMC:
 565         case HCLK_EMMC:
 566         case SCLK_SDMMC:
 567         case SCLK_EMMC:
 568                 rate = rk3328_mmc_get_clk(priv->cru, clk->id);
 569                 break;
 570         case SCLK_I2C0:
 571         case SCLK_I2C1:
 572         case SCLK_I2C2:
 573         case SCLK_I2C3:
 574                 rate = rk3328_i2c_get_clk(priv->cru, clk->id);
 575                 break;
 576         case SCLK_PWM:
 577                 rate = rk3328_pwm_get_clk(priv->cru);
 578                 break;
 579         case SCLK_SARADC:
 580                 rate = rk3328_saradc_get_clk(priv->cru);
 581                 break;
 582         default:
 583                 return -ENOENT;
 584         }
 585
 586         return rate;
 587 }
 588
 589 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 590 {
 591         struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
 592         ulong ret = 0;
 593
 594         switch (clk->id) {
 595         case 0 ... 29:
 596                 return 0;
 597         case HCLK_SDMMC:
 598         case HCLK_EMMC:
 599         case SCLK_SDMMC:
 600         case SCLK_EMMC:
 601                 ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
 602                 break;
 603         case SCLK_I2C0:
 604         case SCLK_I2C1:
 605         case SCLK_I2C2:
 606         case SCLK_I2C3:
 607                 ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
 608                 break;
 609         case SCLK_MAC2IO:
 610                 ret = rk3328_gmac2io_set_clk(priv->cru, rate);
 611                 break;
 612         case SCLK_PWM:
 613                 ret = rk3328_pwm_set_clk(priv->cru, rate);
 614                 break;
 615         case SCLK_SARADC:
 616                 ret = rk3328_saradc_set_clk(priv->cru, rate);
 617                 break;
 618         case DCLK_LCDC:
 619         case SCLK_PDM:
 620         case SCLK_RTC32K:
 621         case SCLK_UART0:
 622         case SCLK_UART1:
 623         case SCLK_UART2:
 624         case SCLK_SDIO:
 625         case SCLK_TSP:
 626         case SCLK_WIFI:
 627         case ACLK_BUS_PRE:
 628         case HCLK_BUS_PRE:
 629         case PCLK_BUS_PRE:
 630         case ACLK_PERI_PRE:
 631         case HCLK_PERI:
 632         case PCLK_PERI:
 633         case ACLK_VIO_PRE:
 634         case HCLK_VIO_PRE:
 635         case ACLK_RGA_PRE:
 636         case SCLK_RGA:
 637         case ACLK_VOP_PRE:
 638         case ACLK_RKVDEC_PRE:
 639         case ACLK_RKVENC:
 640         case ACLK_VPU_PRE:
 641         case SCLK_VDEC_CABAC:
 642         case SCLK_VDEC_CORE:
 643         case SCLK_VENC_CORE:
 644         case SCLK_VENC_DSP:
 645         case SCLK_EFUSE:
 646         case PCLK_DDR:
 647         case ACLK_GMAC:
 648         case PCLK_GMAC:
 649         case SCLK_USB3OTG_SUSPEND:
 650                 return 0;
 651         default:
 652                 return -ENOENT;
 653         }
 654
 655         return ret;
 656 }
 657
 658 static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
 659 {
 660         struct rk3328_grf_regs *grf;
 661         const char *clock_output_name;
 662         int ret;
 663
 664         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 665
 666         /*
 667          * If the requested parent is in the same clock-controller and the id
 668          * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
 669          */
 670         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
 671                 debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
 672                 rk_clrreg(&grf->mac_con[1], BIT(10));
 673                 return 0;
 674         }
 675
 676         /*
 677          * Otherwise, we need to check the clock-output-names of the
 678          * requested parent to see if the requested id is "gmac_clkin".
 679          */
 680         ret = dev_read_string_index(parent->dev, "clock-output-names",
 681                                     parent->id, &clock_output_name);
 682         if (ret < 0)
 683                 return -ENODATA;
 684
 685         /* If this is "gmac_clkin", switch to the external clock input */
 686         if (!strcmp(clock_output_name, "gmac_clkin")) {
 687                 debug("%s: switching RGMII to CLKIN\n", __func__);
 688                 rk_setreg(&grf->mac_con[1], BIT(10));
 689                 return 0;
 690         }
 691
 692         return -EINVAL;
 693 }
 694
 695 static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
 696 {
 697         struct rk3328_grf_regs *grf;
 698         const char *clock_output_name;
 699         int ret;
 700
 701         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 702
 703         /*
 704          * If the requested parent is in the same clock-controller and the id
 705          * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
 706          */
 707         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
 708                 debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
 709                 rk_clrreg(&grf->soc_con[4], BIT(14));
 710                 return 0;
 711         }
 712
 713         /*
 714          * Otherwise, we need to check the clock-output-names of the
 715          * requested parent to see if the requested id is "gmac_clkin".
 716          */
 717         ret = dev_read_string_index(parent->dev, "clock-output-names",
 718                                     parent->id, &clock_output_name);
 719         if (ret < 0)
 720                 return -ENODATA;
 721
 722         /* If this is "gmac_clkin", switch to the external clock input */
 723         if (!strcmp(clock_output_name, "gmac_clkin")) {
 724                 debug("%s: switching RGMII to CLKIN\n", __func__);
 725                 rk_setreg(&grf->soc_con[4], BIT(14));
 726                 return 0;
 727         }
 728
 729         return -EINVAL;
 730 }
 731
 732 static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
 733 {
 734         switch (clk->id) {
 735         case SCLK_MAC2IO:
 736                 return rk3328_gmac2io_set_parent(clk, parent);
 737         case SCLK_MAC2IO_EXT:
 738                 return rk3328_gmac2io_ext_set_parent(clk, parent);
 739         case DCLK_LCDC:
 740         case SCLK_PDM:
 741         case SCLK_RTC32K:
 742         case SCLK_UART0:
 743         case SCLK_UART1:
 744         case SCLK_UART2:
 745                 return 0;
 746         }
 747
 748         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 749         return -ENOENT;
 750 }
 751
 752 static struct clk_ops rk3328_clk_ops = {
 753         .get_rate = rk3328_clk_get_rate,
 754         .set_rate = rk3328_clk_set_rate,
 755         .set_parent = rk3328_clk_set_parent,
 756 };
 757
 758 static int rk3328_clk_probe(struct udevice *dev)
 759 {
 760         struct rk3328_clk_priv *priv = dev_get_priv(dev);
 761
 762         rkclk_init(priv->cru);
 763
 764         return 0;
 765 }
 766
 767 static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
 768 {
 769         struct rk3328_clk_priv *priv = dev_get_priv(dev);
 770
 771         priv->cru = dev_read_addr_ptr(dev);
 772
 773         return 0;
 774 }
 775
 776 static int rk3328_clk_bind(struct udevice *dev)
 777 {
 778         int ret;
 779         struct udevice *sys_child;
 780         struct sysreset_reg *priv;
 781
 782         /* The reset driver does not have a device node, so bind it here */
 783         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 784                                  &sys_child);
 785         if (ret) {
 786                 debug("Warning: No sysreset driver: ret=%d\n", ret);
 787         } else {
 788                 priv = malloc(sizeof(struct sysreset_reg));
 789                 priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
 790                                                     glb_srst_fst_value);
 791                 priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
 792                                                     glb_srst_snd_value);
 793                 sys_child->priv = priv;
 794         }
 795
 796 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
 797         ret = offsetof(struct rk3328_cru, softrst_con[0]);
 798         ret = rockchip_reset_bind(dev, ret, 12);
 799         if (ret)
 800                 debug("Warning: software reset driver bind faile\n");
 801 #endif
 802
 803         return ret;
 804 }
 805
 806 static const struct udevice_id rk3328_clk_ids[] = {
 807         { .compatible = "rockchip,rk3328-cru" },
 808         { }
 809 };
 810
 811 U_BOOT_DRIVER(rockchip_rk3328_cru) = {
 812         .name           = "rockchip_rk3328_cru",
 813         .id             = UCLASS_CLK,
 814         .of_match       = rk3328_clk_ids,
 815         .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
 816         .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
 817         .ops            = &rk3328_clk_ops,
 818         .bind           = rk3328_clk_bind,
 819         .probe          = rk3328_clk_probe,
 820 };