drivers/clk/rockchip/clk_rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  */
   5
   6 #include <common.h>
   7 #include <bitfield.h>
   8 #include <clk-uclass.h>
   9 #include <div64.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mapmem.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/grf_rk3288.h>
  21 #include <asm/arch-rockchip/hardware.h>
  22 #include <dt-bindings/clock/rk3288-cru.h>
  23 #include <dm/device-internal.h>
  24 #include <dm/lists.h>
  25 #include <dm/uclass-internal.h>
  26 #include <linux/delay.h>
  27 #include <linux/err.h>
  28 #include <linux/log2.h>
  29 #include <linux/stringify.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 struct rk3288_clk_plat {
  34 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  35         struct dtd_rockchip_rk3288_cru dtd;
  36 #endif
  37 };
  38
  39 struct pll_div {
  40         u32 nr;
  41         u32 nf;
  42         u32 no;
  43 };
  44
  45 enum {
  46         VCO_MAX_HZ      = 2200U * 1000000,
  47         VCO_MIN_HZ      = 440 * 1000000,
  48         OUTPUT_MAX_HZ   = 2200U * 1000000,
  49         OUTPUT_MIN_HZ   = 27500000,
  50         FREF_MAX_HZ     = 2200U * 1000000,
  51         FREF_MIN_HZ     = 269 * 1000,
  52 };
  53
  54 enum {
  55         /* PLL CON0 */
  56         PLL_OD_MASK             = 0x0f,
  57
  58         /* PLL CON1 */
  59         PLL_NF_MASK             = 0x1fff,
  60
  61         /* PLL CON2 */
  62         PLL_BWADJ_MASK          = 0x0fff,
  63
  64         /* PLL CON3 */
  65         PLL_RESET_SHIFT         = 5,
  66
  67         /* CLKSEL0 */
  68         CORE_SEL_PLL_SHIFT      = 15,
  69         CORE_SEL_PLL_MASK       = 1 << CORE_SEL_PLL_SHIFT,
  70         A17_DIV_SHIFT           = 8,
  71         A17_DIV_MASK            = 0x1f << A17_DIV_SHIFT,
  72         MP_DIV_SHIFT            = 4,
  73         MP_DIV_MASK             = 0xf << MP_DIV_SHIFT,
  74         M0_DIV_SHIFT            = 0,
  75         M0_DIV_MASK             = 0xf << M0_DIV_SHIFT,
  76
  77         /* CLKSEL1: pd bus clk pll sel: codec or general */
  78         PD_BUS_SEL_PLL_MASK     = 15,
  79         PD_BUS_SEL_CPLL         = 0,
  80         PD_BUS_SEL_GPLL,
  81
  82         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  83         PD_BUS_PCLK_DIV_SHIFT   = 12,
  84         PD_BUS_PCLK_DIV_MASK    = 7 << PD_BUS_PCLK_DIV_SHIFT,
  85
  86         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  87         PD_BUS_HCLK_DIV_SHIFT   = 8,
  88         PD_BUS_HCLK_DIV_MASK    = 3 << PD_BUS_HCLK_DIV_SHIFT,
  89
  90         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  91         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  92         PD_BUS_ACLK_DIV0_MASK   = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
  93         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  94         PD_BUS_ACLK_DIV1_MASK   = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
  95
  96         /*
  97          * CLKSEL10
  98          * peripheral bus pclk div:
  99          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
 100          */
 101         PERI_SEL_PLL_SHIFT       = 15,
 102         PERI_SEL_PLL_MASK        = 1 << PERI_SEL_PLL_SHIFT,
 103         PERI_SEL_CPLL           = 0,
 104         PERI_SEL_GPLL,
 105
 106         PERI_PCLK_DIV_SHIFT     = 12,
 107         PERI_PCLK_DIV_MASK      = 3 << PERI_PCLK_DIV_SHIFT,
 108
 109         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 110         PERI_HCLK_DIV_SHIFT     = 8,
 111         PERI_HCLK_DIV_MASK      = 3 << PERI_HCLK_DIV_SHIFT,
 112
 113         /*
 114          * peripheral bus aclk div:
 115          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 116          */
 117         PERI_ACLK_DIV_SHIFT     = 0,
 118         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 119
 120         /*
 121          * CLKSEL24
 122          * saradc_div_con:
 123          * clk_saradc=24MHz/(saradc_div_con+1)
 124          */
 125         CLK_SARADC_DIV_CON_SHIFT        = 8,
 126         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 127         CLK_SARADC_DIV_CON_WIDTH        = 8,
 128
 129         SOCSTS_DPLL_LOCK        = 1 << 5,
 130         SOCSTS_APLL_LOCK        = 1 << 6,
 131         SOCSTS_CPLL_LOCK        = 1 << 7,
 132         SOCSTS_GPLL_LOCK        = 1 << 8,
 133         SOCSTS_NPLL_LOCK        = 1 << 9,
 134 };
 135
 136 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 137
 138 #define PLL_DIVISORS(hz, _nr, _no) {\
 139         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 140         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 141                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 142                        "divisors on line " __stringify(__LINE__));
 143
 144 /* Keep divisors as low as possible to reduce jitter and power usage */
 145 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 146 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 147 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 148
 149 static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
 150                          const struct pll_div *div)
 151 {
 152         int pll_id = rk_pll_id(clk_id);
 153         struct rk3288_pll *pll = &cru->pll[pll_id];
 154         /* All PLLs have same VCO and output frequency range restrictions. */
 155         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 156         uint output_hz = vco_hz / div->no;
 157
 158         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 159               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 160         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 161                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 162                (div->no == 1 || !(div->no % 2)));
 163
 164         /* enter reset */
 165         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 166
 167         rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
 168                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 169         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 170         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 171
 172         udelay(10);
 173
 174         /* return from reset */
 175         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 176
 177         return 0;
 178 }
 179
 180 static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
 181                                unsigned int hz)
 182 {
 183         static const struct pll_div dpll_cfg[] = {
 184                 {.nf = 25, .nr = 2, .no = 1},
 185                 {.nf = 400, .nr = 9, .no = 2},
 186                 {.nf = 500, .nr = 9, .no = 2},
 187                 {.nf = 100, .nr = 3, .no = 1},
 188         };
 189         int cfg;
 190
 191         switch (hz) {
 192         case 300000000:
 193                 cfg = 0;
 194                 break;
 195         case 533000000: /* actually 533.3P MHz */
 196                 cfg = 1;
 197                 break;
 198         case 666000000: /* actually 666.6P MHz */
 199                 cfg = 2;
 200                 break;
 201         case 800000000:
 202                 cfg = 3;
 203                 break;
 204         default:
 205                 debug("Unsupported SDRAM frequency");
 206                 return -EINVAL;
 207         }
 208
 209         /* pll enter slow-mode */
 210         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 211                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 212
 213         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 214
 215         /* wait for pll lock */
 216         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 217                 udelay(1);
 218
 219         /* PLL enter normal-mode */
 220         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 221                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 222
 223         return 0;
 224 }
 225
 226 #ifndef CONFIG_SPL_BUILD
 227 #define VCO_MAX_KHZ     2200000
 228 #define VCO_MIN_KHZ     440000
 229 #define FREF_MAX_KHZ    2200000
 230 #define FREF_MIN_KHZ    269
 231
 232 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 233 {
 234         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 235         uint fref_khz;
 236         uint diff_khz, best_diff_khz;
 237         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 238         uint vco_khz;
 239         uint no = 1;
 240         uint freq_khz = freq_hz / 1000;
 241
 242         if (!freq_hz) {
 243                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 244                 return -EINVAL;
 245         }
 246
 247         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 248         if (ext_div) {
 249                 *ext_div = DIV_ROUND_UP(no, max_no);
 250                 no = DIV_ROUND_UP(no, *ext_div);
 251         }
 252
 253         /* only even divisors (and 1) are supported */
 254         if (no > 1)
 255                 no = DIV_ROUND_UP(no, 2) * 2;
 256
 257         vco_khz = freq_khz * no;
 258         if (ext_div)
 259                 vco_khz *= *ext_div;
 260
 261         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 262                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 263                        __func__, freq_hz);
 264                 return -1;
 265         }
 266
 267         div->no = no;
 268
 269         best_diff_khz = vco_khz;
 270         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 271                 fref_khz = ref_khz / nr;
 272                 if (fref_khz < FREF_MIN_KHZ)
 273                         break;
 274                 if (fref_khz > FREF_MAX_KHZ)
 275                         continue;
 276
 277                 nf = vco_khz / fref_khz;
 278                 if (nf >= max_nf)
 279                         continue;
 280                 diff_khz = vco_khz - nf * fref_khz;
 281                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 282                         nf++;
 283                         diff_khz = fref_khz - diff_khz;
 284                 }
 285
 286                 if (diff_khz >= best_diff_khz)
 287                         continue;
 288
 289                 best_diff_khz = diff_khz;
 290                 div->nr = nr;
 291                 div->nf = nf;
 292         }
 293
 294         if (best_diff_khz > 4 * 1000) {
 295                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 296                        __func__, freq_hz, best_diff_khz * 1000);
 297                 return -EINVAL;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
 304 {
 305         ulong ret;
 306
 307         /*
 308          * The gmac clock can be derived either from an external clock
 309          * or can be generated from internally by a divider from SCLK_MAC.
 310          */
 311         if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
 312                 /* An external clock will always generate the right rate... */
 313                 ret = freq;
 314         } else {
 315                 u32 con = readl(&cru->cru_clksel_con[21]);
 316                 ulong pll_rate;
 317                 u8 div;
 318
 319                 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
 320                     EMAC_PLL_SELECT_GENERAL)
 321                         pll_rate = GPLL_HZ;
 322                 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
 323                          EMAC_PLL_SELECT_CODEC)
 324                         pll_rate = CPLL_HZ;
 325                 else
 326                         pll_rate = NPLL_HZ;
 327
 328                 div = DIV_ROUND_UP(pll_rate, freq) - 1;
 329                 if (div <= 0x1f)
 330                         rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
 331                                      div << MAC_DIV_CON_SHIFT);
 332                 else
 333                         debug("Unsupported div for gmac:%d\n", div);
 334
 335                 return DIV_TO_RATE(pll_rate, div);
 336         }
 337
 338         return ret;
 339 }
 340
 341 static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
 342                                 int periph, unsigned int rate_hz)
 343 {
 344         struct pll_div npll_config = {0};
 345         u32 lcdc_div;
 346         int ret;
 347
 348         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 349         if (ret)
 350                 return ret;
 351
 352         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 353                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 354         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 355
 356         /* waiting for pll lock */
 357         while (1) {
 358                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 359                         break;
 360                 udelay(1);
 361         }
 362
 363         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 364                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 365
 366         /* vop dclk source clk: npll,dclk_div: 1 */
 367         switch (periph) {
 368         case DCLK_VOP0:
 369                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 370                              (lcdc_div - 1) << 8 | 2 << 0);
 371                 break;
 372         case DCLK_VOP1:
 373                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 374                              (lcdc_div - 1) << 8 | 2 << 6);
 375                 break;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static u32 rockchip_clk_gcd(u32 a, u32 b)
 382 {
 383         while (b != 0) {
 384                 int r = b;
 385
 386                 b = a % b;
 387                 a = r;
 388         }
 389         return a;
 390 }
 391
 392 static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
 393 {
 394         unsigned long long rate;
 395         uint val;
 396         int n, d;
 397
 398         val = readl(&cru->cru_clksel_con[8]);
 399         n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
 400         d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
 401
 402         rate = (unsigned long long)gclk_rate * n;
 403         do_div(rate, d);
 404
 405         return (ulong)rate;
 406 }
 407
 408 static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 409                                   uint freq)
 410 {
 411         int n, d;
 412         int v;
 413
 414         /* set frac divider */
 415         v = rockchip_clk_gcd(gclk_rate, freq);
 416         n = gclk_rate / v;
 417         d = freq / v;
 418         assert(freq == gclk_rate / n * d);
 419         writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
 420                &cru->cru_clksel_con[8]);
 421
 422         return rockchip_i2s_get_clk(cru, gclk_rate);
 423 }
 424 #endif /* CONFIG_SPL_BUILD */
 425
 426 static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
 427 {
 428         u32 aclk_div;
 429         u32 hclk_div;
 430         u32 pclk_div;
 431
 432         /* pll enter slow-mode */
 433         rk_clrsetreg(&cru->cru_mode_con,
 434                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 435                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 436                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 437
 438         /* init pll */
 439         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 440         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 441
 442         /* waiting for pll lock */
 443         while ((readl(&grf->soc_status[1]) &
 444                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 445                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 446                 udelay(1);
 447
 448         /*
 449          * pd_bus clock pll source selection and
 450          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 451          */
 452         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 453         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 454         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 455         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 456                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 457
 458         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 459         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 460                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 461
 462         rk_clrsetreg(&cru->cru_clksel_con[1],
 463                      PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
 464                      PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
 465                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 466                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 467                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 468                      0 << 0);
 469
 470         /*
 471          * peri clock pll source selection and
 472          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 473          */
 474         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 475         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 476
 477         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 478         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 479                 PERI_ACLK_HZ && (hclk_div < 0x4));
 480
 481         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 482         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 483                 PERI_ACLK_HZ && (pclk_div < 0x4));
 484
 485         rk_clrsetreg(&cru->cru_clksel_con[10],
 486                      PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
 487                      PERI_ACLK_DIV_MASK,
 488                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 489                      pclk_div << PERI_PCLK_DIV_SHIFT |
 490                      hclk_div << PERI_HCLK_DIV_SHIFT |
 491                      aclk_div << PERI_ACLK_DIV_SHIFT);
 492
 493         /* PLL enter normal-mode */
 494         rk_clrsetreg(&cru->cru_mode_con,
 495                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 496                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 497                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 498 }
 499
 500 void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
 501 {
 502         /* pll enter slow-mode */
 503         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 504                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 505
 506         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 507
 508         /* waiting for pll lock */
 509         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 510                 udelay(1);
 511
 512         /*
 513          * core clock pll source selection and
 514          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 515          * core clock select apll, apll clk = 1800MHz
 516          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 517          */
 518         rk_clrsetreg(&cru->cru_clksel_con[0],
 519                      CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
 520                      M0_DIV_MASK,
 521                      0 << A17_DIV_SHIFT |
 522                      3 << MP_DIV_SHIFT |
 523                      1 << M0_DIV_SHIFT);
 524
 525         /*
 526          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 527          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 528          */
 529         rk_clrsetreg(&cru->cru_clksel_con[37],
 530                      CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
 531                      PCLK_CORE_DBG_DIV_MASK,
 532                      1 << CLK_L2RAM_DIV_SHIFT |
 533                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 534                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 535
 536         /* PLL enter normal-mode */
 537         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 538                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 539 }
 540
 541 /* Get pll rate by id */
 542 static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
 543                                    enum rk_clk_id clk_id)
 544 {
 545         uint32_t nr, no, nf;
 546         uint32_t con;
 547         int pll_id = rk_pll_id(clk_id);
 548         struct rk3288_pll *pll = &cru->pll[pll_id];
 549         static u8 clk_shift[CLK_COUNT] = {
 550                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 551                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 552         };
 553         uint shift;
 554
 555         con = readl(&cru->cru_mode_con);
 556         shift = clk_shift[clk_id];
 557         switch ((con >> shift) & CRU_MODE_MASK) {
 558         case APLL_MODE_SLOW:
 559                 return OSC_HZ;
 560         case APLL_MODE_NORMAL:
 561                 /* normal mode */
 562                 con = readl(&pll->con0);
 563                 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
 564                 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
 565                 con = readl(&pll->con1);
 566                 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
 567
 568                 return (24 * nf / (nr * no)) * 1000000;
 569         case APLL_MODE_DEEP:
 570         default:
 571                 return 32768;
 572         }
 573 }
 574
 575 static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 576                                   int periph)
 577 {
 578         uint src_rate;
 579         uint div, mux;
 580         u32 con;
 581
 582         switch (periph) {
 583         case HCLK_EMMC:
 584         case SCLK_EMMC:
 585                 con = readl(&cru->cru_clksel_con[12]);
 586                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 587                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 588                 break;
 589         case HCLK_SDMMC:
 590         case SCLK_SDMMC:
 591                 con = readl(&cru->cru_clksel_con[11]);
 592                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 593                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 594                 break;
 595         case HCLK_SDIO0:
 596         case SCLK_SDIO0:
 597                 con = readl(&cru->cru_clksel_con[12]);
 598                 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
 599                 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 600                 break;
 601         default:
 602                 return -EINVAL;
 603         }
 604
 605         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 606         return DIV_TO_RATE(src_rate, div);
 607 }
 608
 609 static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 610                                   int  periph, uint freq)
 611 {
 612         int src_clk_div;
 613         int mux;
 614
 615         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 616         /* mmc clock default div 2 internal, need provide double in cru */
 617         src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
 618
 619         if (src_clk_div > 0x3f) {
 620                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
 621                 assert(src_clk_div < 0x40);
 622                 mux = EMMC_PLL_SELECT_24MHZ;
 623                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 624                        (int)MMC0_PLL_SELECT_24MHZ);
 625         } else {
 626                 mux = EMMC_PLL_SELECT_GENERAL;
 627                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 628                        (int)MMC0_PLL_SELECT_GENERAL);
 629         }
 630         switch (periph) {
 631         case HCLK_EMMC:
 632         case SCLK_EMMC:
 633                 rk_clrsetreg(&cru->cru_clksel_con[12],
 634                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 635                              mux << EMMC_PLL_SHIFT |
 636                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 637                 break;
 638         case HCLK_SDMMC:
 639         case SCLK_SDMMC:
 640                 rk_clrsetreg(&cru->cru_clksel_con[11],
 641                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 642                              mux << MMC0_PLL_SHIFT |
 643                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 644                 break;
 645         case HCLK_SDIO0:
 646         case SCLK_SDIO0:
 647                 rk_clrsetreg(&cru->cru_clksel_con[12],
 648                              SDIO0_PLL_MASK | SDIO0_DIV_MASK,
 649                              mux << SDIO0_PLL_SHIFT |
 650                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 651                 break;
 652         default:
 653                 return -EINVAL;
 654         }
 655
 656         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 657 }
 658
 659 static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 660                                   int periph)
 661 {
 662         uint div, mux;
 663         u32 con;
 664
 665         switch (periph) {
 666         case SCLK_SPI0:
 667                 con = readl(&cru->cru_clksel_con[25]);
 668                 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
 669                 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
 670                 break;
 671         case SCLK_SPI1:
 672                 con = readl(&cru->cru_clksel_con[25]);
 673                 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
 674                 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
 675                 break;
 676         case SCLK_SPI2:
 677                 con = readl(&cru->cru_clksel_con[39]);
 678                 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
 679                 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 680                 break;
 681         default:
 682                 return -EINVAL;
 683         }
 684         assert(mux == SPI0_PLL_SELECT_GENERAL);
 685
 686         return DIV_TO_RATE(gclk_rate, div);
 687 }
 688
 689 static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 690                                   int periph, uint freq)
 691 {
 692         int src_clk_div;
 693
 694         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 695         src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
 696         assert(src_clk_div < 128);
 697         switch (periph) {
 698         case SCLK_SPI0:
 699                 rk_clrsetreg(&cru->cru_clksel_con[25],
 700                              SPI0_PLL_MASK | SPI0_DIV_MASK,
 701                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 702                              src_clk_div << SPI0_DIV_SHIFT);
 703                 break;
 704         case SCLK_SPI1:
 705                 rk_clrsetreg(&cru->cru_clksel_con[25],
 706                              SPI1_PLL_MASK | SPI1_DIV_MASK,
 707                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 708                              src_clk_div << SPI1_DIV_SHIFT);
 709                 break;
 710         case SCLK_SPI2:
 711                 rk_clrsetreg(&cru->cru_clksel_con[39],
 712                              SPI2_PLL_MASK | SPI2_DIV_MASK,
 713                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 714                              src_clk_div << SPI2_DIV_SHIFT);
 715                 break;
 716         default:
 717                 return -EINVAL;
 718         }
 719
 720         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 721 }
 722
 723 static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
 724 {
 725         u32 div, val;
 726
 727         val = readl(&cru->cru_clksel_con[24]);
 728         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 729                                CLK_SARADC_DIV_CON_WIDTH);
 730
 731         return DIV_TO_RATE(OSC_HZ, div);
 732 }
 733
 734 static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 735 {
 736         int src_clk_div;
 737
 738         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 739         assert(src_clk_div < 128);
 740
 741         rk_clrsetreg(&cru->cru_clksel_con[24],
 742                      CLK_SARADC_DIV_CON_MASK,
 743                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 744
 745         return rockchip_saradc_get_clk(cru);
 746 }
 747
 748 static ulong rk3288_clk_get_rate(struct clk *clk)
 749 {
 750         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 751         ulong new_rate, gclk_rate;
 752
 753         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 754         switch (clk->id) {
 755         case 0 ... 63:
 756                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 757                 break;
 758         case HCLK_EMMC:
 759         case HCLK_SDMMC:
 760         case HCLK_SDIO0:
 761         case SCLK_EMMC:
 762         case SCLK_SDMMC:
 763         case SCLK_SDIO0:
 764                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 765                 break;
 766         case SCLK_SPI0:
 767         case SCLK_SPI1:
 768         case SCLK_SPI2:
 769                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 770                 break;
 771         case PCLK_I2C0:
 772         case PCLK_I2C1:
 773         case PCLK_I2C2:
 774         case PCLK_I2C3:
 775         case PCLK_I2C4:
 776         case PCLK_I2C5:
 777                 return gclk_rate;
 778         case PCLK_PWM:
 779                 return PD_BUS_PCLK_HZ;
 780         case SCLK_SARADC:
 781                 new_rate = rockchip_saradc_get_clk(priv->cru);
 782                 break;
 783         default:
 784                 return -ENOENT;
 785         }
 786
 787         return new_rate;
 788 }
 789
 790 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 791 {
 792         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 793         struct rockchip_cru *cru = priv->cru;
 794         ulong new_rate, gclk_rate;
 795
 796         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 797         switch (clk->id) {
 798         case PLL_APLL:
 799                 /* We only support a fixed rate here */
 800                 if (rate != 1800000000)
 801                         return -EINVAL;
 802                 rk3288_clk_configure_cpu(priv->cru, priv->grf);
 803                 new_rate = rate;
 804                 break;
 805         case CLK_DDR:
 806                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 807                 break;
 808         case HCLK_EMMC:
 809         case HCLK_SDMMC:
 810         case HCLK_SDIO0:
 811         case SCLK_EMMC:
 812         case SCLK_SDMMC:
 813         case SCLK_SDIO0:
 814                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 815                 break;
 816         case SCLK_SPI0:
 817         case SCLK_SPI1:
 818         case SCLK_SPI2:
 819                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 820                 break;
 821 #ifndef CONFIG_SPL_BUILD
 822         case SCLK_I2S0:
 823                 new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
 824                 break;
 825         case SCLK_MAC:
 826                 new_rate = rockchip_mac_set_clk(priv->cru, rate);
 827                 break;
 828         case DCLK_VOP0:
 829         case DCLK_VOP1:
 830                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 831                 break;
 832         case SCLK_EDP_24M:
 833                 /* clk_edp_24M source: 24M */
 834                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 835
 836                 /* rst edp */
 837                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 838                 udelay(1);
 839                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 840                 new_rate = rate;
 841                 break;
 842         case ACLK_VOP0:
 843         case ACLK_VOP1: {
 844                 u32 div;
 845
 846                 /* vop aclk source clk: cpll */
 847                 div = CPLL_HZ / rate;
 848                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 849
 850                 switch (clk->id) {
 851                 case ACLK_VOP0:
 852                         rk_clrsetreg(&cru->cru_clksel_con[31],
 853                                      3 << 6 | 0x1f << 0,
 854                                      0 << 6 | (div - 1) << 0);
 855                         break;
 856                 case ACLK_VOP1:
 857                         rk_clrsetreg(&cru->cru_clksel_con[31],
 858                                      3 << 14 | 0x1f << 8,
 859                                      0 << 14 | (div - 1) << 8);
 860                         break;
 861                 }
 862                 new_rate = rate;
 863                 break;
 864         }
 865         case PCLK_HDMI_CTRL:
 866                 /* enable pclk hdmi ctrl */
 867                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 868
 869                 /* software reset hdmi */
 870                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 871                 udelay(1);
 872                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 873                 new_rate = rate;
 874                 break;
 875 #endif
 876         case SCLK_SARADC:
 877                 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
 878                 break;
 879         case PLL_GPLL:
 880         case PLL_CPLL:
 881         case PLL_NPLL:
 882         case ACLK_CPU:
 883         case HCLK_CPU:
 884         case PCLK_CPU:
 885         case ACLK_PERI:
 886         case HCLK_PERI:
 887         case PCLK_PERI:
 888         case SCLK_UART0:
 889                 return 0;
 890         default:
 891                 return -ENOENT;
 892         }
 893
 894         return new_rate;
 895 }
 896
 897 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
 898 {
 899         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 900         struct rockchip_cru *cru = priv->cru;
 901         const char *clock_output_name;
 902         int ret;
 903
 904         /*
 905          * If the requested parent is in the same clock-controller and
 906          * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
 907          * clock.
 908          */
 909         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
 910                 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
 911                 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
 912                 return 0;
 913         }
 914
 915         /*
 916          * Otherwise, we need to check the clock-output-names of the
 917          * requested parent to see if the requested id is "ext_gmac".
 918          */
 919         ret = dev_read_string_index(parent->dev, "clock-output-names",
 920                                     parent->id, &clock_output_name);
 921         if (ret < 0)
 922                 return -ENODATA;
 923
 924         /* If this is "ext_gmac", switch to the external clock input */
 925         if (!strcmp(clock_output_name, "ext_gmac")) {
 926                 debug("%s: switching GMAC to external clock\n", __func__);
 927                 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
 928                              RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 929                 return 0;
 930         }
 931
 932         return -EINVAL;
 933 }
 934
 935 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
 936 {
 937         switch (clk->id) {
 938         case SCLK_MAC:
 939                 return rk3288_gmac_set_parent(clk, parent);
 940         case SCLK_USBPHY480M_SRC:
 941                 return 0;
 942         }
 943
 944         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 945         return -ENOENT;
 946 }
 947
 948 static struct clk_ops rk3288_clk_ops = {
 949         .get_rate       = rk3288_clk_get_rate,
 950         .set_rate       = rk3288_clk_set_rate,
 951 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 952         .set_parent     = rk3288_clk_set_parent,
 953 #endif
 954 };
 955
 956 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 957 {
 958 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 959         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 960
 961         priv->cru = dev_read_addr_ptr(dev);
 962 #endif
 963
 964         return 0;
 965 }
 966
 967 static int rk3288_clk_probe(struct udevice *dev)
 968 {
 969         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 970         bool init_clocks = false;
 971
 972         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 973         if (IS_ERR(priv->grf))
 974                 return PTR_ERR(priv->grf);
 975 #ifdef CONFIG_SPL_BUILD
 976 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 977         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 978
 979         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 980 #endif
 981         init_clocks = true;
 982 #endif
 983         if (!(gd->flags & GD_FLG_RELOC)) {
 984                 u32 reg;
 985
 986                 /*
 987                  * Init clocks in U-Boot proper if the NPLL is runnning. This
 988                  * indicates that a previous boot loader set up the clocks, so
 989                  * we need to redo it. U-Boot's SPL does not set this clock.
 990                  */
 991                 reg = readl(&priv->cru->cru_mode_con);
 992                 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
 993                                 NPLL_MODE_NORMAL)
 994                         init_clocks = true;
 995         }
 996
 997         if (init_clocks)
 998                 rkclk_init(priv->cru, priv->grf);
 999
1000         return 0;
1001 }
1002
1003 static int rk3288_clk_bind(struct udevice *dev)
1004 {
1005         int ret;
1006         struct udevice *sys_child;
1007         struct sysreset_reg *priv;
1008
1009         /* The reset driver does not have a device node, so bind it here */
1010         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1011                                  &sys_child);
1012         if (ret) {
1013                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1014         } else {
1015                 priv = malloc(sizeof(struct sysreset_reg));
1016                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1017                                                     cru_glb_srst_fst_value);
1018                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1019                                                     cru_glb_srst_snd_value);
1020                 sys_child->priv = priv;
1021         }
1022
1023 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1024         ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
1025         ret = rockchip_reset_bind(dev, ret, 12);
1026         if (ret)
1027                 debug("Warning: software reset driver bind faile\n");
1028 #endif
1029
1030         return 0;
1031 }
1032
1033 static const struct udevice_id rk3288_clk_ids[] = {
1034         { .compatible = "rockchip,rk3288-cru" },
1035         { }
1036 };
1037
1038 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
1039         .name           = "rockchip_rk3288_cru",
1040         .id             = UCLASS_CLK,
1041         .of_match       = rk3288_clk_ids,
1042         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
1043         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
1044         .ops            = &rk3288_clk_ops,
1045         .bind           = rk3288_clk_bind,
1046         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
1047         .probe          = rk3288_clk_probe,
1048 };