drivers/clk/rockchip/clk_rk3188.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dt-structs.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <mapmem.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3188.h>
  18 #include <asm/arch-rockchip/grf_rk3188.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <dt-bindings/clock/rk3188-cru.h>
  21 #include <dm/device-internal.h>
  22 #include <dm/lists.h>
  23 #include <dm/uclass-internal.h>
  24 #include <linux/err.h>
  25 #include <linux/log2.h>
  26
  27 enum rk3188_clk_type {
  28         RK3188_CRU,
  29         RK3188A_CRU,
  30 };
  31
  32 struct rk3188_clk_plat {
  33 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  34         struct dtd_rockchip_rk3188_cru dtd;
  35 #endif
  36 };
  37
  38 struct pll_div {
  39         u32 nr;
  40         u32 nf;
  41         u32 no;
  42 };
  43
  44 enum {
  45         VCO_MAX_HZ      = 2200U * 1000000,
  46         VCO_MIN_HZ      = 440 * 1000000,
  47         OUTPUT_MAX_HZ   = 2200U * 1000000,
  48         OUTPUT_MIN_HZ   = 30 * 1000000,
  49         FREF_MAX_HZ     = 2200U * 1000000,
  50         FREF_MIN_HZ     = 30 * 1000,
  51 };
  52
  53 enum {
  54         /* PLL CON0 */
  55         PLL_OD_MASK             = 0x0f,
  56
  57         /* PLL CON1 */
  58         PLL_NF_MASK             = 0x1fff,
  59
  60         /* PLL CON2 */
  61         PLL_BWADJ_MASK          = 0x0fff,
  62
  63         /* PLL CON3 */
  64         PLL_RESET_SHIFT         = 5,
  65
  66         /* GRF_SOC_STATUS0 */
  67         SOCSTS_DPLL_LOCK        = 1 << 5,
  68         SOCSTS_APLL_LOCK        = 1 << 6,
  69         SOCSTS_CPLL_LOCK        = 1 << 7,
  70         SOCSTS_GPLL_LOCK        = 1 << 8,
  71 };
  72
  73 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  74
  75 #define PLL_DIVISORS(hz, _nr, _no) {\
  76         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  77         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  78                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  79                        "divisors on line " __stringify(__LINE__));
  80
  81 /* Keep divisors as low as possible to reduce jitter and power usage */
  82 #ifdef CONFIG_SPL_BUILD
  83 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  84 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  85 #endif
  86
  87 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
  88                          const struct pll_div *div, bool has_bwadj)
  89 {
  90         int pll_id = rk_pll_id(clk_id);
  91         struct rk3188_pll *pll = &cru->pll[pll_id];
  92         /* All PLLs have same VCO and output frequency range restrictions. */
  93         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  94         uint output_hz = vco_hz / div->no;
  95
  96         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  97               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  98         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  99                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 100                (div->no == 1 || !(div->no % 2)));
 101
 102         /* enter reset */
 103         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 104
 105         rk_clrsetreg(&pll->con0,
 106                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 107                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 108         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 109
 110         if (has_bwadj)
 111                 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 112
 113         udelay(10);
 114
 115         /* return from reset */
 116         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 117
 118         return 0;
 119 }
 120
 121 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
 122                                unsigned int hz, bool has_bwadj)
 123 {
 124         static const struct pll_div dpll_cfg[] = {
 125                 {.nf = 75, .nr = 1, .no = 6},
 126                 {.nf = 400, .nr = 9, .no = 2},
 127                 {.nf = 500, .nr = 9, .no = 2},
 128                 {.nf = 100, .nr = 3, .no = 1},
 129         };
 130         int cfg;
 131
 132         switch (hz) {
 133         case 300000000:
 134                 cfg = 0;
 135                 break;
 136         case 533000000: /* actually 533.3P MHz */
 137                 cfg = 1;
 138                 break;
 139         case 666000000: /* actually 666.6P MHz */
 140                 cfg = 2;
 141                 break;
 142         case 800000000:
 143                 cfg = 3;
 144                 break;
 145         default:
 146                 debug("Unsupported SDRAM frequency");
 147                 return -EINVAL;
 148         }
 149
 150         /* pll enter slow-mode */
 151         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 152                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 153
 154         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
 155
 156         /* wait for pll lock */
 157         while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
 158                 udelay(1);
 159
 160         /* PLL enter normal-mode */
 161         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 162                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 163
 164         return 0;
 165 }
 166
 167 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
 168                               unsigned int hz, bool has_bwadj)
 169 {
 170         static const struct pll_div apll_cfg[] = {
 171                 {.nf = 50, .nr = 1, .no = 2},
 172                 {.nf = 67, .nr = 1, .no = 1},
 173         };
 174         int div_core_peri, div_aclk_core, cfg;
 175
 176         /*
 177          * We support two possible frequencies, the safe 600MHz
 178          * which will work with default pmic settings and will
 179          * be set in SPL to get away from the 24MHz default and
 180          * the maximum of 1.6Ghz, which boards can set if they
 181          * were able to get pmic support for it.
 182          */
 183         switch (hz) {
 184         case APLL_SAFE_HZ:
 185                 cfg = 0;
 186                 div_core_peri = 1;
 187                 div_aclk_core = 3;
 188                 break;
 189         case APLL_HZ:
 190                 cfg = 1;
 191                 div_core_peri = 2;
 192                 div_aclk_core = 3;
 193                 break;
 194         default:
 195                 debug("Unsupported ARMCLK frequency");
 196                 return -EINVAL;
 197         }
 198
 199         /* pll enter slow-mode */
 200         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
 201                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 202
 203         rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
 204
 205         /* waiting for pll lock */
 206         while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
 207                 udelay(1);
 208
 209         /* Set divider for peripherals attached to the cpu core. */
 210         rk_clrsetreg(&cru->cru_clksel_con[0],
 211                 CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
 212                 div_core_peri << CORE_PERI_DIV_SHIFT);
 213
 214         /* set up dependent divisor for aclk_core */
 215         rk_clrsetreg(&cru->cru_clksel_con[1],
 216                 CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
 217                 div_aclk_core << CORE_ACLK_DIV_SHIFT);
 218
 219         /* PLL enter normal-mode */
 220         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
 221                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 222
 223         return hz;
 224 }
 225
 226 /* Get pll rate by id */
 227 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
 228                                    enum rk_clk_id clk_id)
 229 {
 230         uint32_t nr, no, nf;
 231         uint32_t con;
 232         int pll_id = rk_pll_id(clk_id);
 233         struct rk3188_pll *pll = &cru->pll[pll_id];
 234         static u8 clk_shift[CLK_COUNT] = {
 235                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 236                 GPLL_MODE_SHIFT
 237         };
 238         uint shift;
 239
 240         con = readl(&cru->cru_mode_con);
 241         shift = clk_shift[clk_id];
 242         switch ((con >> shift) & APLL_MODE_MASK) {
 243         case APLL_MODE_SLOW:
 244                 return OSC_HZ;
 245         case APLL_MODE_NORMAL:
 246                 /* normal mode */
 247                 con = readl(&pll->con0);
 248                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 249                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 250                 con = readl(&pll->con1);
 251                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 252
 253                 return (24 * nf / (nr * no)) * 1000000;
 254         case APLL_MODE_DEEP:
 255         default:
 256                 return 32768;
 257         }
 258 }
 259
 260 static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 261                                   int periph)
 262 {
 263         uint div;
 264         u32 con;
 265
 266         switch (periph) {
 267         case HCLK_EMMC:
 268         case SCLK_EMMC:
 269                 con = readl(&cru->cru_clksel_con[12]);
 270                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 271                 break;
 272         case HCLK_SDMMC:
 273         case SCLK_SDMMC:
 274                 con = readl(&cru->cru_clksel_con[11]);
 275                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 276                 break;
 277         case HCLK_SDIO:
 278         case SCLK_SDIO:
 279                 con = readl(&cru->cru_clksel_con[12]);
 280                 div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
 281                 break;
 282         default:
 283                 return -EINVAL;
 284         }
 285
 286         return DIV_TO_RATE(gclk_rate, div) / 2;
 287 }
 288
 289 static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
 290                                   int  periph, uint freq)
 291 {
 292         int src_clk_div;
 293
 294         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 295         /* mmc clock defaulg div 2 internal, need provide double in cru */
 296         src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
 297         assert(src_clk_div <= 0x3f);
 298
 299         switch (periph) {
 300         case HCLK_EMMC:
 301         case SCLK_EMMC:
 302                 rk_clrsetreg(&cru->cru_clksel_con[12],
 303                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 304                              src_clk_div << EMMC_DIV_SHIFT);
 305                 break;
 306         case HCLK_SDMMC:
 307         case SCLK_SDMMC:
 308                 rk_clrsetreg(&cru->cru_clksel_con[11],
 309                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 310                              src_clk_div << MMC0_DIV_SHIFT);
 311                 break;
 312         case HCLK_SDIO:
 313         case SCLK_SDIO:
 314                 rk_clrsetreg(&cru->cru_clksel_con[12],
 315                              SDIO_DIV_MASK << SDIO_DIV_SHIFT,
 316                              src_clk_div << SDIO_DIV_SHIFT);
 317                 break;
 318         default:
 319                 return -EINVAL;
 320         }
 321
 322         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 323 }
 324
 325 static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
 326                                   int periph)
 327 {
 328         uint div;
 329         u32 con;
 330
 331         switch (periph) {
 332         case SCLK_SPI0:
 333                 con = readl(&cru->cru_clksel_con[25]);
 334                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 335                 break;
 336         case SCLK_SPI1:
 337                 con = readl(&cru->cru_clksel_con[25]);
 338                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 339                 break;
 340         default:
 341                 return -EINVAL;
 342         }
 343
 344         return DIV_TO_RATE(gclk_rate, div);
 345 }
 346
 347 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
 348                                   int periph, uint freq)
 349 {
 350         int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
 351
 352         assert(src_clk_div < 128);
 353         switch (periph) {
 354         case SCLK_SPI0:
 355                 assert(src_clk_div <= SPI0_DIV_MASK);
 356                 rk_clrsetreg(&cru->cru_clksel_con[25],
 357                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 358                              src_clk_div << SPI0_DIV_SHIFT);
 359                 break;
 360         case SCLK_SPI1:
 361                 assert(src_clk_div <= SPI1_DIV_MASK);
 362                 rk_clrsetreg(&cru->cru_clksel_con[25],
 363                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 364                              src_clk_div << SPI1_DIV_SHIFT);
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         }
 369
 370         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 371 }
 372
 373 #ifdef CONFIG_SPL_BUILD
 374 static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
 375                        bool has_bwadj)
 376 {
 377         u32 aclk_div, hclk_div, pclk_div, h2p_div;
 378
 379         /* pll enter slow-mode */
 380         rk_clrsetreg(&cru->cru_mode_con,
 381                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 382                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 383                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 384                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 385
 386         /* init pll */
 387         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
 388         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
 389
 390         /* waiting for pll lock */
 391         while ((readl(&grf->soc_status0) &
 392                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 393                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 394                 udelay(1);
 395
 396         /*
 397          * cpu clock pll source selection and
 398          * reparent aclk_cpu_pre from apll to gpll
 399          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 400          */
 401         aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
 402         assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 403
 404         rk_clrsetreg(&cru->cru_clksel_con[0],
 405                      CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
 406                      A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
 407                      CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
 408                      aclk_div << A9_CPU_DIV_SHIFT);
 409
 410         hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
 411         assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
 412         pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
 413         assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
 414         h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
 415         assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
 416
 417         rk_clrsetreg(&cru->cru_clksel_con[1],
 418                      AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
 419                      CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
 420                      CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
 421                      h2p_div << AHB2APB_DIV_SHIFT |
 422                      pclk_div << CPU_PCLK_DIV_SHIFT |
 423                      hclk_div << CPU_HCLK_DIV_SHIFT);
 424
 425         /*
 426          * peri clock pll source selection and
 427          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 428          */
 429         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 430         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 431
 432         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 433         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 434                 PERI_ACLK_HZ && (hclk_div < 0x4));
 435
 436         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 437         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 438                 PERI_ACLK_HZ && (pclk_div < 0x4));
 439
 440         rk_clrsetreg(&cru->cru_clksel_con[10],
 441                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 442                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 443                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 444                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 445                      pclk_div << PERI_PCLK_DIV_SHIFT |
 446                      hclk_div << PERI_HCLK_DIV_SHIFT |
 447                      aclk_div << PERI_ACLK_DIV_SHIFT);
 448
 449         /* PLL enter normal-mode */
 450         rk_clrsetreg(&cru->cru_mode_con,
 451                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 452                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 453                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 454                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 455
 456         rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
 457 }
 458 #endif
 459
 460 static ulong rk3188_clk_get_rate(struct clk *clk)
 461 {
 462         struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
 463         ulong new_rate, gclk_rate;
 464
 465         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 466         switch (clk->id) {
 467         case 1 ... 4:
 468                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 469                 break;
 470         case HCLK_EMMC:
 471         case HCLK_SDMMC:
 472         case HCLK_SDIO:
 473         case SCLK_EMMC:
 474         case SCLK_SDMMC:
 475         case SCLK_SDIO:
 476                 new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
 477                                                 clk->id);
 478                 break;
 479         case SCLK_SPI0:
 480         case SCLK_SPI1:
 481                 new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
 482                                                 clk->id);
 483                 break;
 484         case PCLK_I2C0:
 485         case PCLK_I2C1:
 486         case PCLK_I2C2:
 487         case PCLK_I2C3:
 488         case PCLK_I2C4:
 489                 return gclk_rate;
 490         default:
 491                 return -ENOENT;
 492         }
 493
 494         return new_rate;
 495 }
 496
 497 static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
 498 {
 499         struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
 500         struct rk3188_cru *cru = priv->cru;
 501         ulong new_rate;
 502
 503         switch (clk->id) {
 504         case PLL_APLL:
 505                 new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
 506                                                priv->has_bwadj);
 507                 break;
 508         case CLK_DDR:
 509                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
 510                                                priv->has_bwadj);
 511                 break;
 512         case HCLK_EMMC:
 513         case HCLK_SDMMC:
 514         case HCLK_SDIO:
 515         case SCLK_EMMC:
 516         case SCLK_SDMMC:
 517         case SCLK_SDIO:
 518                 new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
 519                                                 clk->id, rate);
 520                 break;
 521         case SCLK_SPI0:
 522         case SCLK_SPI1:
 523                 new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
 524                                                 clk->id, rate);
 525                 break;
 526         default:
 527                 return -ENOENT;
 528         }
 529
 530         return new_rate;
 531 }
 532
 533 static struct clk_ops rk3188_clk_ops = {
 534         .get_rate       = rk3188_clk_get_rate,
 535         .set_rate       = rk3188_clk_set_rate,
 536 };
 537
 538 static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
 539 {
 540 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 541         struct rk3188_clk_priv *priv = dev_get_priv(dev);
 542
 543         priv->cru = dev_read_addr_ptr(dev);
 544 #endif
 545
 546         return 0;
 547 }
 548
 549 static int rk3188_clk_probe(struct udevice *dev)
 550 {
 551         struct rk3188_clk_priv *priv = dev_get_priv(dev);
 552         enum rk3188_clk_type type = dev_get_driver_data(dev);
 553
 554         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 555         if (IS_ERR(priv->grf))
 556                 return PTR_ERR(priv->grf);
 557         priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
 558
 559 #ifdef CONFIG_SPL_BUILD
 560 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 561         struct rk3188_clk_plat *plat = dev_get_platdata(dev);
 562
 563         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 564 #endif
 565
 566         rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
 567
 568         /* Init CPU frequency */
 569         rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
 570 #endif
 571
 572         return 0;
 573 }
 574
 575 static int rk3188_clk_bind(struct udevice *dev)
 576 {
 577         int ret;
 578         struct udevice *sys_child;
 579         struct sysreset_reg *priv;
 580
 581         /* The reset driver does not have a device node, so bind it here */
 582         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 583                                  &sys_child);
 584         if (ret) {
 585                 debug("Warning: No sysreset driver: ret=%d\n", ret);
 586         } else {
 587                 priv = malloc(sizeof(struct sysreset_reg));
 588                 priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
 589                                                     cru_glb_srst_fst_value);
 590                 priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
 591                                                     cru_glb_srst_snd_value);
 592                 sys_child->priv = priv;
 593         }
 594
 595 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
 596         ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
 597         ret = rockchip_reset_bind(dev, ret, 9);
 598         if (ret)
 599                 debug("Warning: software reset driver bind faile\n");
 600 #endif
 601
 602         return 0;
 603 }
 604
 605 static const struct udevice_id rk3188_clk_ids[] = {
 606         { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
 607         { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
 608         { }
 609 };
 610
 611 U_BOOT_DRIVER(rockchip_rk3188_cru) = {
 612         .name                   = "rockchip_rk3188_cru",
 613         .id                     = UCLASS_CLK,
 614         .of_match               = rk3188_clk_ids,
 615         .priv_auto_alloc_size   = sizeof(struct rk3188_clk_priv),
 616         .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
 617         .ops                    = &rk3188_clk_ops,
 618         .bind                   = rk3188_clk_bind,
 619         .ofdata_to_platdata     = rk3188_clk_ofdata_to_platdata,
 620         .probe                  = rk3188_clk_probe,
 621 };