drivers/clk/rockchip/clk_rk3128.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch-rockchip/clock.h>
  13 #include <asm/arch-rockchip/cru_rk3128.h>
  14 #include <asm/arch-rockchip/hardware.h>
  15 #include <bitfield.h>
  16 #include <dm/lists.h>
  17 #include <dt-bindings/clock/rk3128-cru.h>
  18 #include <linux/log2.h>
  19
  20 enum {
  21         VCO_MAX_HZ      = 2400U * 1000000,
  22         VCO_MIN_HZ      = 600 * 1000000,
  23         OUTPUT_MAX_HZ   = 2400U * 1000000,
  24         OUTPUT_MIN_HZ   = 24 * 1000000,
  25 };
  26
  27 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  28
  29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  30         .refdiv = _refdiv,\
  31         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  32         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  33
  34 /* use integer mode*/
  35 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  36 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  37
  38 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
  39                          const struct pll_div *div)
  40 {
  41         int pll_id = rk_pll_id(clk_id);
  42         struct rk3128_pll *pll = &cru->pll[pll_id];
  43
  44         /* All PLLs have same VCO and output frequency range restrictions. */
  45         uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  46         uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  47
  48         debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
  49               pll, div->fbdiv, div->refdiv, div->postdiv1,
  50               div->postdiv2, vco_hz, output_hz);
  51         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  52                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  53
  54         /* use integer mode */
  55         rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  56         /* Power down */
  57         rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
  58
  59         rk_clrsetreg(&pll->con0,
  60                      PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  61                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  62         rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  63                      (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  64                      div->refdiv << PLL_REFDIV_SHIFT));
  65
  66         /* Power Up */
  67         rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
  68
  69         /* waiting for pll lock */
  70         while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  71                 udelay(1);
  72
  73         return 0;
  74 }
  75
  76 static int pll_para_config(u32 freq_hz, struct pll_div *div)
  77 {
  78         u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
  79         u32 postdiv1, postdiv2 = 1;
  80         u32 fref_khz;
  81         u32 diff_khz, best_diff_khz;
  82         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
  83         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
  84         u32 vco_khz;
  85         u32 freq_khz = freq_hz / 1000;
  86
  87         if (!freq_hz) {
  88                 printf("%s: the frequency can't be 0 Hz\n", __func__);
  89                 return -1;
  90         }
  91
  92         postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
  93         if (postdiv1 > max_postdiv1) {
  94                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
  95                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
  96         }
  97
  98         vco_khz = freq_khz * postdiv1 * postdiv2;
  99
 100         if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
 101             postdiv2 > max_postdiv2) {
 102                 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
 103                        __func__, freq_hz);
 104                 return -1;
 105         }
 106
 107         div->postdiv1 = postdiv1;
 108         div->postdiv2 = postdiv2;
 109
 110         best_diff_khz = vco_khz;
 111         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 112                 fref_khz = ref_khz / refdiv;
 113
 114                 fbdiv = vco_khz / fref_khz;
 115                 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
 116                         continue;
 117                 diff_khz = vco_khz - fbdiv * fref_khz;
 118                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 119                         fbdiv++;
 120                         diff_khz = fref_khz - diff_khz;
 121                 }
 122
 123                 if (diff_khz >= best_diff_khz)
 124                         continue;
 125
 126                 best_diff_khz = diff_khz;
 127                 div->refdiv = refdiv;
 128                 div->fbdiv = fbdiv;
 129         }
 130
 131         if (best_diff_khz > 4 * (1000)) {
 132                 printf("%s: Failed to match output frequency %u bestis %u Hz\n",
 133                        __func__, freq_hz,
 134                        best_diff_khz * 1000);
 135                 return -1;
 136         }
 137         return 0;
 138 }
 139
 140 static void rkclk_init(struct rk3128_cru *cru)
 141 {
 142         u32 aclk_div;
 143         u32 hclk_div;
 144         u32 pclk_div;
 145
 146         /* pll enter slow-mode */
 147         rk_clrsetreg(&cru->cru_mode_con,
 148                      GPLL_MODE_MASK | APLL_MODE_MASK,
 149                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 150                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 151
 152         /* init pll */
 153         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 154         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 155
 156         /*
 157          * select apll as cpu/core clock pll source and
 158          * set up dependent divisors for PERI and ACLK clocks.
 159          * core hz : apll = 1:1
 160          */
 161         aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
 162         assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
 163
 164         pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
 165         assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
 166
 167         rk_clrsetreg(&cru->cru_clksel_con[0],
 168                      CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
 169                      CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
 170                      0 << CORE_DIV_CON_SHIFT);
 171
 172         rk_clrsetreg(&cru->cru_clksel_con[1],
 173                      CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
 174                      aclk_div << CORE_ACLK_DIV_SHIFT |
 175                      pclk_div << CORE_PERI_DIV_SHIFT);
 176
 177         /*
 178          * select gpll as pd_bus bus clock source and
 179          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 180          */
 181         aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
 182         assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 183
 184         pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
 185         assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
 186
 187         hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
 188         assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
 189
 190         rk_clrsetreg(&cru->cru_clksel_con[0],
 191                      BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
 192                      BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
 193                      aclk_div << BUS_ACLK_DIV_SHIFT);
 194
 195         rk_clrsetreg(&cru->cru_clksel_con[1],
 196                      BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
 197                      pclk_div << BUS_PCLK_DIV_SHIFT |
 198                      hclk_div << BUS_HCLK_DIV_SHIFT);
 199
 200         /*
 201          * select gpll as pd_peri bus clock source and
 202          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 203          */
 204         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 205         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 206
 207         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 208         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 209                 PERI_ACLK_HZ && (hclk_div < 0x4));
 210
 211         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 212         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 213                 PERI_ACLK_HZ && pclk_div < 0x8);
 214
 215         rk_clrsetreg(&cru->cru_clksel_con[10],
 216                      PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
 217                      PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
 218                      PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
 219                      pclk_div << PERI_PCLK_DIV_SHIFT |
 220                      hclk_div << PERI_HCLK_DIV_SHIFT |
 221                      aclk_div << PERI_ACLK_DIV_SHIFT);
 222
 223         /* PLL enter normal-mode */
 224         rk_clrsetreg(&cru->cru_mode_con,
 225                      GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
 226                      GPLL_MODE_NORM << GPLL_MODE_SHIFT |
 227                      APLL_MODE_NORM << APLL_MODE_SHIFT |
 228                      CPLL_MODE_NORM << CPLL_MODE_SHIFT);
 229
 230         /*fix NAND controller  working clock max to 150Mhz */
 231         rk_clrsetreg(&cru->cru_clksel_con[2],
 232                      NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
 233                      NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
 234                      3 << NANDC_CLK_DIV_SHIFT);
 235 }
 236
 237 /* Get pll rate by id */
 238 static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
 239                               enum rk_clk_id clk_id)
 240 {
 241         u32 refdiv, fbdiv, postdiv1, postdiv2;
 242         u32 con;
 243         int pll_id = rk_pll_id(clk_id);
 244         struct rk3128_pll *pll = &cru->pll[pll_id];
 245         static u8 clk_shift[CLK_COUNT] = {
 246                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 247                 GPLL_MODE_SHIFT, 0xff
 248         };
 249         static u32 clk_mask[CLK_COUNT] = {
 250                 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
 251                 GPLL_MODE_MASK, 0xff
 252         };
 253         uint shift;
 254         uint mask;
 255
 256         con = readl(&cru->cru_mode_con);
 257         shift = clk_shift[clk_id];
 258         mask = clk_mask[clk_id];
 259
 260         switch ((con & mask) >> shift) {
 261         case GPLL_MODE_SLOW:
 262                 return OSC_HZ;
 263         case GPLL_MODE_NORM:
 264                 /* normal mode */
 265                 con = readl(&pll->con0);
 266                 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
 267                 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
 268                 con = readl(&pll->con1);
 269                 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
 270                 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
 271                 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
 272         case GPLL_MODE_DEEP:
 273         default:
 274                 return 32768;
 275         }
 276 }
 277
 278 static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
 279                                   int periph)
 280 {
 281         uint src_rate;
 282         uint div, mux;
 283         u32 con;
 284
 285         switch (periph) {
 286         case HCLK_EMMC:
 287         case SCLK_EMMC:
 288         case SCLK_EMMC_SAMPLE:
 289                 con = readl(&cru->cru_clksel_con[12]);
 290                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 291                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 292                 break;
 293         case HCLK_SDMMC:
 294         case SCLK_SDMMC:
 295                 con = readl(&cru->cru_clksel_con[11]);
 296                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 297                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 298                 break;
 299         default:
 300                 return -EINVAL;
 301         }
 302
 303         src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
 304         return DIV_TO_RATE(src_rate, div);
 305 }
 306
 307 static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
 308                                   int periph, uint freq)
 309 {
 310         int src_clk_div;
 311         int mux;
 312
 313         debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
 314
 315         /* mmc clock defaulg div 2 internal, need provide double in cru */
 316         src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 317
 318         if (src_clk_div > 128) {
 319                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
 320                 mux = EMMC_SEL_24M;
 321         } else {
 322                 mux = EMMC_SEL_GPLL;
 323         }
 324
 325         switch (periph) {
 326         case HCLK_EMMC:
 327                 rk_clrsetreg(&cru->cru_clksel_con[12],
 328                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 329                              mux << EMMC_PLL_SHIFT |
 330                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 331                 break;
 332         case HCLK_SDMMC:
 333         case SCLK_SDMMC:
 334                 rk_clrsetreg(&cru->cru_clksel_con[11],
 335                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 336                              mux << MMC0_PLL_SHIFT |
 337                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 338                 break;
 339         default:
 340                 return -EINVAL;
 341         }
 342
 343         return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
 344 }
 345
 346 static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
 347 {
 348         u32 div, con;
 349
 350         switch (clk_id) {
 351         case PCLK_I2C0:
 352         case PCLK_I2C1:
 353         case PCLK_I2C2:
 354         case PCLK_I2C3:
 355         case PCLK_PWM:
 356                 con = readl(&cru->cru_clksel_con[10]);
 357                 div = con >> 12 & 0x3;
 358                 break;
 359         default:
 360                 printf("do not support this peripheral bus\n");
 361                 return -EINVAL;
 362         }
 363
 364         return DIV_TO_RATE(PERI_ACLK_HZ, div);
 365 }
 366
 367 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
 368 {
 369         int src_clk_div;
 370
 371         src_clk_div = PERI_ACLK_HZ / hz;
 372         assert(src_clk_div - 1 < 4);
 373
 374         switch (clk_id) {
 375         case PCLK_I2C0:
 376         case PCLK_I2C1:
 377         case PCLK_I2C2:
 378         case PCLK_I2C3:
 379         case PCLK_PWM:
 380                 rk_setreg(&cru->cru_clksel_con[10],
 381                           ((src_clk_div - 1) << 12));
 382                 break;
 383         default:
 384                 printf("do not support this peripheral bus\n");
 385                 return -EINVAL;
 386         }
 387
 388         return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
 389 }
 390
 391 static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
 392 {
 393         u32 div, val;
 394
 395         val = readl(&cru->cru_clksel_con[24]);
 396         div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
 397                                SARADC_DIV_CON_WIDTH);
 398
 399         return DIV_TO_RATE(OSC_HZ, div);
 400 }
 401
 402 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
 403 {
 404         int src_clk_div;
 405
 406         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 407         assert(src_clk_div < 128);
 408
 409         rk_clrsetreg(&cru->cru_clksel_con[24],
 410                      SARADC_DIV_CON_MASK,
 411                      src_clk_div << SARADC_DIV_CON_SHIFT);
 412
 413         return rk3128_saradc_get_clk(cru);
 414 }
 415
 416 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
 417 {
 418         int src_clk_div;
 419         struct pll_div cpll_config = {0};
 420
 421         src_clk_div = GPLL_HZ / hz;
 422         assert(src_clk_div - 1 < 31);
 423
 424         switch (clk_id) {
 425         case ACLK_VIO0:
 426                 rk_clrsetreg(&cru->cru_clksel_con[31],
 427                              VIO0_PLL_MASK | VIO0_DIV_MASK,
 428                              VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
 429                              (src_clk_div - 1) << VIO0_DIV_SHIFT);
 430                 break;
 431         case ACLK_VIO1:
 432                 rk_clrsetreg(&cru->cru_clksel_con[31],
 433                              VIO1_PLL_MASK | VIO1_DIV_MASK,
 434                              VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
 435                              (src_clk_div - 1) << VIO1_DIV_SHIFT);
 436                 break;
 437         case DCLK_LCDC:
 438                 if (pll_para_config(hz, &cpll_config))
 439                         return -1;
 440                 rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
 441
 442                 rk_clrsetreg(&cru->cru_clksel_con[27],
 443                              DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
 444                              DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
 445                              (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 446                 break;
 447         default:
 448                 printf("do not support this vop freq\n");
 449                 return -EINVAL;
 450         }
 451
 452         return hz;
 453 }
 454
 455 static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
 456 {
 457         u32 div, con, parent;
 458
 459         switch (clk_id) {
 460         case ACLK_VIO0:
 461                 con = readl(&cru->cru_clksel_con[31]);
 462                 div = con  & 0x1f;
 463                 parent = GPLL_HZ;
 464                 break;
 465         case ACLK_VIO1:
 466                 con = readl(&cru->cru_clksel_con[31]);
 467                 div = (con >> 8) & 0x1f;
 468                 parent = GPLL_HZ;
 469                 break;
 470         case DCLK_LCDC:
 471                 con = readl(&cru->cru_clksel_con[27]);
 472                 div = (con >> 8) & 0xfff;
 473                 parent = rkclk_pll_get_rate(cru, CLK_CODEC);
 474                 break;
 475         default:
 476                 return -ENOENT;
 477         }
 478         return DIV_TO_RATE(parent, div);
 479 }
 480
 481 static ulong rk3128_clk_get_rate(struct clk *clk)
 482 {
 483         struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
 484
 485         switch (clk->id) {
 486         case 0 ... 63:
 487                 return rkclk_pll_get_rate(priv->cru, clk->id);
 488         case PCLK_I2C0:
 489         case PCLK_I2C1:
 490         case PCLK_I2C2:
 491         case PCLK_I2C3:
 492         case PCLK_PWM:
 493                 return rk3128_peri_get_pclk(priv->cru, clk->id);
 494         case SCLK_SARADC:
 495                 return rk3128_saradc_get_clk(priv->cru);
 496         case DCLK_LCDC:
 497         case ACLK_VIO0:
 498         case ACLK_VIO1:
 499                 return rk3128_vop_get_rate(priv->cru, clk->id);
 500         default:
 501                 return -ENOENT;
 502         }
 503 }
 504
 505 static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
 506 {
 507         struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
 508         ulong new_rate, gclk_rate;
 509
 510         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 511         switch (clk->id) {
 512         case 0 ... 63:
 513                 return 0;
 514         case DCLK_LCDC:
 515         case ACLK_VIO0:
 516         case ACLK_VIO1:
 517                 new_rate = rk3128_vop_set_clk(priv->cru,
 518                                               clk->id, rate);
 519                 break;
 520         case HCLK_EMMC:
 521                 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
 522                                                 clk->id, rate);
 523                 break;
 524         case PCLK_I2C0:
 525         case PCLK_I2C1:
 526         case PCLK_I2C2:
 527         case PCLK_I2C3:
 528         case PCLK_PWM:
 529                 new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
 530                 break;
 531         case SCLK_SARADC:
 532                 new_rate = rk3128_saradc_set_clk(priv->cru, rate);
 533                 break;
 534         default:
 535                 return -ENOENT;
 536         }
 537
 538         return new_rate;
 539 }
 540
 541 static struct clk_ops rk3128_clk_ops = {
 542         .get_rate       = rk3128_clk_get_rate,
 543         .set_rate       = rk3128_clk_set_rate,
 544 };
 545
 546 static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
 547 {
 548         struct rk3128_clk_priv *priv = dev_get_priv(dev);
 549
 550         priv->cru = dev_read_addr_ptr(dev);
 551
 552         return 0;
 553 }
 554
 555 static int rk3128_clk_probe(struct udevice *dev)
 556 {
 557         struct rk3128_clk_priv *priv = dev_get_priv(dev);
 558
 559         rkclk_init(priv->cru);
 560
 561         return 0;
 562 }
 563
 564 static int rk3128_clk_bind(struct udevice *dev)
 565 {
 566         int ret;
 567         struct udevice *sys_child;
 568         struct sysreset_reg *priv;
 569
 570         /* The reset driver does not have a device node, so bind it here */
 571         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 572                                  &sys_child);
 573         if (ret) {
 574                 debug("Warning: No sysreset driver: ret=%d\n", ret);
 575         } else {
 576                 priv = malloc(sizeof(struct sysreset_reg));
 577                 priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
 578                                                     cru_glb_srst_fst_value);
 579                 priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
 580                                                     cru_glb_srst_snd_value);
 581                 sys_child->priv = priv;
 582         }
 583
 584         return 0;
 585 }
 586
 587 static const struct udevice_id rk3128_clk_ids[] = {
 588         { .compatible = "rockchip,rk3128-cru" },
 589         { .compatible = "rockchip,rk3126-cru" },
 590         { }
 591 };
 592
 593 U_BOOT_DRIVER(rockchip_rk3128_cru) = {
 594         .name           = "clk_rk3128",
 595         .id             = UCLASS_CLK,
 596         .of_match       = rk3128_clk_ids,
 597         .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
 598         .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
 599         .ops            = &rk3128_clk_ops,
 600         .bind           = rk3128_clk_bind,
 601         .probe          = rk3128_clk_probe,
 602 };