drivers/clk/owl/clk_owl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Common clock driver for Actions Semi SoCs.
   4  *
   5  * Copyright (C) 2015 Actions Semi Co., Ltd.
   6  * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include "clk_owl.h"
  12 #include <asm/io.h>
  13 #if defined(CONFIG_MACH_S900)
  14 #include <asm/arch-owl/regs_s900.h>
  15 #include <dt-bindings/clock/actions,s900-cmu.h>
  16 #elif defined(CONFIG_MACH_S700)
  17 #include <asm/arch-owl/regs_s700.h>
  18 #include <dt-bindings/clock/actions,s700-cmu.h>
  19 #endif
  20 #include <linux/delay.h>
  21
  22 void owl_clk_init(struct owl_clk_priv *priv)
  23 {
  24         u32 bus_clk = 0, core_pll, dev_pll;
  25
  26 #if defined(CONFIG_MACH_S900)
  27         /* Enable ASSIST_PLL */
  28         setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
  29         udelay(PLL_STABILITY_WAIT_US);
  30 #endif
  31
  32         /* Source HOSC to DEV_CLK */
  33         clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
  34
  35         /* Configure BUS_CLK */
  36         bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
  37                         CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  38                         CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  39         writel(bus_clk, priv->base + CMU_BUSCLK);
  40
  41         udelay(PLL_STABILITY_WAIT_US);
  42
  43         /* Configure CORE_PLL */
  44         core_pll = readl(priv->base + CMU_COREPLL);
  45         core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
  46         writel(core_pll, priv->base + CMU_COREPLL);
  47
  48         udelay(PLL_STABILITY_WAIT_US);
  49
  50         /* Configure DEV_PLL */
  51         dev_pll = readl(priv->base + CMU_DEVPLL);
  52         dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
  53         writel(dev_pll, priv->base + CMU_DEVPLL);
  54
  55         udelay(PLL_STABILITY_WAIT_US);
  56
  57         /* Source CORE_PLL for CORE_CLK */
  58         clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
  59                         CMU_CORECLK_CPLL);
  60
  61         /* Source DEV_PLL for DEV_CLK */
  62         setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
  63
  64         udelay(PLL_STABILITY_WAIT_US);
  65 }
  66
  67 int owl_clk_enable(struct clk *clk)
  68 {
  69         struct owl_clk_priv *priv = dev_get_priv(clk->dev);
  70         enum owl_soc model = dev_get_driver_data(clk->dev);
  71
  72         switch (clk->id) {
  73         case CLK_UART5:
  74                 if (model != S900)
  75                         return -EINVAL;
  76                 /* Source HOSC for UART5 interface */
  77                 clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
  78                 /* Enable UART5 interface clock */
  79                 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  80                 break;
  81         case CLK_UART3:
  82                 if (model != S700)
  83                         return -EINVAL;
  84                 /* Source HOSC for UART3 interface */
  85                 clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
  86                 /* Enable UART3 interface clock */
  87                 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  88                 break;
  89         default:
  90                 return -EINVAL;
  91         }
  92
  93         return 0;
  94 }
  95
  96 int owl_clk_disable(struct clk *clk)
  97 {
  98         struct owl_clk_priv *priv = dev_get_priv(clk->dev);
  99         enum owl_soc model = dev_get_driver_data(clk->dev);
 100
 101         switch (clk->id) {
 102         case CLK_UART5:
 103                 if (model != S900)
 104                         return -EINVAL;
 105                 /* Disable UART5 interface clock */
 106                 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
 107                 break;
 108         case CLK_UART3:
 109                 if (model != S700)
 110                         return -EINVAL;
 111                 /* Disable UART3 interface clock */
 112                 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
 113                 break;
 114         default:
 115                 return -EINVAL;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static int owl_clk_probe(struct udevice *dev)
 122 {
 123         struct owl_clk_priv *priv = dev_get_priv(dev);
 124
 125         priv->base = dev_read_addr(dev);
 126         if (priv->base == FDT_ADDR_T_NONE)
 127                 return -EINVAL;
 128
 129         /* setup necessary clocks */
 130         owl_clk_init(priv);
 131
 132         return 0;
 133 }
 134
 135 static const struct clk_ops owl_clk_ops = {
 136         .enable = owl_clk_enable,
 137         .disable = owl_clk_disable,
 138 };
 139
 140 static const struct udevice_id owl_clk_ids[] = {
 141 #if defined(CONFIG_MACH_S900)
 142         { .compatible = "actions,s900-cmu", .data = S900 },
 143 #elif defined(CONFIG_MACH_S700)
 144         { .compatible = "actions,s700-cmu", .data = S700 },
 145 #endif
 146         { }
 147 };
 148
 149 U_BOOT_DRIVER(clk_owl) = {
 150         .name           = "clk_owl",
 151         .id             = UCLASS_CLK,
 152         .of_match       = owl_clk_ids,
 153         .ops            = &owl_clk_ops,
 154         .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
 155         .probe          = owl_clk_probe,
 156 };