drivers/clk/mtmips/clk-mt7628.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
   4  *
   5  * Author: Weijie Gao <weijie.gao@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <dt-bindings/clock/mt7628-clk.h>
  12 #include <linux/bitops.h>
  13 #include <linux/io.h>
  14
  15 /* SYSCFG0 */
  16 #define XTAL_40M_SEL                    BIT(6)
  17
  18 /* CLKCFG0 */
  19 #define CLKCFG0_REG                     0x0
  20 #define PERI_CLK_FROM_XTAL_SEL          BIT(4)
  21 #define CPU_PLL_FROM_BBP                BIT(1)
  22 #define CPU_PLL_FROM_XTAL               BIT(0)
  23
  24 /* CLKCFG1 */
  25 #define CLKCFG1_REG                     0x4
  26
  27 #define CLK_SRC_CPU                     -1
  28 #define CLK_SRC_CPU_D2                  -2
  29 #define CLK_SRC_SYS                     -3
  30 #define CLK_SRC_XTAL                    -4
  31 #define CLK_SRC_PERI                    -5
  32
  33 struct mt7628_clk_priv {
  34         void __iomem *base;
  35         int cpu_clk;
  36         int sys_clk;
  37         int xtal_clk;
  38 };
  39
  40 static const int mt7628_clks[] = {
  41         [CLK_SYS] = CLK_SRC_SYS,
  42         [CLK_CPU] = CLK_SRC_CPU,
  43         [CLK_XTAL] = CLK_SRC_XTAL,
  44         [CLK_PWM] = CLK_SRC_PERI,
  45         [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
  46         [CLK_UART2] = CLK_SRC_PERI,
  47         [CLK_UART1] = CLK_SRC_PERI,
  48         [CLK_UART0] = CLK_SRC_PERI,
  49         [CLK_SPI] = CLK_SRC_SYS,
  50         [CLK_I2C] = CLK_SRC_PERI,
  51 };
  52
  53 static ulong mt7628_clk_get_rate(struct clk *clk)
  54 {
  55         struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
  56         u32 val;
  57
  58         if (clk->id >= ARRAY_SIZE(mt7628_clks))
  59                 return 0;
  60
  61         switch (mt7628_clks[clk->id]) {
  62         case CLK_SRC_CPU:
  63                 return priv->cpu_clk;
  64         case CLK_SRC_CPU_D2:
  65                 return priv->cpu_clk / 2;
  66         case CLK_SRC_SYS:
  67                 return priv->sys_clk;
  68         case CLK_SRC_XTAL:
  69                 return priv->xtal_clk;
  70         case CLK_SRC_PERI:
  71                 val = readl(priv->base + CLKCFG0_REG);
  72                 if (val & PERI_CLK_FROM_XTAL_SEL)
  73                         return priv->xtal_clk;
  74                 else
  75                         return 40000000;
  76         default:
  77                 return mt7628_clks[clk->id];
  78         }
  79 }
  80
  81 static int mt7628_clk_enable(struct clk *clk)
  82 {
  83         struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
  84
  85         if (clk->id > 31)
  86                 return -1;
  87
  88         setbits_32(priv->base + CLKCFG1_REG, BIT(clk->id));
  89
  90         return 0;
  91 }
  92
  93 static int mt7628_clk_disable(struct clk *clk)
  94 {
  95         struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
  96
  97         if (clk->id > 31)
  98                 return -1;
  99
 100         clrbits_32(priv->base + CLKCFG1_REG, BIT(clk->id));
 101
 102         return 0;
 103 }
 104
 105 const struct clk_ops mt7628_clk_ops = {
 106         .enable = mt7628_clk_enable,
 107         .disable = mt7628_clk_disable,
 108         .get_rate = mt7628_clk_get_rate,
 109 };
 110
 111 static int mt7628_clk_probe(struct udevice *dev)
 112 {
 113         struct mt7628_clk_priv *priv = dev_get_priv(dev);
 114         void __iomem *syscfg_base;
 115         u32 val;
 116
 117         priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
 118         if (!priv->base)
 119                 return -EINVAL;
 120
 121         syscfg_base = (void __iomem *)dev_remap_addr_index(dev, 1);
 122         if (!syscfg_base)
 123                 return -EINVAL;
 124
 125         val = readl(syscfg_base);
 126         if (val & XTAL_40M_SEL)
 127                 priv->xtal_clk = 40000000;
 128         else
 129                 priv->xtal_clk = 25000000;
 130
 131         val = readl(priv->base + CLKCFG0_REG);
 132         if (val & CPU_PLL_FROM_BBP)
 133                 priv->cpu_clk = 480000000;
 134         else if (val & CPU_PLL_FROM_XTAL)
 135                 priv->cpu_clk = priv->xtal_clk;
 136         else if (priv->xtal_clk == 40000000)
 137                 priv->cpu_clk = 580000000;      /* (xtal_freq / 2) * 29 */
 138         else
 139                 priv->cpu_clk = 575000000;      /* xtal_freq * 23 */
 140
 141         priv->sys_clk = priv->cpu_clk / 3;
 142
 143         return 0;
 144 }
 145
 146 static const struct udevice_id mt7628_clk_ids[] = {
 147         { .compatible = "mediatek,mt7628-clk" },
 148         { }
 149 };
 150
 151 U_BOOT_DRIVER(mt7628_clk) = {
 152         .name = "mt7628-clk",
 153         .id = UCLASS_CLK,
 154         .of_match = mt7628_clk_ids,
 155         .probe = mt7628_clk_probe,
 156         .priv_auto_alloc_size = sizeof(struct mt7628_clk_priv),
 157         .ops = &mt7628_clk_ops,
 158 };