drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
   4  * (C) Copyright 2018 - BayLibre, SAS
   5  * Author: Neil Armstrong <narmstrong@baylibre.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock-gx.h>
  10 #include <asm/io.h>
  11 #include <clk-uclass.h>
  12 #include <div64.h>
  13 #include <dm.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <dt-bindings/clock/gxbb-clkc.h>
  17 #include "clk_meson.h"
  18 #include <linux/err.h>
  19
  20 /* This driver support only basic clock tree operations :
  21  * - Can calculate clock frequency on a limited tree
  22  * - Can Read muxes and basic dividers (0-based only)
  23  * - Can enable/disable gates with limited propagation
  24  * - Can reparent without propagation, only on muxes
  25  * - Can set rates without reparenting
  26  * This driver is adapted to what is actually supported by U-Boot
  27  */
  28
  29 /* Only the clocks ids we don't want to expose, such as the internal muxes
  30  * and dividers of composite clocks, will remain defined here.
  31  */
  32 #define CLKID_MPEG_SEL            10
  33 #define CLKID_MPEG_DIV            11
  34 #define CLKID_SAR_ADC_DIV         99
  35 #define CLKID_MALI_0_DIV          101
  36 #define CLKID_MALI_1_DIV          104
  37 #define CLKID_CTS_AMCLK_SEL       108
  38 #define CLKID_CTS_AMCLK_DIV       109
  39 #define CLKID_CTS_MCLK_I958_SEL   111
  40 #define CLKID_CTS_MCLK_I958_DIV   112
  41 #define CLKID_32K_CLK_SEL         115
  42 #define CLKID_32K_CLK_DIV         116
  43 #define CLKID_SD_EMMC_A_CLK0_SEL  117
  44 #define CLKID_SD_EMMC_A_CLK0_DIV  118
  45 #define CLKID_SD_EMMC_B_CLK0_SEL  120
  46 #define CLKID_SD_EMMC_B_CLK0_DIV  121
  47 #define CLKID_SD_EMMC_C_CLK0_SEL  123
  48 #define CLKID_SD_EMMC_C_CLK0_DIV  124
  49 #define CLKID_VPU_0_DIV           127
  50 #define CLKID_VPU_1_DIV           130
  51 #define CLKID_VAPB_0_DIV          134
  52 #define CLKID_VAPB_1_DIV          137
  53 #define CLKID_HDMI_PLL_PRE_MULT   141
  54 #define CLKID_MPLL0_DIV           142
  55 #define CLKID_MPLL1_DIV           143
  56 #define CLKID_MPLL2_DIV           144
  57 #define CLKID_MPLL_PREDIV         145
  58 #define CLKID_FCLK_DIV2_DIV       146
  59 #define CLKID_FCLK_DIV3_DIV       147
  60 #define CLKID_FCLK_DIV4_DIV       148
  61 #define CLKID_FCLK_DIV5_DIV       149
  62 #define CLKID_FCLK_DIV7_DIV       150
  63 #define CLKID_VDEC_1_SEL          151
  64 #define CLKID_VDEC_1_DIV          152
  65 #define CLKID_VDEC_HEVC_SEL       154
  66 #define CLKID_VDEC_HEVC_DIV       155
  67
  68 #define XTAL_RATE 24000000
  69
  70 struct meson_clk {
  71         struct regmap *map;
  72 };
  73
  74 static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  75 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  76                                 ulong current_rate);
  77 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  78                                   unsigned long parent_id);
  79 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  80 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  81                                       ulong rate, ulong current_rate);
  82 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  83 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  84
  85 static struct meson_gate gates[] = {
  86         /* Everything Else (EE) domain gates */
  87         MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
  88         MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
  89         MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5),
  90         MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6),
  91         MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7),
  92         MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8),
  93         MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  94         MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10),
  95         MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11),
  96         MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12),
  97         MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  98         MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14),
  99         MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15),
 100         MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16),
 101         MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17),
 102         MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18),
 103         MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19),
 104         MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23),
 105         MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24),
 106         MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
 107         MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
 108         MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30),
 109
 110         MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2),
 111         MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
 112         MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4),
 113         MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6),
 114         MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7),
 115         MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8),
 116         MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9),
 117         MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10),
 118         MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11),
 119         MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12),
 120         MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13),
 121         MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14),
 122         MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15),
 123         MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
 124         MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20),
 125         MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21),
 126         MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22),
 127         MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23),
 128         MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24),
 129         MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25),
 130         MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26),
 131         MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28),
 132         MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29),
 133         MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30),
 134         MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31),
 135
 136         MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
 137         MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
 138         MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
 139         MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
 140         MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
 141         MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
 142         MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
 143         MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
 144         MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
 145         MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
 146         MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
 147         MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26),
 148         MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29),
 149
 150         MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1),
 151         MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2),
 152         MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3),
 153         MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4),
 154         MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8),
 155         MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10),
 156         MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14),
 157         MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16),
 158         MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20),
 159         MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21),
 160         MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22),
 161         MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24),
 162         MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25),
 163         MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26),
 164         MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31),
 165
 166         /* Always On (AO) domain gates */
 167         MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0),
 168         MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1),
 169         MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2),
 170         MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3),
 171         MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
 172
 173         /* PLL Gates */
 174         /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
 175         MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
 176         MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
 177         MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
 178         MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),
 179         MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
 180         MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
 181         MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
 182         /* CLKID_CLK81 is critical for the system */
 183
 184         /* Peripheral Gates */
 185         MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8),
 186         MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
 187         MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
 188         MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
 189         MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
 190         MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
 191         MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
 192         MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
 193         MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
 194 };
 195
 196 static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
 197 {
 198         struct meson_clk *priv = dev_get_priv(clk->dev);
 199         struct meson_gate *gate;
 200
 201         debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
 202
 203         /* Propagate through muxes */
 204         switch (id) {
 205         case CLKID_VPU:
 206                 return meson_set_gate_by_id(clk,
 207                                 meson_mux_get_parent(clk, CLKID_VPU), on);
 208         case CLKID_VAPB_SEL:
 209                 return meson_set_gate_by_id(clk,
 210                                 meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
 211         }
 212
 213         if (id >= ARRAY_SIZE(gates))
 214                 return -ENOENT;
 215
 216         gate = &gates[id];
 217
 218         if (gate->reg == 0)
 219                 return 0;
 220
 221         debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
 222
 223         regmap_update_bits(priv->map, gate->reg,
 224                            BIT(gate->bit), on ? BIT(gate->bit) : 0);
 225
 226         /* Propagate to next gate(s) */
 227         switch (id) {
 228         case CLKID_VAPB:
 229                 return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
 230         }
 231
 232         return 0;
 233 }
 234
 235 static int meson_clk_enable(struct clk *clk)
 236 {
 237         return meson_set_gate_by_id(clk, clk->id, true);
 238 }
 239
 240 static int meson_clk_disable(struct clk *clk)
 241 {
 242         return meson_set_gate_by_id(clk, clk->id, false);
 243 }
 244
 245 static struct parm meson_vpu_0_div_parm = {
 246         HHI_VPU_CLK_CNTL, 0, 7,
 247 };
 248
 249 int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
 250
 251 static struct parm meson_vpu_1_div_parm = {
 252         HHI_VPU_CLK_CNTL, 16, 7,
 253 };
 254
 255 int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
 256
 257 static struct parm meson_vapb_0_div_parm = {
 258         HHI_VAPBCLK_CNTL, 0, 7,
 259 };
 260
 261 int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
 262
 263 static struct parm meson_vapb_1_div_parm = {
 264         HHI_VAPBCLK_CNTL, 16, 7,
 265 };
 266
 267 int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
 268
 269 static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 270 {
 271         struct meson_clk *priv = dev_get_priv(clk->dev);
 272         unsigned int rate, parent_rate;
 273         struct parm *parm;
 274         int parent;
 275         uint reg;
 276
 277         switch (id) {
 278         case CLKID_VPU_0_DIV:
 279                 parm = &meson_vpu_0_div_parm;
 280                 parent = meson_vpu_0_div_parent;
 281                 break;
 282         case CLKID_VPU_1_DIV:
 283                 parm = &meson_vpu_1_div_parm;
 284                 parent = meson_vpu_1_div_parent;
 285                 break;
 286         case CLKID_VAPB_0_DIV:
 287                 parm = &meson_vapb_0_div_parm;
 288                 parent = meson_vapb_0_div_parent;
 289                 break;
 290         case CLKID_VAPB_1_DIV:
 291                 parm = &meson_vapb_1_div_parm;
 292                 parent = meson_vapb_1_div_parent;
 293                 break;
 294         default:
 295                 return -ENOENT;
 296         }
 297
 298         regmap_read(priv->map, parm->reg_off, &reg);
 299         reg = PARM_GET(parm->width, parm->shift, reg);
 300
 301         debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
 302
 303         parent_rate = meson_clk_get_rate_by_id(clk, parent);
 304         if (IS_ERR_VALUE(parent_rate))
 305                 return parent_rate;
 306
 307         debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
 308
 309         rate = parent_rate / (reg + 1);
 310
 311         debug("%s: rate of %ld is %d\n", __func__, id, rate);
 312
 313         return rate;
 314 }
 315
 316 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
 317                                 ulong current_rate)
 318 {
 319         struct meson_clk *priv = dev_get_priv(clk->dev);
 320         unsigned int new_div = -EINVAL;
 321         unsigned long parent_rate;
 322         struct parm *parm;
 323         int parent;
 324         int ret;
 325
 326         if (current_rate == rate)
 327                 return 0;
 328
 329         debug("%s: setting rate of %ld from %ld to %ld\n",
 330               __func__, id, current_rate, rate);
 331
 332         switch (id) {
 333         case CLKID_VPU_0_DIV:
 334                 parm = &meson_vpu_0_div_parm;
 335                 parent = meson_vpu_0_div_parent;
 336                 break;
 337         case CLKID_VPU_1_DIV:
 338                 parm = &meson_vpu_1_div_parm;
 339                 parent = meson_vpu_1_div_parent;
 340                 break;
 341         case CLKID_VAPB_0_DIV:
 342                 parm = &meson_vapb_0_div_parm;
 343                 parent = meson_vapb_0_div_parent;
 344                 break;
 345         case CLKID_VAPB_1_DIV:
 346                 parm = &meson_vapb_1_div_parm;
 347                 parent = meson_vapb_1_div_parent;
 348                 break;
 349         default:
 350                 return -ENOENT;
 351         }
 352
 353         parent_rate = meson_clk_get_rate_by_id(clk, parent);
 354         if (IS_ERR_VALUE(parent_rate))
 355                 return parent_rate;
 356
 357         debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
 358
 359         /* If can't divide, set parent instead */
 360         if (!parent_rate || rate > parent_rate)
 361                 return meson_clk_set_rate_by_id(clk, parent, rate,
 362                                                 current_rate);
 363
 364         new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
 365
 366         debug("%s: new div of %ld is %d\n", __func__, id, new_div);
 367
 368         /* If overflow, try to set parent rate and retry */
 369         if (!new_div || new_div > (1 << parm->width)) {
 370                 ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
 371                 if (IS_ERR_VALUE(ret))
 372                         return ret;
 373
 374                 parent_rate = meson_clk_get_rate_by_id(clk, parent);
 375                 if (IS_ERR_VALUE(parent_rate))
 376                         return parent_rate;
 377
 378                 new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
 379
 380                 debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
 381
 382                 if (!new_div || new_div > (1 << parm->width))
 383                         return -EINVAL;
 384         }
 385
 386         debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
 387
 388         regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
 389                            (new_div - 1) << parm->shift);
 390
 391         debug("%s: new rate of %ld is %ld\n",
 392               __func__, id, meson_div_get_rate(clk, id));
 393
 394         return 0;
 395 }
 396
 397 static struct parm meson_vpu_mux_parm = {
 398         HHI_VPU_CLK_CNTL, 31, 1,
 399 };
 400
 401 int meson_vpu_mux_parents[] = {
 402         CLKID_VPU_0,
 403         CLKID_VPU_1,
 404 };
 405
 406 static struct parm meson_vpu_0_mux_parm = {
 407         HHI_VPU_CLK_CNTL, 9, 2,
 408 };
 409
 410 static struct parm meson_vpu_1_mux_parm = {
 411         HHI_VPU_CLK_CNTL, 25, 2,
 412 };
 413
 414 static int meson_vpu_0_1_mux_parents[] = {
 415         CLKID_FCLK_DIV4,
 416         CLKID_FCLK_DIV3,
 417         CLKID_FCLK_DIV5,
 418         CLKID_FCLK_DIV7,
 419 };
 420
 421 static struct parm meson_vapb_sel_mux_parm = {
 422         HHI_VAPBCLK_CNTL, 31, 1,
 423 };
 424
 425 int meson_vapb_sel_mux_parents[] = {
 426         CLKID_VAPB_0,
 427         CLKID_VAPB_1,
 428 };
 429
 430 static struct parm meson_vapb_0_mux_parm = {
 431         HHI_VAPBCLK_CNTL, 9, 2,
 432 };
 433
 434 static struct parm meson_vapb_1_mux_parm = {
 435         HHI_VAPBCLK_CNTL, 25, 2,
 436 };
 437
 438 static int meson_vapb_0_1_mux_parents[] = {
 439         CLKID_FCLK_DIV4,
 440         CLKID_FCLK_DIV3,
 441         CLKID_FCLK_DIV5,
 442         CLKID_FCLK_DIV7,
 443 };
 444
 445 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
 446 {
 447         struct meson_clk *priv = dev_get_priv(clk->dev);
 448         struct parm *parm;
 449         int *parents;
 450         uint reg;
 451
 452         switch (id) {
 453         case CLKID_VPU:
 454                 parm = &meson_vpu_mux_parm;
 455                 parents = meson_vpu_mux_parents;
 456                 break;
 457         case CLKID_VPU_0_SEL:
 458                 parm = &meson_vpu_0_mux_parm;
 459                 parents = meson_vpu_0_1_mux_parents;
 460                 break;
 461         case CLKID_VPU_1_SEL:
 462                 parm = &meson_vpu_1_mux_parm;
 463                 parents = meson_vpu_0_1_mux_parents;
 464                 break;
 465         case CLKID_VAPB_SEL:
 466                 parm = &meson_vapb_sel_mux_parm;
 467                 parents = meson_vapb_sel_mux_parents;
 468                 break;
 469         case CLKID_VAPB_0_SEL:
 470                 parm = &meson_vapb_0_mux_parm;
 471                 parents = meson_vapb_0_1_mux_parents;
 472                 break;
 473         case CLKID_VAPB_1_SEL:
 474                 parm = &meson_vapb_1_mux_parm;
 475                 parents = meson_vapb_0_1_mux_parents;
 476                 break;
 477         default:
 478                 return -ENOENT;
 479         }
 480
 481         regmap_read(priv->map, parm->reg_off, &reg);
 482         reg = PARM_GET(parm->width, parm->shift, reg);
 483
 484         debug("%s: parent of %ld is %d (%d)\n",
 485               __func__, id, parents[reg], reg);
 486
 487         return parents[reg];
 488 }
 489
 490 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
 491                                   unsigned long parent_id)
 492 {
 493         unsigned long cur_parent = meson_mux_get_parent(clk, id);
 494         struct meson_clk *priv = dev_get_priv(clk->dev);
 495         unsigned int new_index = -EINVAL;
 496         struct parm *parm;
 497         int *parents;
 498         int i;
 499
 500         if (IS_ERR_VALUE(cur_parent))
 501                 return cur_parent;
 502
 503         debug("%s: setting parent of %ld from %ld to %ld\n",
 504               __func__, id, cur_parent, parent_id);
 505
 506         if (cur_parent == parent_id)
 507                 return 0;
 508
 509         switch (id) {
 510         case CLKID_VPU:
 511                 parm = &meson_vpu_mux_parm;
 512                 parents = meson_vpu_mux_parents;
 513                 break;
 514         case CLKID_VPU_0_SEL:
 515                 parm = &meson_vpu_0_mux_parm;
 516                 parents = meson_vpu_0_1_mux_parents;
 517                 break;
 518         case CLKID_VPU_1_SEL:
 519                 parm = &meson_vpu_1_mux_parm;
 520                 parents = meson_vpu_0_1_mux_parents;
 521                 break;
 522         case CLKID_VAPB_SEL:
 523                 parm = &meson_vapb_sel_mux_parm;
 524                 parents = meson_vapb_sel_mux_parents;
 525                 break;
 526         case CLKID_VAPB_0_SEL:
 527                 parm = &meson_vapb_0_mux_parm;
 528                 parents = meson_vapb_0_1_mux_parents;
 529                 break;
 530         case CLKID_VAPB_1_SEL:
 531                 parm = &meson_vapb_1_mux_parm;
 532                 parents = meson_vapb_0_1_mux_parents;
 533                 break;
 534         default:
 535                 /* Not a mux */
 536                 return -ENOENT;
 537         }
 538
 539         for (i = 0 ; i < (1 << parm->width) ; ++i) {
 540                 if (parents[i] == parent_id)
 541                         new_index = i;
 542         }
 543
 544         if (IS_ERR_VALUE(new_index))
 545                 return new_index;
 546
 547         debug("%s: new index of %ld is %d\n", __func__, id, new_index);
 548
 549         regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
 550                            new_index << parm->shift);
 551
 552         debug("%s: new parent of %ld is %ld\n",
 553               __func__, id, meson_mux_get_parent(clk, id));
 554
 555         return 0;
 556 }
 557
 558 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
 559 {
 560         int parent = meson_mux_get_parent(clk, id);
 561
 562         if (IS_ERR_VALUE(parent))
 563                 return parent;
 564
 565         return meson_clk_get_rate_by_id(clk, parent);
 566 }
 567
 568 static unsigned long meson_clk81_get_rate(struct clk *clk)
 569 {
 570         struct meson_clk *priv = dev_get_priv(clk->dev);
 571         unsigned long parent_rate;
 572         uint reg;
 573         int parents[] = {
 574                 -1,
 575                 -1,
 576                 CLKID_FCLK_DIV7,
 577                 CLKID_MPLL1,
 578                 CLKID_MPLL2,
 579                 CLKID_FCLK_DIV4,
 580                 CLKID_FCLK_DIV3,
 581                 CLKID_FCLK_DIV5
 582         };
 583
 584         /* mux */
 585         regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
 586         reg = (reg >> 12) & 7;
 587
 588         switch (reg) {
 589         case 0:
 590                 parent_rate = XTAL_RATE;
 591                 break;
 592         case 1:
 593                 return -ENOENT;
 594         default:
 595                 parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
 596         }
 597
 598         /* divider */
 599         regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
 600         reg = reg & ((1 << 7) - 1);
 601
 602         /* clk81 divider is zero based */
 603         return parent_rate / (reg + 1);
 604 }
 605
 606 static long mpll_rate_from_params(unsigned long parent_rate,
 607                                   unsigned long sdm,
 608                                   unsigned long n2)
 609 {
 610         unsigned long divisor = (SDM_DEN * n2) + sdm;
 611
 612         if (n2 < N2_MIN)
 613                 return -EINVAL;
 614
 615         return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
 616 }
 617
 618 static struct parm meson_mpll0_parm[3] = {
 619         {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
 620         {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
 621 };
 622
 623 static struct parm meson_mpll1_parm[3] = {
 624         {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
 625         {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
 626 };
 627
 628 static struct parm meson_mpll2_parm[3] = {
 629         {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
 630         {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
 631 };
 632
 633 /*
 634  * MultiPhase Locked Loops are outputs from a PLL with additional frequency
 635  * scaling capabilities. MPLL rates are calculated as:
 636  *
 637  * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
 638  */
 639 static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
 640 {
 641         struct meson_clk *priv = dev_get_priv(clk->dev);
 642         struct parm *psdm, *pn2;
 643         unsigned long sdm, n2;
 644         unsigned long parent_rate;
 645         uint reg;
 646
 647         switch (id) {
 648         case CLKID_MPLL0:
 649                 psdm = &meson_mpll0_parm[0];
 650                 pn2 = &meson_mpll0_parm[1];
 651                 break;
 652         case CLKID_MPLL1:
 653                 psdm = &meson_mpll1_parm[0];
 654                 pn2 = &meson_mpll1_parm[1];
 655                 break;
 656         case CLKID_MPLL2:
 657                 psdm = &meson_mpll2_parm[0];
 658                 pn2 = &meson_mpll2_parm[1];
 659                 break;
 660         default:
 661                 return -ENOENT;
 662         }
 663
 664         parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
 665         if (IS_ERR_VALUE(parent_rate))
 666                 return parent_rate;
 667
 668         regmap_read(priv->map, psdm->reg_off, &reg);
 669         sdm = PARM_GET(psdm->width, psdm->shift, reg);
 670
 671         regmap_read(priv->map, pn2->reg_off, &reg);
 672         n2 = PARM_GET(pn2->width, pn2->shift, reg);
 673
 674         return mpll_rate_from_params(parent_rate, sdm, n2);
 675 }
 676
 677 static struct parm meson_fixed_pll_parm[3] = {
 678         {HHI_MPLL_CNTL, 0, 9}, /* pm */
 679         {HHI_MPLL_CNTL, 9, 5}, /* pn */
 680         {HHI_MPLL_CNTL, 16, 2}, /* pod */
 681 };
 682
 683 static struct parm meson_sys_pll_parm[3] = {
 684         {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
 685         {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
 686         {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
 687 };
 688
 689 static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
 690 {
 691         struct meson_clk *priv = dev_get_priv(clk->dev);
 692         struct parm *pm, *pn, *pod;
 693         unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
 694         u16 n, m, od;
 695         uint reg;
 696
 697         switch (id) {
 698         case CLKID_FIXED_PLL:
 699                 pm = &meson_fixed_pll_parm[0];
 700                 pn = &meson_fixed_pll_parm[1];
 701                 pod = &meson_fixed_pll_parm[2];
 702                 break;
 703         case CLKID_SYS_PLL:
 704                 pm = &meson_sys_pll_parm[0];
 705                 pn = &meson_sys_pll_parm[1];
 706                 pod = &meson_sys_pll_parm[2];
 707                 break;
 708         default:
 709                 return -ENOENT;
 710         }
 711
 712         regmap_read(priv->map, pn->reg_off, &reg);
 713         n = PARM_GET(pn->width, pn->shift, reg);
 714
 715         regmap_read(priv->map, pm->reg_off, &reg);
 716         m = PARM_GET(pm->width, pm->shift, reg);
 717
 718         regmap_read(priv->map, pod->reg_off, &reg);
 719         od = PARM_GET(pod->width, pod->shift, reg);
 720
 721         return ((parent_rate_mhz * m / n) >> od) * 1000000;
 722 }
 723
 724 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 725 {
 726         ulong rate;
 727
 728         switch (id) {
 729         case CLKID_FIXED_PLL:
 730         case CLKID_SYS_PLL:
 731                 rate = meson_pll_get_rate(clk, id);
 732                 break;
 733         case CLKID_FCLK_DIV2:
 734                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
 735                 break;
 736         case CLKID_FCLK_DIV3:
 737                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
 738                 break;
 739         case CLKID_FCLK_DIV4:
 740                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
 741                 break;
 742         case CLKID_FCLK_DIV5:
 743                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
 744                 break;
 745         case CLKID_FCLK_DIV7:
 746                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
 747                 break;
 748         case CLKID_MPLL0:
 749         case CLKID_MPLL1:
 750         case CLKID_MPLL2:
 751                 rate = meson_mpll_get_rate(clk, id);
 752                 break;
 753         case CLKID_CLK81:
 754                 rate = meson_clk81_get_rate(clk);
 755                 break;
 756         case CLKID_VPU_0:
 757                 rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
 758                 break;
 759         case CLKID_VPU_1:
 760                 rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
 761                 break;
 762         case CLKID_VAPB:
 763                 rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
 764                 break;
 765         case CLKID_VAPB_0:
 766                 rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
 767                 break;
 768         case CLKID_VAPB_1:
 769                 rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
 770                 break;
 771         case CLKID_VPU_0_DIV:
 772         case CLKID_VPU_1_DIV:
 773         case CLKID_VAPB_0_DIV:
 774         case CLKID_VAPB_1_DIV:
 775                 rate = meson_div_get_rate(clk, id);
 776                 break;
 777         case CLKID_VPU:
 778         case CLKID_VPU_0_SEL:
 779         case CLKID_VPU_1_SEL:
 780         case CLKID_VAPB_SEL:
 781         case CLKID_VAPB_0_SEL:
 782         case CLKID_VAPB_1_SEL:
 783                 rate = meson_mux_get_rate(clk, id);
 784                 break;
 785         default:
 786                 if (gates[id].reg != 0) {
 787                         /* a clock gate */
 788                         rate = meson_clk81_get_rate(clk);
 789                         break;
 790                 }
 791                 return -ENOENT;
 792         }
 793
 794         debug("clock %lu has rate %lu\n", id, rate);
 795         return rate;
 796 }
 797
 798 static ulong meson_clk_get_rate(struct clk *clk)
 799 {
 800         return meson_clk_get_rate_by_id(clk, clk->id);
 801 }
 802
 803 static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
 804 {
 805         return meson_mux_set_parent(clk, clk->id, parent->id);
 806 }
 807
 808 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
 809                                       ulong rate, ulong current_rate)
 810 {
 811         if (current_rate == rate)
 812                 return 0;
 813
 814         switch (id) {
 815         /* Fixed clocks */
 816         case CLKID_FIXED_PLL:
 817         case CLKID_SYS_PLL:
 818         case CLKID_FCLK_DIV2:
 819         case CLKID_FCLK_DIV3:
 820         case CLKID_FCLK_DIV4:
 821         case CLKID_FCLK_DIV5:
 822         case CLKID_FCLK_DIV7:
 823         case CLKID_MPLL0:
 824         case CLKID_MPLL1:
 825         case CLKID_MPLL2:
 826         case CLKID_CLK81:
 827                 return -EINVAL;
 828         case CLKID_VPU:
 829                 return meson_clk_set_rate_by_id(clk,
 830                                 meson_mux_get_parent(clk, CLKID_VPU), rate,
 831                                                      current_rate);
 832         case CLKID_VAPB:
 833         case CLKID_VAPB_SEL:
 834                 return meson_clk_set_rate_by_id(clk,
 835                                 meson_mux_get_parent(clk, CLKID_VAPB_SEL),
 836                                 rate, current_rate);
 837         case CLKID_VPU_0:
 838                 return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
 839                                           current_rate);
 840         case CLKID_VPU_1:
 841                 return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
 842                                           current_rate);
 843         case CLKID_VAPB_0:
 844                 return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
 845                                           current_rate);
 846         case CLKID_VAPB_1:
 847                 return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
 848                                           current_rate);
 849         case CLKID_VPU_0_DIV:
 850         case CLKID_VPU_1_DIV:
 851         case CLKID_VAPB_0_DIV:
 852         case CLKID_VAPB_1_DIV:
 853                 return meson_div_set_rate(clk, id, rate, current_rate);
 854         default:
 855                 return -ENOENT;
 856         }
 857
 858         return -EINVAL;
 859 }
 860
 861 static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
 862 {
 863         ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
 864         int ret;
 865
 866         if (IS_ERR_VALUE(current_rate))
 867                 return current_rate;
 868
 869         debug("%s: setting rate of %ld from %ld to %ld\n",
 870               __func__, clk->id, current_rate, rate);
 871
 872         ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
 873         if (IS_ERR_VALUE(ret))
 874                 return ret;
 875
 876         debug("clock %lu has new rate %lu\n", clk->id,
 877               meson_clk_get_rate_by_id(clk, clk->id));
 878
 879         return 0;
 880 }
 881
 882 static int meson_clk_probe(struct udevice *dev)
 883 {
 884         struct meson_clk *priv = dev_get_priv(dev);
 885
 886         priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
 887         if (IS_ERR(priv->map))
 888                 return PTR_ERR(priv->map);
 889
 890         debug("meson-clk: probed\n");
 891
 892         return 0;
 893 }
 894
 895 static struct clk_ops meson_clk_ops = {
 896         .disable        = meson_clk_disable,
 897         .enable         = meson_clk_enable,
 898         .get_rate       = meson_clk_get_rate,
 899         .set_parent     = meson_clk_set_parent,
 900         .set_rate       = meson_clk_set_rate,
 901 };
 902
 903 static const struct udevice_id meson_clk_ids[] = {
 904         { .compatible = "amlogic,gxbb-clkc" },
 905         { .compatible = "amlogic,gxl-clkc" },
 906         { }
 907 };
 908
 909 U_BOOT_DRIVER(meson_clk) = {
 910         .name           = "meson_clk",
 911         .id             = UCLASS_CLK,
 912         .of_match       = meson_clk_ids,
 913         .priv_auto_alloc_size = sizeof(struct meson_clk),
 914         .ops            = &meson_clk_ops,
 915         .probe          = meson_clk_probe,
 916 };