drivers/clk/imx/clk-pll14xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2017-2019 NXP.
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <malloc.h>
  11 #include <clk-uclass.h>
  12 #include <dm/device.h>
  13 #include <dm/devres.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/err.h>
  16 #include <linux/iopoll.h>
  17 #include <clk.h>
  18 #include <div64.h>
  19
  20 #include "clk.h"
  21
  22 #define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
  23 #define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
  24
  25 #define GNRL_CTL        0x0
  26 #define DIV_CTL         0x4
  27 #define LOCK_STATUS     BIT(31)
  28 #define LOCK_SEL_MASK   BIT(29)
  29 #define CLKE_MASK       BIT(11)
  30 #define RST_MASK        BIT(9)
  31 #define BYPASS_MASK     BIT(4)
  32 #define MDIV_SHIFT      12
  33 #define MDIV_MASK       GENMASK(21, 12)
  34 #define PDIV_SHIFT      4
  35 #define PDIV_MASK       GENMASK(9, 4)
  36 #define SDIV_SHIFT      0
  37 #define SDIV_MASK       GENMASK(2, 0)
  38 #define KDIV_SHIFT      0
  39 #define KDIV_MASK       GENMASK(15, 0)
  40
  41 #define LOCK_TIMEOUT_US         10000
  42
  43 struct clk_pll14xx {
  44         struct clk                      clk;
  45         void __iomem                    *base;
  46         enum imx_pll14xx_type           type;
  47         const struct imx_pll14xx_rate_table *rate_table;
  48         int rate_count;
  49 };
  50
  51 #define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
  52
  53 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
  54                 struct clk_pll14xx *pll, unsigned long rate)
  55 {
  56         const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
  57         int i;
  58
  59         for (i = 0; i < pll->rate_count; i++)
  60                 if (rate == rate_table[i].rate)
  61                         return &rate_table[i];
  62
  63         return NULL;
  64 }
  65
  66 static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
  67 {
  68         struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  69         u64 fvco = clk_get_parent_rate(clk);
  70         u32 mdiv, pdiv, sdiv, pll_div;
  71
  72         pll_div = readl(pll->base + 4);
  73         mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
  74         pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
  75         sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
  76
  77         fvco *= mdiv;
  78         do_div(fvco, pdiv << sdiv);
  79
  80         return fvco;
  81 }
  82
  83 static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
  84 {
  85         struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
  86         u64 fvco = clk_get_parent_rate(clk);
  87         u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
  88         short int kdiv;
  89
  90         pll_div_ctl0 = readl(pll->base + 4);
  91         pll_div_ctl1 = readl(pll->base + 8);
  92         mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
  93         pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
  94         sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
  95         kdiv = pll_div_ctl1 & KDIV_MASK;
  96
  97         /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
  98         fvco *= (mdiv * 65536 + kdiv);
  99         pdiv *= 65536;
 100
 101         do_div(fvco, pdiv << sdiv);
 102
 103         return fvco;
 104 }
 105
 106 static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
 107                                           u32 pll_div)
 108 {
 109         u32 old_mdiv, old_pdiv;
 110
 111         old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
 112         old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
 113
 114         return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
 115 }
 116
 117 static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
 118                                            u32 pll_div_ctl0, u32 pll_div_ctl1)
 119 {
 120         u32 old_mdiv, old_pdiv, old_kdiv;
 121
 122         old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
 123         old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
 124         old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
 125
 126         return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
 127                 rate->kdiv != old_kdiv;
 128 }
 129
 130 static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
 131                                           u32 pll_div_ctl0, u32 pll_div_ctl1)
 132 {
 133         u32 old_mdiv, old_pdiv, old_kdiv;
 134
 135         old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
 136         old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
 137         old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
 138
 139         return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
 140                 rate->kdiv != old_kdiv;
 141 }
 142
 143 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
 144 {
 145         u32 val;
 146
 147         return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
 148                         LOCK_TIMEOUT_US);
 149 }
 150
 151 static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
 152 {
 153         struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
 154         const struct imx_pll14xx_rate_table *rate;
 155         u32 tmp, div_val;
 156         int ret;
 157
 158         rate = imx_get_pll_settings(pll, drate);
 159         if (!rate) {
 160                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 161                        drate, "xxxx");
 162                 return -EINVAL;
 163         }
 164
 165         tmp = readl(pll->base + 4);
 166
 167         if (!clk_pll1416x_mp_change(rate, tmp)) {
 168                 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
 169                 tmp |= rate->sdiv << SDIV_SHIFT;
 170                 writel(tmp, pll->base + 4);
 171
 172                 return clk_pll1416x_recalc_rate(clk);
 173         }
 174
 175         /* Bypass clock and set lock to pll output lock */
 176         tmp = readl(pll->base);
 177         tmp |= LOCK_SEL_MASK;
 178         writel(tmp, pll->base);
 179
 180         /* Enable RST */
 181         tmp &= ~RST_MASK;
 182         writel(tmp, pll->base);
 183
 184         /* Enable BYPASS */
 185         tmp |= BYPASS_MASK;
 186         writel(tmp, pll->base);
 187
 188
 189         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 190                 (rate->sdiv << SDIV_SHIFT);
 191         writel(div_val, pll->base + 0x4);
 192
 193         /*
 194          * According to SPEC, t3 - t2 need to be greater than
 195          * 1us and 1/FREF, respectively.
 196          * FREF is FIN / Prediv, the prediv is [1, 63], so choose
 197          * 3us.
 198          */
 199         udelay(3);
 200
 201         /* Disable RST */
 202         tmp |= RST_MASK;
 203         writel(tmp, pll->base);
 204
 205         /* Wait Lock */
 206         ret = clk_pll14xx_wait_lock(pll);
 207         if (ret)
 208                 return ret;
 209
 210         /* Bypass */
 211         tmp &= ~BYPASS_MASK;
 212         writel(tmp, pll->base);
 213
 214         return clk_pll1416x_recalc_rate(clk);
 215 }
 216
 217 static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
 218 {
 219         struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
 220         const struct imx_pll14xx_rate_table *rate;
 221         u32 tmp, div_val;
 222         int ret;
 223
 224         rate = imx_get_pll_settings(pll, drate);
 225         if (!rate) {
 226                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 227                        drate, "===");
 228                 return -EINVAL;
 229         }
 230
 231         tmp = readl(pll->base + 4);
 232         div_val = readl(pll->base + 8);
 233
 234         if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
 235                 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
 236                 tmp |= rate->sdiv << SDIV_SHIFT;
 237                 writel(tmp, pll->base + 4);
 238
 239                 return clk_pll1443x_recalc_rate(clk);
 240         }
 241
 242         tmp = readl(pll->base);
 243
 244         /* Enable RST */
 245         tmp &= ~RST_MASK;
 246         writel(tmp, pll->base);
 247
 248         /* Enable BYPASS */
 249         tmp |= BYPASS_MASK;
 250         writel(tmp, pll->base);
 251
 252         div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
 253                 (rate->sdiv << SDIV_SHIFT);
 254         writel(div_val, pll->base + 0x4);
 255         writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
 256
 257         /*
 258          * According to SPEC, t3 - t2 need to be greater than
 259          * 1us and 1/FREF, respectively.
 260          * FREF is FIN / Prediv, the prediv is [1, 63], so choose
 261          * 3us.
 262          */
 263         udelay(3);
 264
 265         /* Disable RST */
 266         tmp |= RST_MASK;
 267         writel(tmp, pll->base);
 268
 269         /* Wait Lock*/
 270         ret = clk_pll14xx_wait_lock(pll);
 271         if (ret)
 272                 return ret;
 273
 274         /* Bypass */
 275         tmp &= ~BYPASS_MASK;
 276         writel(tmp, pll->base);
 277
 278         return clk_pll1443x_recalc_rate(clk);
 279 }
 280
 281 static int clk_pll14xx_prepare(struct clk *clk)
 282 {
 283         struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
 284         u32 val;
 285
 286         /*
 287          * RESETB = 1 from 0, PLL starts its normal
 288          * operation after lock time
 289          */
 290         val = readl(pll->base + GNRL_CTL);
 291         val |= RST_MASK;
 292         writel(val, pll->base + GNRL_CTL);
 293
 294         return clk_pll14xx_wait_lock(pll);
 295 }
 296
 297 static int clk_pll14xx_unprepare(struct clk *clk)
 298 {
 299         struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
 300         u32 val;
 301
 302         /*
 303          * Set RST to 0, power down mode is enabled and
 304          * every digital block is reset
 305          */
 306         val = readl(pll->base + GNRL_CTL);
 307         val &= ~RST_MASK;
 308         writel(val, pll->base + GNRL_CTL);
 309
 310         return 0;
 311 }
 312
 313 static const struct clk_ops clk_pll1416x_ops = {
 314         .enable         = clk_pll14xx_prepare,
 315         .disable        = clk_pll14xx_unprepare,
 316         .set_rate       = clk_pll1416x_set_rate,
 317         .get_rate       = clk_pll1416x_recalc_rate,
 318 };
 319
 320 static const struct clk_ops clk_pll1443x_ops = {
 321         .enable         = clk_pll14xx_prepare,
 322         .disable        = clk_pll14xx_unprepare,
 323         .set_rate       = clk_pll1443x_set_rate,
 324         .get_rate       = clk_pll1443x_recalc_rate,
 325 };
 326
 327 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
 328                             void __iomem *base,
 329                             const struct imx_pll14xx_clk *pll_clk)
 330 {
 331         struct clk_pll14xx *pll;
 332         struct clk *clk;
 333         char *type_name;
 334         int ret;
 335
 336         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 337         if (!pll)
 338                 return ERR_PTR(-ENOMEM);
 339
 340         switch (pll_clk->type) {
 341         case PLL_1416X:
 342                 type_name = UBOOT_DM_CLK_IMX_PLL1416X;
 343                 break;
 344         case PLL_1443X:
 345                 type_name = UBOOT_DM_CLK_IMX_PLL1443X;
 346                 break;
 347         default:
 348                 pr_err("%s: Unknown pll type for pll clk %s\n",
 349                        __func__, name);
 350                 return ERR_PTR(-EINVAL);
 351         };
 352
 353         pll->base = base;
 354         pll->type = pll_clk->type;
 355         pll->rate_table = pll_clk->rate_table;
 356         pll->rate_count = pll_clk->rate_count;
 357
 358         clk = &pll->clk;
 359
 360         ret = clk_register(clk, type_name, name, parent_name);
 361         if (ret) {
 362                 pr_err("%s: failed to register pll %s %d\n",
 363                        __func__, name, ret);
 364                 kfree(pll);
 365                 return ERR_PTR(ret);
 366         }
 367
 368         return clk;
 369 }
 370
 371 U_BOOT_DRIVER(clk_pll1443x) = {
 372         .name   = UBOOT_DM_CLK_IMX_PLL1443X,
 373         .id     = UCLASS_CLK,
 374         .ops    = &clk_pll1443x_ops,
 375         .flags = DM_FLAG_PRE_RELOC,
 376 };
 377
 378 U_BOOT_DRIVER(clk_pll1416x) = {
 379         .name   = UBOOT_DM_CLK_IMX_PLL1416X,
 380         .id     = UCLASS_CLK,
 381         .ops    = &clk_pll1416x_ops,
 382         .flags = DM_FLAG_PRE_RELOC,
 383 };