drivers/clk/imx/clk-imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  * Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <dt-bindings/clock/imx8mm-clock.h>
  14
  15 #include "clk.h"
  16
  17 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
  18         {                                               \
  19                 .rate   =       (_rate),                \
  20                 .mdiv   =       (_m),                   \
  21                 .pdiv   =       (_p),                   \
  22                 .sdiv   =       (_s),                   \
  23         }
  24
  25 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
  26         {                                               \
  27                 .rate   =       (_rate),                \
  28                 .mdiv   =       (_m),                   \
  29                 .pdiv   =       (_p),                   \
  30                 .sdiv   =       (_s),                   \
  31                 .kdiv   =       (_k),                   \
  32         }
  33
  34 static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
  35         PLL_1416X_RATE(1800000000U, 225, 3, 0),
  36         PLL_1416X_RATE(1600000000U, 200, 3, 0),
  37         PLL_1416X_RATE(1200000000U, 300, 3, 1),
  38         PLL_1416X_RATE(1000000000U, 250, 3, 1),
  39         PLL_1416X_RATE(800000000U,  200, 3, 1),
  40         PLL_1416X_RATE(750000000U,  250, 2, 2),
  41         PLL_1416X_RATE(700000000U,  350, 3, 2),
  42         PLL_1416X_RATE(600000000U,  300, 3, 2),
  43 };
  44
  45 static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
  46         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  47 };
  48
  49 static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
  50                 .type = PLL_1443X,
  51                 .rate_table = imx8mm_drampll_tbl,
  52                 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
  53 };
  54
  55 static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
  56                 .type = PLL_1416X,
  57                 .rate_table = imx8mm_pll1416x_tbl,
  58                 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
  59 };
  60
  61 static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
  62                 .type = PLL_1416X,
  63                 .rate_table = imx8mm_pll1416x_tbl,
  64                 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
  65 };
  66
  67 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  68 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  69 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  70 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  71 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  72 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  73
  74 static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  75                                         "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  76
  77 static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  78                                         "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  79
  80 static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  81                                              "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  82
  83 #ifndef CONFIG_SPL_BUILD
  84 static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
  85                                              "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
  86
  87 static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
  88                                                "clk_ext3", "clk_ext4", "video_pll1_out", };
  89
  90 static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
  91                                              "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
  92 #endif
  93
  94 static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  95                                                "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  96
  97 static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  98                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  99
 100 static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
 101                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
 102
 103 static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 104                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 105
 106 static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 107                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 108
 109 static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 110                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 111
 112 static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 113                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 114
 115 static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
 116                                          "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
 117
 118 static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
 119                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
 120
 121 static ulong imx8mm_clk_get_rate(struct clk *clk)
 122 {
 123         struct clk *c;
 124         int ret;
 125
 126         debug("%s(#%lu)\n", __func__, clk->id);
 127
 128         ret = clk_get_by_id(clk->id, &c);
 129         if (ret)
 130                 return ret;
 131
 132         return clk_get_rate(c);
 133 }
 134
 135 static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
 136 {
 137         struct clk *c;
 138         int ret;
 139
 140         debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
 141
 142         ret = clk_get_by_id(clk->id, &c);
 143         if (ret)
 144                 return ret;
 145
 146         return clk_set_rate(c, rate);
 147 }
 148
 149 static int __imx8mm_clk_enable(struct clk *clk, bool enable)
 150 {
 151         struct clk *c;
 152         int ret;
 153
 154         debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
 155
 156         ret = clk_get_by_id(clk->id, &c);
 157         if (ret)
 158                 return ret;
 159
 160         if (enable)
 161                 ret = clk_enable(c);
 162         else
 163                 ret = clk_disable(c);
 164
 165         return ret;
 166 }
 167
 168 static int imx8mm_clk_disable(struct clk *clk)
 169 {
 170         return __imx8mm_clk_enable(clk, 0);
 171 }
 172
 173 static int imx8mm_clk_enable(struct clk *clk)
 174 {
 175         return __imx8mm_clk_enable(clk, 1);
 176 }
 177
 178 static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
 179 {
 180         struct clk *c, *cp;
 181         int ret;
 182
 183         debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
 184
 185         ret = clk_get_by_id(clk->id, &c);
 186         if (ret)
 187                 return ret;
 188
 189         ret = clk_get_by_id(parent->id, &cp);
 190         if (ret)
 191                 return ret;
 192
 193         return clk_set_parent(c, cp);
 194 }
 195
 196 static struct clk_ops imx8mm_clk_ops = {
 197         .set_rate = imx8mm_clk_set_rate,
 198         .get_rate = imx8mm_clk_get_rate,
 199         .enable = imx8mm_clk_enable,
 200         .disable = imx8mm_clk_disable,
 201         .set_parent = imx8mm_clk_set_parent,
 202 };
 203
 204 static int imx8mm_clk_probe(struct udevice *dev)
 205 {
 206         void __iomem *base;
 207
 208         base = (void *)ANATOP_BASE_ADDR;
 209
 210         clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
 211                imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
 212                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 213         clk_dm(IMX8MM_ARM_PLL_REF_SEL,
 214                imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
 215                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 216         clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
 217                imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
 218                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 219         clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
 220                imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
 221                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 222         clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
 223                imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
 224                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 225
 226         clk_dm(IMX8MM_DRAM_PLL,
 227                imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
 228                                base + 0x50, &imx8mm_dram_pll));
 229         clk_dm(IMX8MM_ARM_PLL,
 230                imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
 231                                base + 0x84, &imx8mm_arm_pll));
 232         clk_dm(IMX8MM_SYS_PLL1,
 233                imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
 234                                base + 0x94, &imx8mm_sys_pll));
 235         clk_dm(IMX8MM_SYS_PLL2,
 236                imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
 237                                base + 0x104, &imx8mm_sys_pll));
 238         clk_dm(IMX8MM_SYS_PLL3,
 239                imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
 240                                base + 0x114, &imx8mm_sys_pll));
 241
 242         /* PLL bypass out */
 243         clk_dm(IMX8MM_DRAM_PLL_BYPASS,
 244                imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
 245                                  dram_pll_bypass_sels,
 246                                  ARRAY_SIZE(dram_pll_bypass_sels),
 247                                  CLK_SET_RATE_PARENT));
 248         clk_dm(IMX8MM_ARM_PLL_BYPASS,
 249                imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
 250                                  arm_pll_bypass_sels,
 251                                  ARRAY_SIZE(arm_pll_bypass_sels),
 252                                  CLK_SET_RATE_PARENT));
 253         clk_dm(IMX8MM_SYS_PLL1_BYPASS,
 254                imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
 255                                  sys_pll1_bypass_sels,
 256                                  ARRAY_SIZE(sys_pll1_bypass_sels),
 257                                  CLK_SET_RATE_PARENT));
 258         clk_dm(IMX8MM_SYS_PLL2_BYPASS,
 259                imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
 260                                  sys_pll2_bypass_sels,
 261                                  ARRAY_SIZE(sys_pll2_bypass_sels),
 262                                  CLK_SET_RATE_PARENT));
 263         clk_dm(IMX8MM_SYS_PLL3_BYPASS,
 264                imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
 265                                  sys_pll3_bypass_sels,
 266                                  ARRAY_SIZE(sys_pll3_bypass_sels),
 267                                  CLK_SET_RATE_PARENT));
 268
 269         /* PLL out gate */
 270         clk_dm(IMX8MM_DRAM_PLL_OUT,
 271                imx_clk_gate("dram_pll_out", "dram_pll_bypass",
 272                             base + 0x50, 13));
 273         clk_dm(IMX8MM_ARM_PLL_OUT,
 274                imx_clk_gate("arm_pll_out", "arm_pll_bypass",
 275                             base + 0x84, 11));
 276         clk_dm(IMX8MM_SYS_PLL1_OUT,
 277                imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
 278                             base + 0x94, 11));
 279         clk_dm(IMX8MM_SYS_PLL2_OUT,
 280                imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
 281                             base + 0x104, 11));
 282         clk_dm(IMX8MM_SYS_PLL3_OUT,
 283                imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
 284                             base + 0x114, 11));
 285
 286         /* SYS PLL fixed output */
 287         clk_dm(IMX8MM_SYS_PLL1_40M,
 288                imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
 289         clk_dm(IMX8MM_SYS_PLL1_80M,
 290                imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
 291         clk_dm(IMX8MM_SYS_PLL1_100M,
 292                imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
 293         clk_dm(IMX8MM_SYS_PLL1_133M,
 294                imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
 295         clk_dm(IMX8MM_SYS_PLL1_160M,
 296                imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
 297         clk_dm(IMX8MM_SYS_PLL1_200M,
 298                imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
 299         clk_dm(IMX8MM_SYS_PLL1_266M,
 300                imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
 301         clk_dm(IMX8MM_SYS_PLL1_400M,
 302                imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
 303         clk_dm(IMX8MM_SYS_PLL1_800M,
 304                imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
 305
 306         clk_dm(IMX8MM_SYS_PLL2_50M,
 307                imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
 308         clk_dm(IMX8MM_SYS_PLL2_100M,
 309                imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
 310         clk_dm(IMX8MM_SYS_PLL2_125M,
 311                imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
 312         clk_dm(IMX8MM_SYS_PLL2_166M,
 313                imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
 314         clk_dm(IMX8MM_SYS_PLL2_200M,
 315                imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
 316         clk_dm(IMX8MM_SYS_PLL2_250M,
 317                imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
 318         clk_dm(IMX8MM_SYS_PLL2_333M,
 319                imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
 320         clk_dm(IMX8MM_SYS_PLL2_500M,
 321                imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
 322         clk_dm(IMX8MM_SYS_PLL2_1000M,
 323                imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 324
 325         base = dev_read_addr_ptr(dev);
 326         if (!base)
 327                 return -EINVAL;
 328
 329         clk_dm(IMX8MM_CLK_A53_SRC,
 330                imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
 331                             imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
 332         clk_dm(IMX8MM_CLK_A53_CG,
 333                imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 334         clk_dm(IMX8MM_CLK_A53_DIV,
 335                imx_clk_divider2("arm_a53_div", "arm_a53_cg",
 336                                 base + 0x8000, 0, 3));
 337
 338         clk_dm(IMX8MM_CLK_AHB,
 339                imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
 340                                             base + 0x9000));
 341         clk_dm(IMX8MM_CLK_IPG_ROOT,
 342                imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
 343
 344         clk_dm(IMX8MM_CLK_ENET_AXI,
 345                imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
 346                                    base + 0x8880));
 347         clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
 348                imx8m_clk_composite_critical("nand_usdhc_bus",
 349                                             imx8mm_nand_usdhc_sels,
 350                                             base + 0x8900));
 351
 352         /* IP */
 353         clk_dm(IMX8MM_CLK_USDHC1,
 354                imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
 355                                    base + 0xac00));
 356         clk_dm(IMX8MM_CLK_USDHC2,
 357                imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
 358                                    base + 0xac80));
 359         clk_dm(IMX8MM_CLK_I2C1,
 360                imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
 361         clk_dm(IMX8MM_CLK_I2C2,
 362                imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
 363         clk_dm(IMX8MM_CLK_I2C3,
 364                imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
 365         clk_dm(IMX8MM_CLK_I2C4,
 366                imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
 367         clk_dm(IMX8MM_CLK_WDOG,
 368                imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
 369         clk_dm(IMX8MM_CLK_USDHC3,
 370                imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
 371                                    base + 0xbc80));
 372
 373         clk_dm(IMX8MM_CLK_I2C1_ROOT,
 374                imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 375         clk_dm(IMX8MM_CLK_I2C2_ROOT,
 376                imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 377         clk_dm(IMX8MM_CLK_I2C3_ROOT,
 378                imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 379         clk_dm(IMX8MM_CLK_I2C4_ROOT,
 380                imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 381         clk_dm(IMX8MM_CLK_OCOTP_ROOT,
 382                imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 383         clk_dm(IMX8MM_CLK_USDHC1_ROOT,
 384                imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 385         clk_dm(IMX8MM_CLK_USDHC2_ROOT,
 386                imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 387         clk_dm(IMX8MM_CLK_WDOG1_ROOT,
 388                imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
 389         clk_dm(IMX8MM_CLK_WDOG2_ROOT,
 390                imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
 391         clk_dm(IMX8MM_CLK_WDOG3_ROOT,
 392                imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
 393         clk_dm(IMX8MM_CLK_USDHC3_ROOT,
 394                imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 395
 396         /* clks not needed in SPL stage */
 397 #ifndef CONFIG_SPL_BUILD
 398         clk_dm(IMX8MM_CLK_ENET_REF,
 399                imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
 400                base + 0xa980));
 401         clk_dm(IMX8MM_CLK_ENET_TIMER,
 402                imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
 403                base + 0xaa00));
 404         clk_dm(IMX8MM_CLK_ENET_PHY_REF,
 405                imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
 406                base + 0xaa80));
 407         clk_dm(IMX8MM_CLK_ENET1_ROOT,
 408                imx_clk_gate4("enet1_root_clk", "enet_axi",
 409                base + 0x40a0, 0));
 410 #endif
 411
 412 #ifdef CONFIG_SPL_BUILD
 413         struct clk *clkp, *clkp1;
 414
 415         clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
 416         clk_enable(clkp);
 417         clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
 418         clk_enable(clkp);
 419         clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
 420         clk_enable(clkp);
 421
 422         /* Configure SYS_PLL3 to 750MHz */
 423         clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
 424         clk_set_rate(clkp, 750000000UL);
 425         clk_enable(clkp);
 426
 427         /* Configure ARM to sys_pll2_500m */
 428         clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
 429         clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1);
 430         clk_enable(clkp1);
 431         clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1);
 432         clk_set_parent(clkp, clkp1);
 433
 434         /* Configure ARM PLL to 1.2GHz */
 435         clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
 436         clk_set_rate(clkp1, 1200000000UL);
 437         clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
 438         clk_enable(clkp1);
 439         clk_set_parent(clkp, clkp1);
 440
 441         /* Configure DIV to 1.2GHz */
 442         clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
 443         clk_set_rate(clkp1, 1200000000UL);
 444 #endif
 445
 446         return 0;
 447 }
 448
 449 static const struct udevice_id imx8mm_clk_ids[] = {
 450         { .compatible = "fsl,imx8mm-ccm" },
 451         { },
 452 };
 453
 454 U_BOOT_DRIVER(imx8mm_clk) = {
 455         .name = "clk_imx8mm",
 456         .id = UCLASS_CLK,
 457         .of_match = imx8mm_clk_ids,
 458         .ops = &imx8mm_clk_ops,
 459         .probe = imx8mm_clk_probe,
 460         .flags = DM_FLAG_PRE_RELOC,
 461 };