drivers/clk/imx/clk-composite-8m.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <malloc.h>
   9 #include <clk-uclass.h>
  10 #include <dm/device.h>
  11 #include <linux/clk-provider.h>
  12 #include <clk.h>
  13 #include "clk.h"
  14
  15 #define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
  16
  17 #define PCG_PREDIV_SHIFT        16
  18 #define PCG_PREDIV_WIDTH        3
  19 #define PCG_PREDIV_MAX          8
  20
  21 #define PCG_DIV_SHIFT           0
  22 #define PCG_DIV_WIDTH           6
  23 #define PCG_DIV_MAX             64
  24
  25 #define PCG_PCS_SHIFT           24
  26 #define PCG_PCS_MASK            0x7
  27
  28 #define PCG_CGC_SHIFT           28
  29
  30 static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
  31 {
  32         struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  33         struct clk_composite *composite = (struct clk_composite *)clk->data;
  34         ulong parent_rate = clk_get_parent_rate(&composite->clk);
  35         unsigned long prediv_rate;
  36         unsigned int prediv_value;
  37         unsigned int div_value;
  38
  39         debug("%s: name %s prate: %lu reg: %p\n", __func__,
  40               (&composite->clk)->dev->name, parent_rate, divider->reg);
  41         prediv_value = readl(divider->reg) >> divider->shift;
  42         prediv_value &= clk_div_mask(divider->width);
  43
  44         prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
  45                                           NULL, divider->flags,
  46                                           divider->width);
  47
  48         div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
  49         div_value &= clk_div_mask(PCG_DIV_WIDTH);
  50
  51         return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
  52                                    divider->flags, PCG_DIV_WIDTH);
  53 }
  54
  55 static int imx8m_clk_composite_compute_dividers(unsigned long rate,
  56                                                 unsigned long parent_rate,
  57                                                 int *prediv, int *postdiv)
  58 {
  59         int div1, div2;
  60         int error = INT_MAX;
  61         int ret = -EINVAL;
  62
  63         *prediv = 1;
  64         *postdiv = 1;
  65
  66         for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
  67                 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
  68                         int new_error = ((parent_rate / div1) / div2) - rate;
  69
  70                         if (abs(new_error) < abs(error)) {
  71                                 *prediv = div1;
  72                                 *postdiv = div2;
  73                                 error = new_error;
  74                                 ret = 0;
  75                         }
  76                 }
  77         }
  78         return ret;
  79 }
  80
  81 /*
  82  * The clk are bound to a dev, because it is part of composite clk
  83  * use composite clk to get dev
  84  */
  85 static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
  86                                                   unsigned long rate)
  87 {
  88         struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  89         struct clk_composite *composite = (struct clk_composite *)clk->data;
  90         ulong parent_rate = clk_get_parent_rate(&composite->clk);
  91         int prediv_value;
  92         int div_value;
  93         int ret;
  94         u32 val;
  95
  96         ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
  97                                                    &prediv_value, &div_value);
  98         if (ret)
  99                 return ret;
 100
 101         val = readl(divider->reg);
 102         val &= ~((clk_div_mask(divider->width) << divider->shift) |
 103                         (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
 104
 105         val |= (u32)(prediv_value  - 1) << divider->shift;
 106         val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
 107         writel(val, divider->reg);
 108
 109         return clk_get_rate(&composite->clk);
 110 }
 111
 112 static const struct clk_ops imx8m_clk_composite_divider_ops = {
 113         .get_rate = imx8m_clk_composite_divider_recalc_rate,
 114         .set_rate = imx8m_clk_composite_divider_set_rate,
 115 };
 116
 117 struct clk *imx8m_clk_composite_flags(const char *name,
 118                                       const char * const *parent_names,
 119                                       int num_parents, void __iomem *reg,
 120                                       unsigned long flags)
 121 {
 122         struct clk *clk = ERR_PTR(-ENOMEM);
 123         struct clk_divider *div = NULL;
 124         struct clk_gate *gate = NULL;
 125         struct clk_mux *mux = NULL;
 126
 127         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 128         if (!mux)
 129                 goto fail;
 130
 131         mux->reg = reg;
 132         mux->shift = PCG_PCS_SHIFT;
 133         mux->mask = PCG_PCS_MASK;
 134         mux->num_parents = num_parents;
 135         mux->flags = flags;
 136         mux->parent_names = parent_names;
 137
 138         div = kzalloc(sizeof(*div), GFP_KERNEL);
 139         if (!div)
 140                 goto fail;
 141
 142         div->reg = reg;
 143         div->shift = PCG_PREDIV_SHIFT;
 144         div->width = PCG_PREDIV_WIDTH;
 145         div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
 146
 147         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 148         if (!gate)
 149                 goto fail;
 150
 151         gate->reg = reg;
 152         gate->bit_idx = PCG_CGC_SHIFT;
 153         gate->flags = flags;
 154
 155         clk = clk_register_composite(NULL, name,
 156                                      parent_names, num_parents,
 157                                      &mux->clk, &clk_mux_ops, &div->clk,
 158                                      &imx8m_clk_composite_divider_ops,
 159                                      &gate->clk, &clk_gate_ops, flags);
 160         if (IS_ERR(clk))
 161                 goto fail;
 162
 163         return clk;
 164
 165 fail:
 166         kfree(gate);
 167         kfree(div);
 168         kfree(mux);
 169         return ERR_CAST(clk);
 170 }