drivers/clk/clk_sandbox_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Common Clock Framework [CCF] driver for Sandbox
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <asm/clk.h>
  13 #include <clk-uclass.h>
  14 #include <linux/clk-provider.h>
  15 #include <sandbox-clk.h>
  16
  17 /*
  18  * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  19  *
  20  * --- Sandbox PLLv3 ---
  21  */
  22 struct clk_pllv3 {
  23         struct clk      clk;
  24         u32             div_mask;
  25         u32             div_shift;
  26 };
  27
  28 static ulong clk_pllv3_get_rate(struct clk *clk)
  29 {
  30         unsigned long parent_rate = clk_get_parent_rate(clk);
  31
  32         return parent_rate * 24;
  33 }
  34
  35 static const struct clk_ops clk_pllv3_generic_ops = {
  36         .get_rate       = clk_pllv3_get_rate,
  37 };
  38
  39 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  40                               const char *parent_name, void __iomem *base,
  41                               u32 div_mask)
  42 {
  43         struct clk_pllv3 *pll;
  44         struct clk *clk;
  45         char *drv_name = "sandbox_clk_pllv3";
  46         int ret;
  47
  48         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  49         if (!pll)
  50                 return ERR_PTR(-ENOMEM);
  51
  52         pll->div_mask = div_mask;
  53         clk = &pll->clk;
  54
  55         ret = clk_register(clk, drv_name, name, parent_name);
  56         if (ret) {
  57                 kfree(pll);
  58                 return ERR_PTR(ret);
  59         }
  60
  61         return clk;
  62 }
  63
  64 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  65         .name   = "sandbox_clk_pllv3",
  66         .id     = UCLASS_CLK,
  67         .ops    = &clk_pllv3_generic_ops,
  68 };
  69
  70 /* --- Sandbox PLLv3 --- */
  71 /* --- Sandbox Gate  --- */
  72 struct clk_gate2 {
  73         struct clk clk;
  74         bool    state;
  75 };
  76
  77 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  78
  79 static int clk_gate2_enable(struct clk *clk)
  80 {
  81         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  82
  83         gate->state = 1;
  84         return 0;
  85 }
  86
  87 static int clk_gate2_disable(struct clk *clk)
  88 {
  89         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  90
  91         gate->state = 0;
  92         return 0;
  93 }
  94
  95 static const struct clk_ops clk_gate2_ops = {
  96         .enable = clk_gate2_enable,
  97         .disable = clk_gate2_disable,
  98         .get_rate = clk_generic_get_rate,
  99 };
 100
 101 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 102                                        const char *parent_name,
 103                                        unsigned long flags, void __iomem *reg,
 104                                        u8 bit_idx, u8 cgr_val,
 105                                        u8 clk_gate2_flags)
 106 {
 107         struct clk_gate2 *gate;
 108         struct clk *clk;
 109         int ret;
 110
 111         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 112         if (!gate)
 113                 return ERR_PTR(-ENOMEM);
 114
 115         gate->state = 0;
 116         clk = &gate->clk;
 117
 118         ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
 119         if (ret) {
 120                 kfree(gate);
 121                 return ERR_PTR(ret);
 122         }
 123
 124         return clk;
 125 }
 126
 127 U_BOOT_DRIVER(sandbox_clk_gate2) = {
 128         .name   = "sandbox_clk_gate2",
 129         .id     = UCLASS_CLK,
 130         .ops    = &clk_gate2_ops,
 131 };
 132
 133 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
 134 {
 135         struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
 136         struct clk_composite *composite = (struct clk_composite *)clk->data;
 137         ulong parent_rate = clk_get_parent_rate(&composite->clk);
 138         unsigned int val;
 139
 140         val = divider->io_divider_val;
 141         val >>= divider->shift;
 142         val &= clk_div_mask(divider->width);
 143
 144         return divider_recalc_rate(clk, parent_rate, val, divider->table,
 145                                    divider->flags, divider->width);
 146 }
 147
 148 static const struct clk_ops sandbox_clk_composite_divider_ops = {
 149         .get_rate = sandbox_clk_composite_divider_recalc_rate,
 150 };
 151
 152 struct clk *sandbox_clk_composite(const char *name,
 153                                   const char * const *parent_names,
 154                                   int num_parents, void __iomem *reg,
 155                                   unsigned long flags)
 156 {
 157         struct clk *clk = ERR_PTR(-ENOMEM);
 158         struct clk_divider *div = NULL;
 159         struct clk_gate *gate = NULL;
 160         struct clk_mux *mux = NULL;
 161
 162         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 163         if (!mux)
 164                 goto fail;
 165
 166         mux->reg = reg;
 167         mux->shift = 24;
 168         mux->mask = 0x7;
 169         mux->num_parents = num_parents;
 170         mux->flags = flags;
 171         mux->parent_names = parent_names;
 172
 173         div = kzalloc(sizeof(*div), GFP_KERNEL);
 174         if (!div)
 175                 goto fail;
 176
 177         div->reg = reg;
 178         div->shift = 16;
 179         div->width = 3;
 180         div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
 181
 182         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 183         if (!gate)
 184                 goto fail;
 185
 186         gate->reg = reg;
 187         gate->bit_idx = 28;
 188         gate->flags = flags;
 189
 190         clk = clk_register_composite(NULL, name,
 191                                      parent_names, num_parents,
 192                                      &mux->clk, &clk_mux_ops, &div->clk,
 193                                      &sandbox_clk_composite_divider_ops,
 194                                      &gate->clk, &clk_gate_ops, flags);
 195         if (IS_ERR(clk))
 196                 goto fail;
 197
 198         return clk;
 199
 200 fail:
 201         kfree(gate);
 202         kfree(div);
 203         kfree(mux);
 204         return ERR_CAST(clk);
 205 }
 206
 207 /* --- Sandbox Gate --- */
 208 /* The CCF core driver itself */
 209 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
 210         { .compatible = "sandbox,clk-ccf" },
 211         { }
 212 };
 213
 214 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
 215 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
 216
 217 static int sandbox_clk_ccf_probe(struct udevice *dev)
 218 {
 219         void *base = NULL;
 220         u32 reg;
 221
 222         clk_dm(SANDBOX_CLK_PLL3,
 223                sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
 224                                  base + 0x10, 0x3));
 225
 226         clk_dm(SANDBOX_CLK_PLL3_60M,
 227                sandbox_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
 228
 229         clk_dm(SANDBOX_CLK_PLL3_80M,
 230                sandbox_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
 231
 232         /* The HW adds +1 to the divider value (2+1) is the divider */
 233         reg = (2 << 19);
 234         clk_dm(SANDBOX_CLK_ECSPI_ROOT,
 235                sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
 236
 237         clk_dm(SANDBOX_CLK_ECSPI1,
 238                sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 239
 240         /* Select 'pll3_60m' */
 241         reg = 0;
 242         clk_dm(SANDBOX_CLK_USDHC1_SEL,
 243                sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
 244                                ARRAY_SIZE(usdhc_sels)));
 245
 246         /* Select 'pll3_80m' */
 247         reg = BIT(17);
 248         clk_dm(SANDBOX_CLK_USDHC2_SEL,
 249                sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
 250                                ARRAY_SIZE(usdhc_sels)));
 251
 252         reg = BIT(28) | BIT(24) | BIT(16);
 253         clk_dm(SANDBOX_CLK_I2C,
 254                sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
 255                                      &reg, 0));
 256
 257         return 0;
 258 }
 259
 260 U_BOOT_DRIVER(sandbox_clk_ccf) = {
 261         .name = "sandbox_clk_ccf",
 262         .id = UCLASS_CLK,
 263         .probe = sandbox_clk_ccf_probe,
 264         .of_match = sandbox_clk_ccf_test_ids,
 265 };