1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
7 #include <clk-uclass.h>
9 #include <linux/clk-provider.h>
11 static ulong clk_fixed_rate_get_rate(struct clk *clk)
13 return to_clk_fixed_rate(clk->dev)->fixed_rate;
16 /* avoid clk_enable() return -ENOSYS */
17 static int dummy_enable(struct clk *clk)
22 const struct clk_ops clk_fixed_rate_ops = {
23 .get_rate = clk_fixed_rate_get_rate,
24 .enable = dummy_enable,
27 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
29 struct clk *clk = &to_clk_fixed_rate(dev)->clk;
30 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
31 to_clk_fixed_rate(dev)->fixed_rate =
32 dev_read_u32_default(dev, "clock-frequency", 0);
34 /* Make fixed rate clock accessible from higher level struct clk */
35 dev->uclass_priv = clk;
37 clk->enable_count = 0;
42 static const struct udevice_id clk_fixed_rate_match[] = {
44 .compatible = "fixed-clock",
49 U_BOOT_DRIVER(clk_fixed_rate) = {
50 .name = "fixed_rate_clock",
52 .of_match = clk_fixed_rate_match,
53 .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
54 .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
55 .ops = &clk_fixed_rate_ops,