drivers/clk/clk-hsdk-cgu.c

   1 /*
   2  * Synopsys HSDK SDP CGU clock driver
   3  *
   4  * Copyright (C) 2017 Synopsys
   5  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <common.h>
  13 #include <clk-uclass.h>
  14 #include <div64.h>
  15 #include <dm.h>
  16 #include <log.h>
  17 #include <linux/io.h>
  18 #include <asm/arcregs.h>
  19
  20 #include <dt-bindings/clock/snps,hsdk-cgu.h>
  21
  22 /*
  23  * Synopsys ARC HSDK clock tree.
  24  *
  25  *   ------------------
  26  *   | 33.33 MHz xtal |
  27  *   ------------------
  28  *            |
  29  *            |   -----------
  30  *            |-->| ARC PLL |
  31  *            |   -----------
  32  *            |        |
  33  *            |        |-->|CGU_ARC_IDIV|----------->
  34  *            |        |-->|CREG_CORE_IF_DIV|------->
  35  *            |
  36  *            |   --------------
  37  *            |-->| SYSTEM PLL |
  38  *            |   --------------
  39  *            |        |
  40  *            |        |-->|CGU_SYS_IDIV_APB|------->
  41  *            |        |-->|CGU_SYS_IDIV_AXI|------->
  42  *            |        |-->|CGU_SYS_IDIV_*|--------->
  43  *            |        |-->|CGU_SYS_IDIV_EBI_REF|--->
  44  *            |
  45  *            |   --------------
  46  *            |-->| TUNNEL PLL |
  47  *            |   --------------
  48  *            |        |
  49  *            |        |-->|CGU_TUN_IDIV_TUN|----------->
  50  *            |        |-->|CGU_TUN_IDIV_ROM|----------->
  51  *            |        |-->|CGU_TUN_IDIV_PWM|----------->
  52  *            |
  53  *            |   -----------
  54  *            |-->| DDR PLL |
  55  *                -----------
  56  *                     |
  57  *                     |---------------------------->
  58  *
  59  *   ------------------
  60  *   | 27.00 MHz xtal |
  61  *   ------------------
  62  *            |
  63  *            |   ------------
  64  *            |-->| HDMI PLL |
  65  *                ------------
  66  *                     |
  67  *                     |-->|CGU_HDMI_IDIV_APB|------>
  68  */
  69
  70 #define CGU_ARC_IDIV            0x080
  71 #define CGU_TUN_IDIV_TUN        0x380
  72 #define CGU_TUN_IDIV_ROM        0x390
  73 #define CGU_TUN_IDIV_PWM        0x3A0
  74 #define CGU_TUN_IDIV_TIMER      0x3B0
  75 #define CGU_HDMI_IDIV_APB       0x480
  76 #define CGU_SYS_IDIV_APB        0x180
  77 #define CGU_SYS_IDIV_AXI        0x190
  78 #define CGU_SYS_IDIV_ETH        0x1A0
  79 #define CGU_SYS_IDIV_USB        0x1B0
  80 #define CGU_SYS_IDIV_SDIO       0x1C0
  81 #define CGU_SYS_IDIV_HDMI       0x1D0
  82 #define CGU_SYS_IDIV_GFX_CORE   0x1E0
  83 #define CGU_SYS_IDIV_GFX_DMA    0x1F0
  84 #define CGU_SYS_IDIV_GFX_CFG    0x200
  85 #define CGU_SYS_IDIV_DMAC_CORE  0x210
  86 #define CGU_SYS_IDIV_DMAC_CFG   0x220
  87 #define CGU_SYS_IDIV_SDIO_REF   0x230
  88 #define CGU_SYS_IDIV_SPI_REF    0x240
  89 #define CGU_SYS_IDIV_I2C_REF    0x250
  90 #define CGU_SYS_IDIV_UART_REF   0x260
  91 #define CGU_SYS_IDIV_EBI_REF    0x270
  92
  93 #define CGU_IDIV_MASK           0xFF /* All idiv have 8 significant bits */
  94
  95 #define CGU_ARC_PLL             0x0
  96 #define CGU_SYS_PLL             0x10
  97 #define CGU_DDR_PLL             0x20
  98 #define CGU_TUN_PLL             0x30
  99 #define CGU_HDMI_PLL            0x40
 100
 101 #define CGU_PLL_CTRL            0x000 /* ARC PLL control register */
 102 #define CGU_PLL_STATUS          0x004 /* ARC PLL status register */
 103 #define CGU_PLL_FMEAS           0x008 /* ARC PLL frequency measurement register */
 104 #define CGU_PLL_MON             0x00C /* ARC PLL monitor register */
 105
 106 #define CGU_PLL_CTRL_ODIV_SHIFT         2
 107 #define CGU_PLL_CTRL_IDIV_SHIFT         4
 108 #define CGU_PLL_CTRL_FBDIV_SHIFT        9
 109 #define CGU_PLL_CTRL_BAND_SHIFT         20
 110
 111 #define CGU_PLL_CTRL_ODIV_MASK          GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
 112 #define CGU_PLL_CTRL_IDIV_MASK          GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
 113 #define CGU_PLL_CTRL_FBDIV_MASK         GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
 114
 115 #define CGU_PLL_CTRL_PD                 BIT(0)
 116 #define CGU_PLL_CTRL_BYPASS             BIT(1)
 117
 118 #define CGU_PLL_STATUS_LOCK             BIT(0)
 119 #define CGU_PLL_STATUS_ERR              BIT(1)
 120
 121 #define HSDK_PLL_MAX_LOCK_TIME          100 /* 100 us */
 122
 123 #define CREG_CORE_IF_DIV                0x000 /* ARC CORE interface divider */
 124 #define CORE_IF_CLK_THRESHOLD_HZ        500000000
 125 #define CREG_CORE_IF_CLK_DIV_1          0x0
 126 #define CREG_CORE_IF_CLK_DIV_2          0x1
 127
 128 #define MIN_PLL_RATE                    100000000 /* 100 MHz */
 129 #define PARENT_RATE_33                  33333333 /* fixed clock - xtal */
 130 #define PARENT_RATE_27                  27000000 /* fixed clock - xtal */
 131 #define CGU_MAX_CLOCKS                  27
 132
 133 #define MAX_FREQ_VARIATIONS             6
 134
 135 struct hsdk_idiv_cfg {
 136         const u32 oft;
 137         const u8  val[MAX_FREQ_VARIATIONS];
 138 };
 139
 140 struct hsdk_div_full_cfg {
 141         const u32 clk_rate[MAX_FREQ_VARIATIONS];
 142         const u32 pll_rate[MAX_FREQ_VARIATIONS];
 143         const struct hsdk_idiv_cfg idiv[];
 144 };
 145
 146 static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
 147         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 148         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 149         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 150         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 151         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 152         { CGU_TUN_IDIV_TIMER,   { 12,   12,     12,     12,     15,     12 } },
 153         { /* last one */ }
 154         }
 155 };
 156
 157 static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
 158         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 159         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 160         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 161         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 162         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 163         { /* last one */ }
 164         }
 165 };
 166
 167 static const struct hsdk_div_full_cfg axi_clk_cfg = {
 168         { 200000000,    400000000,      600000000,      800000000 },
 169         { 800000000,    800000000,      600000000,      800000000 }, {
 170         { CGU_SYS_IDIV_APB,      { 4,   4,      3,      4 } },  /* APB */
 171         { CGU_SYS_IDIV_AXI,      { 4,   2,      1,      1 } },  /* AXI */
 172         { CGU_SYS_IDIV_ETH,      { 2,   2,      2,      2 } },  /* ETH */
 173         { CGU_SYS_IDIV_USB,      { 2,   2,      2,      2 } },  /* USB */
 174         { CGU_SYS_IDIV_SDIO,     { 2,   2,      2,      2 } },  /* SDIO */
 175         { CGU_SYS_IDIV_HDMI,     { 2,   2,      2,      2 } },  /* HDMI */
 176         { CGU_SYS_IDIV_GFX_CORE, { 1,   1,      1,      1 } },  /* GPU-CORE */
 177         { CGU_SYS_IDIV_GFX_DMA,  { 2,   2,      2,      2 } },  /* GPU-DMA */
 178         { CGU_SYS_IDIV_GFX_CFG,  { 4,   4,      3,      4 } },  /* GPU-CFG */
 179         { CGU_SYS_IDIV_DMAC_CORE,{ 2,   2,      2,      2 } },  /* DMAC-CORE */
 180         { CGU_SYS_IDIV_DMAC_CFG, { 4,   4,      3,      4 } },  /* DMAC-CFG */
 181         { CGU_SYS_IDIV_SDIO_REF, { 8,   8,      6,      8 } },  /* SDIO-REF */
 182         { CGU_SYS_IDIV_SPI_REF,  { 24,  24,     18,     24 } }, /* SPI-REF */
 183         { CGU_SYS_IDIV_I2C_REF,  { 4,   4,      3,      4 } },  /* I2C-REF */
 184         { CGU_SYS_IDIV_UART_REF, { 24,  24,     18,     24 } }, /* UART-REF */
 185         { CGU_SYS_IDIV_EBI_REF,  { 16,  16,     12,     16 } }, /* EBI-REF */
 186         { /* last one */ }
 187         }
 188 };
 189
 190 struct hsdk_pll_cfg {
 191         const u32 rate;
 192         const u8  idiv;
 193         const u8  fbdiv;
 194         const u8  odiv;
 195         const u8  band;
 196 };
 197
 198 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
 199         { 100000000,  0, 11, 3, 0 },
 200         { 125000000,  0, 14, 3, 0 },
 201         { 133000000,  0, 15, 3, 0 },
 202         { 150000000,  0, 17, 3, 0 },
 203         { 200000000,  1, 47, 3, 0 },
 204         { 233000000,  1, 27, 2, 0 },
 205         { 300000000,  1, 35, 2, 0 },
 206         { 333000000,  1, 39, 2, 0 },
 207         { 400000000,  1, 47, 2, 0 },
 208         { 500000000,  0, 14, 1, 0 },
 209         { 600000000,  0, 17, 1, 0 },
 210         { 700000000,  0, 20, 1, 0 },
 211         { 750000000,  1, 44, 1, 0 },
 212         { 800000000,  0, 23, 1, 0 },
 213         { 900000000,  1, 26, 0, 0 },
 214         { 1000000000, 1, 29, 0, 0 },
 215         { 1100000000, 1, 32, 0, 0 },
 216         { 1200000000, 1, 35, 0, 0 },
 217         { 1300000000, 1, 38, 0, 0 },
 218         { 1400000000, 1, 41, 0, 0 },
 219         { 1500000000, 1, 44, 0, 0 },
 220         { 1600000000, 1, 47, 0, 0 },
 221         {}
 222 };
 223
 224 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
 225         { 297000000,  0, 21, 2, 0 },
 226         { 540000000,  0, 19, 1, 0 },
 227         { 594000000,  0, 21, 1, 0 },
 228         {}
 229 };
 230
 231 struct hsdk_cgu_domain {
 232         /* PLLs registers */
 233         void __iomem *pll_regs;
 234         /* PLLs special registers */
 235         void __iomem *spec_regs;
 236         /* PLLs devdata */
 237         const struct hsdk_pll_devdata *pll;
 238
 239         /* Dividers registers */
 240         void __iomem *idiv_regs;
 241 };
 242
 243 struct hsdk_cgu_clk {
 244         const struct cgu_clk_map *map;
 245         /* CGU block register */
 246         void __iomem *cgu_regs;
 247         /* CREG block register */
 248         void __iomem *creg_regs;
 249
 250         /* The domain we are working with */
 251         struct hsdk_cgu_domain curr_domain;
 252 };
 253
 254 struct hsdk_pll_devdata {
 255         const u32 parent_rate;
 256         const struct hsdk_pll_cfg *const pll_cfg;
 257         const int (*const update_rate)(struct hsdk_cgu_clk *clk,
 258                                        unsigned long rate,
 259                                        const struct hsdk_pll_cfg *cfg);
 260 };
 261
 262 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
 263                                      const struct hsdk_pll_cfg *);
 264 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
 265                                      const struct hsdk_pll_cfg *);
 266
 267 static const struct hsdk_pll_devdata core_pll_dat = {
 268         .parent_rate = PARENT_RATE_33,
 269         .pll_cfg = asdt_pll_cfg,
 270         .update_rate = hsdk_pll_core_update_rate,
 271 };
 272
 273 static const struct hsdk_pll_devdata sdt_pll_dat = {
 274         .parent_rate = PARENT_RATE_33,
 275         .pll_cfg = asdt_pll_cfg,
 276         .update_rate = hsdk_pll_comm_update_rate,
 277 };
 278
 279 static const struct hsdk_pll_devdata hdmi_pll_dat = {
 280         .parent_rate = PARENT_RATE_27,
 281         .pll_cfg = hdmi_pll_cfg,
 282         .update_rate = hsdk_pll_comm_update_rate,
 283 };
 284
 285 static ulong idiv_set(struct clk *, ulong);
 286 static ulong cpu_clk_set(struct clk *, ulong);
 287 static ulong axi_clk_set(struct clk *, ulong);
 288 static ulong tun_hsdk_set(struct clk *, ulong);
 289 static ulong tun_h4xd_set(struct clk *, ulong);
 290 static ulong idiv_get(struct clk *);
 291 static int idiv_off(struct clk *);
 292 static ulong pll_set(struct clk *, ulong);
 293 static ulong pll_get(struct clk *);
 294
 295 struct cgu_clk_map {
 296         const u32 cgu_pll_oft;
 297         const u32 cgu_div_oft;
 298         const struct hsdk_pll_devdata *const pll_devdata;
 299         const ulong (*const get_rate)(struct clk *clk);
 300         const ulong (*const set_rate)(struct clk *clk, ulong rate);
 301         const int (*const disable)(struct clk *clk);
 302 };
 303
 304 static const struct cgu_clk_map hsdk_clk_map[] = {
 305         [CLK_ARC_PLL]        = { CGU_ARC_PLL,  0,                      &core_pll_dat, pll_get,  pll_set,      NULL     },
 306         [CLK_ARC]            = { CGU_ARC_PLL,  CGU_ARC_IDIV,           &core_pll_dat, idiv_get, cpu_clk_set,  idiv_off },
 307         [CLK_DDR_PLL]        = { CGU_DDR_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 308         [CLK_SYS_PLL]        = { CGU_SYS_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 309         [CLK_SYS_APB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_APB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 310         [CLK_SYS_AXI]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_AXI,       &sdt_pll_dat,  idiv_get, axi_clk_set,  idiv_off },
 311         [CLK_SYS_ETH]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_ETH,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 312         [CLK_SYS_USB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_USB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 313         [CLK_SYS_SDIO]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 314         [CLK_SYS_HDMI]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_HDMI,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 315         [CLK_SYS_GFX_CORE]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CORE,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 316         [CLK_SYS_GFX_DMA]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_DMA,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 317         [CLK_SYS_GFX_CFG]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CFG,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 318         [CLK_SYS_DMAC_CORE]  = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 319         [CLK_SYS_DMAC_CFG]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CFG,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 320         [CLK_SYS_SDIO_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 321         [CLK_SYS_SPI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_SPI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 322         [CLK_SYS_I2C_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_I2C_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 323         [CLK_SYS_UART_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_UART_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 324         [CLK_SYS_EBI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_EBI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 325         [CLK_TUN_PLL]        = { CGU_TUN_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 326         [CLK_TUN_TUN]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_TUN,       &sdt_pll_dat,  idiv_get, tun_hsdk_set, idiv_off },
 327         [CLK_TUN_ROM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_ROM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 328         [CLK_TUN_PWM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_PWM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 329         [CLK_TUN_TIMER]      = { /* missing in HSDK */ },
 330         [CLK_HDMI_PLL]       = { CGU_HDMI_PLL, 0,                      &hdmi_pll_dat, pll_get,  pll_set,      NULL     },
 331         [CLK_HDMI]           = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,      &hdmi_pll_dat, idiv_get, idiv_set,     idiv_off }
 332 };
 333
 334 static const struct cgu_clk_map hsdk_4xd_clk_map[] = {
 335         [CLK_ARC_PLL]        = { CGU_ARC_PLL,  0,                      &core_pll_dat, pll_get,  pll_set,      NULL     },
 336         [CLK_ARC]            = { CGU_ARC_PLL,  CGU_ARC_IDIV,           &core_pll_dat, idiv_get, cpu_clk_set,  idiv_off },
 337         [CLK_DDR_PLL]        = { CGU_DDR_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 338         [CLK_SYS_PLL]        = { CGU_SYS_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 339         [CLK_SYS_APB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_APB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 340         [CLK_SYS_AXI]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_AXI,       &sdt_pll_dat,  idiv_get, axi_clk_set,  idiv_off },
 341         [CLK_SYS_ETH]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_ETH,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 342         [CLK_SYS_USB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_USB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 343         [CLK_SYS_SDIO]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 344         [CLK_SYS_HDMI]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_HDMI,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 345         [CLK_SYS_GFX_CORE]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CORE,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 346         [CLK_SYS_GFX_DMA]    = { /* missing in HSDK-4xD */ },
 347         [CLK_SYS_GFX_CFG]    = { /* missing in HSDK-4xD */ },
 348         [CLK_SYS_DMAC_CORE]  = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 349         [CLK_SYS_DMAC_CFG]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CFG,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 350         [CLK_SYS_SDIO_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 351         [CLK_SYS_SPI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_SPI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 352         [CLK_SYS_I2C_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_I2C_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 353         [CLK_SYS_UART_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_UART_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 354         [CLK_SYS_EBI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_EBI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 355         [CLK_TUN_PLL]        = { CGU_TUN_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 356         [CLK_TUN_TUN]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_TUN,       &sdt_pll_dat,  idiv_get, tun_h4xd_set, idiv_off },
 357         [CLK_TUN_ROM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_ROM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 358         [CLK_TUN_PWM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_PWM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 359         [CLK_TUN_TIMER]      = { CGU_TUN_PLL,  CGU_TUN_IDIV_TIMER,     &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 360         [CLK_HDMI_PLL]       = { CGU_HDMI_PLL, 0,                      &hdmi_pll_dat, pll_get,  pll_set,      NULL     },
 361         [CLK_HDMI]           = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,      &hdmi_pll_dat, idiv_get, idiv_set,     idiv_off }
 362 };
 363
 364 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
 365 {
 366         iowrite32(val, clk->curr_domain.idiv_regs);
 367 }
 368
 369 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
 370 {
 371         return ioread32(clk->curr_domain.idiv_regs);
 372 }
 373
 374 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 375 {
 376         iowrite32(val, clk->curr_domain.pll_regs + reg);
 377 }
 378
 379 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
 380 {
 381         return ioread32(clk->curr_domain.pll_regs + reg);
 382 }
 383
 384 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 385 {
 386         iowrite32(val, clk->curr_domain.spec_regs + reg);
 387 }
 388
 389 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
 390 {
 391         return ioread32(clk->curr_domain.spec_regs + reg);
 392 }
 393
 394 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
 395                                     const struct hsdk_pll_cfg *cfg)
 396 {
 397         u32 val = 0;
 398
 399         /* Powerdown and Bypass bits should be cleared */
 400         val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
 401         val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
 402         val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
 403         val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
 404
 405         pr_debug("write configurarion: %#x\n", val);
 406
 407         hsdk_pll_write(clk, CGU_PLL_CTRL, val);
 408 }
 409
 410 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
 411 {
 412         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
 413 }
 414
 415 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
 416 {
 417         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
 418 }
 419
 420 static ulong pll_get(struct clk *sclk)
 421 {
 422         u32 val;
 423         u64 rate;
 424         u32 idiv, fbdiv, odiv;
 425         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 426         u32 parent_rate = clk->curr_domain.pll->parent_rate;
 427
 428         val = hsdk_pll_read(clk, CGU_PLL_CTRL);
 429
 430         pr_debug("current configurarion: %#x\n", val);
 431
 432         /* Check if PLL is bypassed */
 433         if (val & CGU_PLL_CTRL_BYPASS)
 434                 return parent_rate;
 435
 436         /* Check if PLL is disabled */
 437         if (val & CGU_PLL_CTRL_PD)
 438                 return 0;
 439
 440         /* input divider = reg.idiv + 1 */
 441         idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
 442         /* fb divider = 2*(reg.fbdiv + 1) */
 443         fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
 444         /* output divider = 2^(reg.odiv) */
 445         odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
 446
 447         rate = (u64)parent_rate * fbdiv;
 448         do_div(rate, idiv * odiv);
 449
 450         return rate;
 451 }
 452
 453 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
 454 {
 455         int i;
 456         unsigned long best_rate;
 457         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 458         const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
 459
 460         if (pll_cfg[0].rate == 0)
 461                 return -EINVAL;
 462
 463         best_rate = pll_cfg[0].rate;
 464
 465         for (i = 1; pll_cfg[i].rate != 0; i++) {
 466                 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
 467                         best_rate = pll_cfg[i].rate;
 468         }
 469
 470         pr_debug("chosen best rate: %lu\n", best_rate);
 471
 472         return best_rate;
 473 }
 474
 475 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
 476                                      unsigned long rate,
 477                                      const struct hsdk_pll_cfg *cfg)
 478 {
 479         hsdk_pll_set_cfg(clk, cfg);
 480
 481         /*
 482          * Wait until CGU relocks and check error status.
 483          * If after timeout CGU is unlocked yet return error.
 484          */
 485         udelay(HSDK_PLL_MAX_LOCK_TIME);
 486         if (!hsdk_pll_is_locked(clk))
 487                 return -ETIMEDOUT;
 488
 489         if (hsdk_pll_is_err(clk))
 490                 return -EINVAL;
 491
 492         return 0;
 493 }
 494
 495 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
 496                                      unsigned long rate,
 497                                      const struct hsdk_pll_cfg *cfg)
 498 {
 499         /*
 500          * When core clock exceeds 500MHz, the divider for the interface
 501          * clock must be programmed to div-by-2.
 502          */
 503         if (rate > CORE_IF_CLK_THRESHOLD_HZ)
 504                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
 505
 506         hsdk_pll_set_cfg(clk, cfg);
 507
 508         /*
 509          * Wait until CGU relocks and check error status.
 510          * If after timeout CGU is unlocked yet return error.
 511          */
 512         udelay(HSDK_PLL_MAX_LOCK_TIME);
 513         if (!hsdk_pll_is_locked(clk))
 514                 return -ETIMEDOUT;
 515
 516         if (hsdk_pll_is_err(clk))
 517                 return -EINVAL;
 518
 519         /*
 520          * Program divider to div-by-1 if we succesfuly set core clock below
 521          * 500MHz threshold.
 522          */
 523         if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
 524                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
 525
 526         return 0;
 527 }
 528
 529 static ulong pll_set(struct clk *sclk, ulong rate)
 530 {
 531         int i;
 532         unsigned long best_rate;
 533         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 534         const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
 535         const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
 536
 537         best_rate = hsdk_pll_round_rate(sclk, rate);
 538
 539         for (i = 0; pll_cfg[i].rate != 0; i++)
 540                 if (pll_cfg[i].rate == best_rate)
 541                         return pll->update_rate(clk, best_rate, &pll_cfg[i]);
 542
 543         pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
 544                pll->parent_rate);
 545
 546         return -EINVAL;
 547 }
 548
 549 static int idiv_off(struct clk *sclk)
 550 {
 551         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 552
 553         hsdk_idiv_write(clk, 0);
 554
 555         return 0;
 556 }
 557
 558 static ulong idiv_get(struct clk *sclk)
 559 {
 560         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 561         ulong parent_rate = pll_get(sclk);
 562         u32 div_factor = hsdk_idiv_read(clk);
 563
 564         div_factor &= CGU_IDIV_MASK;
 565
 566         pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
 567
 568         if (div_factor == 0)
 569                 return 0;
 570
 571         return parent_rate / div_factor;
 572 }
 573
 574 /* Special behavior: wen we set this clock we set both idiv and pll */
 575 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
 576 {
 577         ulong ret;
 578
 579         ret = pll_set(sclk, rate);
 580         idiv_set(sclk, rate);
 581
 582         return ret;
 583 }
 584
 585 /*
 586  * Special behavior:
 587  * when we set these clocks we set both PLL and all idiv dividers related to
 588  * this PLL domain.
 589  */
 590 static ulong common_div_clk_set(struct clk *sclk, ulong rate,
 591                                 const struct hsdk_div_full_cfg *cfg)
 592 {
 593         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 594         ulong pll_rate;
 595         int i, freq_idx = -1;
 596         ulong ret = 0;
 597
 598         pll_rate = pll_get(sclk);
 599
 600         for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
 601                 /* unused freq variations are filled with 0 */
 602                 if (!cfg->clk_rate[i])
 603                         break;
 604
 605                 if (cfg->clk_rate[i] == rate) {
 606                         freq_idx = i;
 607                         break;
 608                 }
 609         }
 610
 611         if (freq_idx < 0) {
 612                 pr_err("clk: invalid rate=%ld Hz\n", rate);
 613                 return -EINVAL;
 614         }
 615
 616         /* configure PLL before dividers */
 617         if (cfg->pll_rate[freq_idx] < pll_rate)
 618                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 619
 620         /* configure SYS dividers */
 621         for (i = 0; cfg->idiv[i].oft != 0; i++) {
 622                 clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
 623                 hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
 624         }
 625
 626         /* configure PLL after dividers */
 627         if (cfg->pll_rate[freq_idx] >= pll_rate)
 628                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 629
 630         return ret;
 631 }
 632
 633 static ulong axi_clk_set(struct clk *sclk, ulong rate)
 634 {
 635         return common_div_clk_set(sclk, rate, &axi_clk_cfg);
 636 }
 637
 638 static ulong tun_hsdk_set(struct clk *sclk, ulong rate)
 639 {
 640         return common_div_clk_set(sclk, rate, &hsdk_tun_clk_cfg);
 641 }
 642
 643 static ulong tun_h4xd_set(struct clk *sclk, ulong rate)
 644 {
 645         return common_div_clk_set(sclk, rate, &hsdk_4xd_tun_clk_cfg);
 646 }
 647
 648 static ulong idiv_set(struct clk *sclk, ulong rate)
 649 {
 650         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 651         ulong parent_rate = pll_get(sclk);
 652         u32 div_factor;
 653
 654         div_factor = parent_rate / rate;
 655         if (abs(rate - parent_rate / (div_factor + 1)) <=
 656             abs(rate - parent_rate / div_factor)) {
 657                 div_factor += 1;
 658         }
 659
 660         if (div_factor & ~CGU_IDIV_MASK) {
 661                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
 662                        rate, parent_rate, div_factor, CGU_IDIV_MASK);
 663
 664                 div_factor = CGU_IDIV_MASK;
 665         }
 666
 667         if (div_factor == 0) {
 668                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
 669                        rate, parent_rate, div_factor);
 670
 671                 div_factor = 1;
 672         }
 673
 674         hsdk_idiv_write(clk, div_factor);
 675
 676         return 0;
 677 }
 678
 679 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
 680 {
 681         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 682
 683         if (sclk->id >= CGU_MAX_CLOCKS)
 684                 return -EINVAL;
 685
 686         /* clocks missing in current map have their entry zeroed */
 687         if (!clk->map[sclk->id].pll_devdata)
 688                 return -EINVAL;
 689
 690         clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
 691         clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
 692         clk->curr_domain.spec_regs = clk->creg_regs;
 693         clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
 694
 695         return 0;
 696 }
 697
 698 static ulong hsdk_cgu_get_rate(struct clk *sclk)
 699 {
 700         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 701
 702         if (hsdk_prepare_clock_tree_branch(sclk))
 703                 return -EINVAL;
 704
 705         return clk->map[sclk->id].get_rate(sclk);
 706 }
 707
 708 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
 709 {
 710         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 711
 712         if (hsdk_prepare_clock_tree_branch(sclk))
 713                 return -EINVAL;
 714
 715         if (clk->map[sclk->id].set_rate)
 716                 return clk->map[sclk->id].set_rate(sclk, rate);
 717
 718         return -ENOTSUPP;
 719 }
 720
 721 static int hsdk_cgu_disable(struct clk *sclk)
 722 {
 723         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 724
 725         if (hsdk_prepare_clock_tree_branch(sclk))
 726                 return -EINVAL;
 727
 728         if (clk->map[sclk->id].disable)
 729                 return clk->map[sclk->id].disable(sclk);
 730
 731         return -ENOTSUPP;
 732 }
 733
 734 static const struct clk_ops hsdk_cgu_ops = {
 735         .set_rate = hsdk_cgu_set_rate,
 736         .get_rate = hsdk_cgu_get_rate,
 737         .disable = hsdk_cgu_disable,
 738 };
 739
 740 static int hsdk_cgu_clk_probe(struct udevice *dev)
 741 {
 742         struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
 743
 744         BUILD_BUG_ON(ARRAY_SIZE(hsdk_clk_map) != CGU_MAX_CLOCKS);
 745         BUILD_BUG_ON(ARRAY_SIZE(hsdk_4xd_clk_map) != CGU_MAX_CLOCKS);
 746
 747         /* Choose which clock map to use in runtime */
 748         if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF) == 0x52)
 749                 hsdk_clk->map = hsdk_clk_map;
 750         else
 751                 hsdk_clk->map = hsdk_4xd_clk_map;
 752
 753         hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
 754         if (!hsdk_clk->cgu_regs)
 755                 return -EINVAL;
 756
 757         hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
 758         if (!hsdk_clk->creg_regs)
 759                 return -EINVAL;
 760
 761         return 0;
 762 }
 763
 764 static const struct udevice_id hsdk_cgu_clk_id[] = {
 765         { .compatible = "snps,hsdk-cgu-clock" },
 766         { }
 767 };
 768
 769 U_BOOT_DRIVER(hsdk_cgu_clk) = {
 770         .name = "hsdk-cgu-clk",
 771         .id = UCLASS_CLK,
 772         .of_match = hsdk_cgu_clk_id,
 773         .probe = hsdk_cgu_clk_probe,
 774         .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
 775         .ops = &hsdk_cgu_ops,
 776 };