drivers/clk/clk-hsdk-cgu.c

   1 /*
   2  * Synopsys HSDK SDP CGU clock driver
   3  *
   4  * Copyright (C) 2017 Synopsys
   5  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <common.h>
  13 #include <clk-uclass.h>
  14 #include <div64.h>
  15 #include <dm.h>
  16 #include <log.h>
  17 #include <linux/bug.h>
  18 #include <linux/delay.h>
  19 #include <linux/io.h>
  20 #include <asm/arcregs.h>
  21
  22 #include <dt-bindings/clock/snps,hsdk-cgu.h>
  23
  24 /*
  25  * Synopsys ARC HSDK clock tree.
  26  *
  27  *   ------------------
  28  *   | 33.33 MHz xtal |
  29  *   ------------------
  30  *            |
  31  *            |   -----------
  32  *            |-->| ARC PLL |
  33  *            |   -----------
  34  *            |        |
  35  *            |        |-->|CGU_ARC_IDIV|----------->
  36  *            |        |-->|CREG_CORE_IF_DIV|------->
  37  *            |
  38  *            |   --------------
  39  *            |-->| SYSTEM PLL |
  40  *            |   --------------
  41  *            |        |
  42  *            |        |-->|CGU_SYS_IDIV_APB|------->
  43  *            |        |-->|CGU_SYS_IDIV_AXI|------->
  44  *            |        |-->|CGU_SYS_IDIV_*|--------->
  45  *            |        |-->|CGU_SYS_IDIV_EBI_REF|--->
  46  *            |
  47  *            |   --------------
  48  *            |-->| TUNNEL PLL |
  49  *            |   --------------
  50  *            |        |
  51  *            |        |-->|CGU_TUN_IDIV_TUN|----------->
  52  *            |        |-->|CGU_TUN_IDIV_ROM|----------->
  53  *            |        |-->|CGU_TUN_IDIV_PWM|----------->
  54  *            |
  55  *            |   -----------
  56  *            |-->| DDR PLL |
  57  *                -----------
  58  *                     |
  59  *                     |---------------------------->
  60  *
  61  *   ------------------
  62  *   | 27.00 MHz xtal |
  63  *   ------------------
  64  *            |
  65  *            |   ------------
  66  *            |-->| HDMI PLL |
  67  *                ------------
  68  *                     |
  69  *                     |-->|CGU_HDMI_IDIV_APB|------>
  70  */
  71
  72 #define CGU_ARC_IDIV            0x080
  73 #define CGU_TUN_IDIV_TUN        0x380
  74 #define CGU_TUN_IDIV_ROM        0x390
  75 #define CGU_TUN_IDIV_PWM        0x3A0
  76 #define CGU_TUN_IDIV_TIMER      0x3B0
  77 #define CGU_HDMI_IDIV_APB       0x480
  78 #define CGU_SYS_IDIV_APB        0x180
  79 #define CGU_SYS_IDIV_AXI        0x190
  80 #define CGU_SYS_IDIV_ETH        0x1A0
  81 #define CGU_SYS_IDIV_USB        0x1B0
  82 #define CGU_SYS_IDIV_SDIO       0x1C0
  83 #define CGU_SYS_IDIV_HDMI       0x1D0
  84 #define CGU_SYS_IDIV_GFX_CORE   0x1E0
  85 #define CGU_SYS_IDIV_GFX_DMA    0x1F0
  86 #define CGU_SYS_IDIV_GFX_CFG    0x200
  87 #define CGU_SYS_IDIV_DMAC_CORE  0x210
  88 #define CGU_SYS_IDIV_DMAC_CFG   0x220
  89 #define CGU_SYS_IDIV_SDIO_REF   0x230
  90 #define CGU_SYS_IDIV_SPI_REF    0x240
  91 #define CGU_SYS_IDIV_I2C_REF    0x250
  92 #define CGU_SYS_IDIV_UART_REF   0x260
  93 #define CGU_SYS_IDIV_EBI_REF    0x270
  94
  95 #define CGU_IDIV_MASK           0xFF /* All idiv have 8 significant bits */
  96
  97 #define CGU_ARC_PLL             0x0
  98 #define CGU_SYS_PLL             0x10
  99 #define CGU_DDR_PLL             0x20
 100 #define CGU_TUN_PLL             0x30
 101 #define CGU_HDMI_PLL            0x40
 102
 103 #define CGU_PLL_CTRL            0x000 /* ARC PLL control register */
 104 #define CGU_PLL_STATUS          0x004 /* ARC PLL status register */
 105 #define CGU_PLL_FMEAS           0x008 /* ARC PLL frequency measurement register */
 106 #define CGU_PLL_MON             0x00C /* ARC PLL monitor register */
 107
 108 #define CGU_PLL_CTRL_ODIV_SHIFT         2
 109 #define CGU_PLL_CTRL_IDIV_SHIFT         4
 110 #define CGU_PLL_CTRL_FBDIV_SHIFT        9
 111 #define CGU_PLL_CTRL_BAND_SHIFT         20
 112
 113 #define CGU_PLL_CTRL_ODIV_MASK          GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
 114 #define CGU_PLL_CTRL_IDIV_MASK          GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
 115 #define CGU_PLL_CTRL_FBDIV_MASK         GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
 116
 117 #define CGU_PLL_CTRL_PD                 BIT(0)
 118 #define CGU_PLL_CTRL_BYPASS             BIT(1)
 119
 120 #define CGU_PLL_STATUS_LOCK             BIT(0)
 121 #define CGU_PLL_STATUS_ERR              BIT(1)
 122
 123 #define HSDK_PLL_MAX_LOCK_TIME          100 /* 100 us */
 124
 125 #define CREG_CORE_IF_DIV                0x000 /* ARC CORE interface divider */
 126 #define CORE_IF_CLK_THRESHOLD_HZ        500000000
 127 #define CREG_CORE_IF_CLK_DIV_1          0x0
 128 #define CREG_CORE_IF_CLK_DIV_2          0x1
 129
 130 #define MIN_PLL_RATE                    100000000 /* 100 MHz */
 131 #define PARENT_RATE_33                  33333333 /* fixed clock - xtal */
 132 #define PARENT_RATE_27                  27000000 /* fixed clock - xtal */
 133 #define CGU_MAX_CLOCKS                  27
 134
 135 #define MAX_FREQ_VARIATIONS             6
 136
 137 struct hsdk_idiv_cfg {
 138         const u32 oft;
 139         const u8  val[MAX_FREQ_VARIATIONS];
 140 };
 141
 142 struct hsdk_div_full_cfg {
 143         const u32 clk_rate[MAX_FREQ_VARIATIONS];
 144         const u32 pll_rate[MAX_FREQ_VARIATIONS];
 145         const struct hsdk_idiv_cfg idiv[];
 146 };
 147
 148 static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
 149         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 150         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 151         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 152         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 153         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 154         { CGU_TUN_IDIV_TIMER,   { 12,   12,     12,     12,     15,     12 } },
 155         { /* last one */ }
 156         }
 157 };
 158
 159 static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
 160         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 161         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 162         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 163         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 164         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 165         { /* last one */ }
 166         }
 167 };
 168
 169 static const struct hsdk_div_full_cfg axi_clk_cfg = {
 170         { 200000000,    400000000,      600000000,      800000000 },
 171         { 800000000,    800000000,      600000000,      800000000 }, {
 172         { CGU_SYS_IDIV_APB,      { 4,   4,      3,      4 } },  /* APB */
 173         { CGU_SYS_IDIV_AXI,      { 4,   2,      1,      1 } },  /* AXI */
 174         { CGU_SYS_IDIV_ETH,      { 2,   2,      2,      2 } },  /* ETH */
 175         { CGU_SYS_IDIV_USB,      { 2,   2,      2,      2 } },  /* USB */
 176         { CGU_SYS_IDIV_SDIO,     { 2,   2,      2,      2 } },  /* SDIO */
 177         { CGU_SYS_IDIV_HDMI,     { 2,   2,      2,      2 } },  /* HDMI */
 178         { CGU_SYS_IDIV_GFX_CORE, { 1,   1,      1,      1 } },  /* GPU-CORE */
 179         { CGU_SYS_IDIV_GFX_DMA,  { 2,   2,      2,      2 } },  /* GPU-DMA */
 180         { CGU_SYS_IDIV_GFX_CFG,  { 4,   4,      3,      4 } },  /* GPU-CFG */
 181         { CGU_SYS_IDIV_DMAC_CORE,{ 2,   2,      2,      2 } },  /* DMAC-CORE */
 182         { CGU_SYS_IDIV_DMAC_CFG, { 4,   4,      3,      4 } },  /* DMAC-CFG */
 183         { CGU_SYS_IDIV_SDIO_REF, { 8,   8,      6,      8 } },  /* SDIO-REF */
 184         { CGU_SYS_IDIV_SPI_REF,  { 24,  24,     18,     24 } }, /* SPI-REF */
 185         { CGU_SYS_IDIV_I2C_REF,  { 4,   4,      3,      4 } },  /* I2C-REF */
 186         { CGU_SYS_IDIV_UART_REF, { 24,  24,     18,     24 } }, /* UART-REF */
 187         { CGU_SYS_IDIV_EBI_REF,  { 16,  16,     12,     16 } }, /* EBI-REF */
 188         { /* last one */ }
 189         }
 190 };
 191
 192 struct hsdk_pll_cfg {
 193         const u32 rate;
 194         const u8  idiv;
 195         const u8  fbdiv;
 196         const u8  odiv;
 197         const u8  band;
 198 };
 199
 200 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
 201         { 100000000,  0, 11, 3, 0 },
 202         { 125000000,  0, 14, 3, 0 },
 203         { 133000000,  0, 15, 3, 0 },
 204         { 150000000,  0, 17, 3, 0 },
 205         { 200000000,  1, 47, 3, 0 },
 206         { 233000000,  1, 27, 2, 0 },
 207         { 300000000,  1, 35, 2, 0 },
 208         { 333000000,  1, 39, 2, 0 },
 209         { 400000000,  1, 47, 2, 0 },
 210         { 500000000,  0, 14, 1, 0 },
 211         { 600000000,  0, 17, 1, 0 },
 212         { 700000000,  0, 20, 1, 0 },
 213         { 750000000,  1, 44, 1, 0 },
 214         { 800000000,  0, 23, 1, 0 },
 215         { 900000000,  1, 26, 0, 0 },
 216         { 1000000000, 1, 29, 0, 0 },
 217         { 1100000000, 1, 32, 0, 0 },
 218         { 1200000000, 1, 35, 0, 0 },
 219         { 1300000000, 1, 38, 0, 0 },
 220         { 1400000000, 1, 41, 0, 0 },
 221         { 1500000000, 1, 44, 0, 0 },
 222         { 1600000000, 1, 47, 0, 0 },
 223         {}
 224 };
 225
 226 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
 227         { 297000000,  0, 21, 2, 0 },
 228         { 540000000,  0, 19, 1, 0 },
 229         { 594000000,  0, 21, 1, 0 },
 230         {}
 231 };
 232
 233 struct hsdk_cgu_domain {
 234         /* PLLs registers */
 235         void __iomem *pll_regs;
 236         /* PLLs special registers */
 237         void __iomem *spec_regs;
 238         /* PLLs devdata */
 239         const struct hsdk_pll_devdata *pll;
 240
 241         /* Dividers registers */
 242         void __iomem *idiv_regs;
 243 };
 244
 245 struct hsdk_cgu_clk {
 246         const struct cgu_clk_map *map;
 247         /* CGU block register */
 248         void __iomem *cgu_regs;
 249         /* CREG block register */
 250         void __iomem *creg_regs;
 251
 252         /* The domain we are working with */
 253         struct hsdk_cgu_domain curr_domain;
 254 };
 255
 256 struct hsdk_pll_devdata {
 257         const u32 parent_rate;
 258         const struct hsdk_pll_cfg *const pll_cfg;
 259         const int (*const update_rate)(struct hsdk_cgu_clk *clk,
 260                                        unsigned long rate,
 261                                        const struct hsdk_pll_cfg *cfg);
 262 };
 263
 264 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
 265                                      const struct hsdk_pll_cfg *);
 266 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
 267                                      const struct hsdk_pll_cfg *);
 268
 269 static const struct hsdk_pll_devdata core_pll_dat = {
 270         .parent_rate = PARENT_RATE_33,
 271         .pll_cfg = asdt_pll_cfg,
 272         .update_rate = hsdk_pll_core_update_rate,
 273 };
 274
 275 static const struct hsdk_pll_devdata sdt_pll_dat = {
 276         .parent_rate = PARENT_RATE_33,
 277         .pll_cfg = asdt_pll_cfg,
 278         .update_rate = hsdk_pll_comm_update_rate,
 279 };
 280
 281 static const struct hsdk_pll_devdata hdmi_pll_dat = {
 282         .parent_rate = PARENT_RATE_27,
 283         .pll_cfg = hdmi_pll_cfg,
 284         .update_rate = hsdk_pll_comm_update_rate,
 285 };
 286
 287 static ulong idiv_set(struct clk *, ulong);
 288 static ulong cpu_clk_set(struct clk *, ulong);
 289 static ulong axi_clk_set(struct clk *, ulong);
 290 static ulong tun_hsdk_set(struct clk *, ulong);
 291 static ulong tun_h4xd_set(struct clk *, ulong);
 292 static ulong idiv_get(struct clk *);
 293 static int idiv_off(struct clk *);
 294 static ulong pll_set(struct clk *, ulong);
 295 static ulong pll_get(struct clk *);
 296
 297 struct cgu_clk_map {
 298         const u32 cgu_pll_oft;
 299         const u32 cgu_div_oft;
 300         const struct hsdk_pll_devdata *const pll_devdata;
 301         const ulong (*const get_rate)(struct clk *clk);
 302         const ulong (*const set_rate)(struct clk *clk, ulong rate);
 303         const int (*const disable)(struct clk *clk);
 304 };
 305
 306 static const struct cgu_clk_map hsdk_clk_map[] = {
 307         [CLK_ARC_PLL]        = { CGU_ARC_PLL,  0,                      &core_pll_dat, pll_get,  pll_set,      NULL     },
 308         [CLK_ARC]            = { CGU_ARC_PLL,  CGU_ARC_IDIV,           &core_pll_dat, idiv_get, cpu_clk_set,  idiv_off },
 309         [CLK_DDR_PLL]        = { CGU_DDR_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 310         [CLK_SYS_PLL]        = { CGU_SYS_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 311         [CLK_SYS_APB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_APB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 312         [CLK_SYS_AXI]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_AXI,       &sdt_pll_dat,  idiv_get, axi_clk_set,  idiv_off },
 313         [CLK_SYS_ETH]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_ETH,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 314         [CLK_SYS_USB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_USB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 315         [CLK_SYS_SDIO]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 316         [CLK_SYS_HDMI]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_HDMI,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 317         [CLK_SYS_GFX_CORE]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CORE,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 318         [CLK_SYS_GFX_DMA]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_DMA,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 319         [CLK_SYS_GFX_CFG]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CFG,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 320         [CLK_SYS_DMAC_CORE]  = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 321         [CLK_SYS_DMAC_CFG]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CFG,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 322         [CLK_SYS_SDIO_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 323         [CLK_SYS_SPI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_SPI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 324         [CLK_SYS_I2C_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_I2C_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 325         [CLK_SYS_UART_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_UART_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 326         [CLK_SYS_EBI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_EBI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 327         [CLK_TUN_PLL]        = { CGU_TUN_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 328         [CLK_TUN_TUN]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_TUN,       &sdt_pll_dat,  idiv_get, tun_hsdk_set, idiv_off },
 329         [CLK_TUN_ROM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_ROM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 330         [CLK_TUN_PWM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_PWM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 331         [CLK_TUN_TIMER]      = { /* missing in HSDK */ },
 332         [CLK_HDMI_PLL]       = { CGU_HDMI_PLL, 0,                      &hdmi_pll_dat, pll_get,  pll_set,      NULL     },
 333         [CLK_HDMI]           = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,      &hdmi_pll_dat, idiv_get, idiv_set,     idiv_off }
 334 };
 335
 336 static const struct cgu_clk_map hsdk_4xd_clk_map[] = {
 337         [CLK_ARC_PLL]        = { CGU_ARC_PLL,  0,                      &core_pll_dat, pll_get,  pll_set,      NULL     },
 338         [CLK_ARC]            = { CGU_ARC_PLL,  CGU_ARC_IDIV,           &core_pll_dat, idiv_get, cpu_clk_set,  idiv_off },
 339         [CLK_DDR_PLL]        = { CGU_DDR_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 340         [CLK_SYS_PLL]        = { CGU_SYS_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 341         [CLK_SYS_APB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_APB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 342         [CLK_SYS_AXI]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_AXI,       &sdt_pll_dat,  idiv_get, axi_clk_set,  idiv_off },
 343         [CLK_SYS_ETH]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_ETH,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 344         [CLK_SYS_USB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_USB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 345         [CLK_SYS_SDIO]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 346         [CLK_SYS_HDMI]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_HDMI,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 347         [CLK_SYS_GFX_CORE]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CORE,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 348         [CLK_SYS_GFX_DMA]    = { /* missing in HSDK-4xD */ },
 349         [CLK_SYS_GFX_CFG]    = { /* missing in HSDK-4xD */ },
 350         [CLK_SYS_DMAC_CORE]  = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 351         [CLK_SYS_DMAC_CFG]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CFG,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 352         [CLK_SYS_SDIO_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 353         [CLK_SYS_SPI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_SPI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 354         [CLK_SYS_I2C_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_I2C_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 355         [CLK_SYS_UART_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_UART_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 356         [CLK_SYS_EBI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_EBI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 357         [CLK_TUN_PLL]        = { CGU_TUN_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 358         [CLK_TUN_TUN]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_TUN,       &sdt_pll_dat,  idiv_get, tun_h4xd_set, idiv_off },
 359         [CLK_TUN_ROM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_ROM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 360         [CLK_TUN_PWM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_PWM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 361         [CLK_TUN_TIMER]      = { CGU_TUN_PLL,  CGU_TUN_IDIV_TIMER,     &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 362         [CLK_HDMI_PLL]       = { CGU_HDMI_PLL, 0,                      &hdmi_pll_dat, pll_get,  pll_set,      NULL     },
 363         [CLK_HDMI]           = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,      &hdmi_pll_dat, idiv_get, idiv_set,     idiv_off }
 364 };
 365
 366 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
 367 {
 368         iowrite32(val, clk->curr_domain.idiv_regs);
 369 }
 370
 371 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
 372 {
 373         return ioread32(clk->curr_domain.idiv_regs);
 374 }
 375
 376 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 377 {
 378         iowrite32(val, clk->curr_domain.pll_regs + reg);
 379 }
 380
 381 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
 382 {
 383         return ioread32(clk->curr_domain.pll_regs + reg);
 384 }
 385
 386 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 387 {
 388         iowrite32(val, clk->curr_domain.spec_regs + reg);
 389 }
 390
 391 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
 392 {
 393         return ioread32(clk->curr_domain.spec_regs + reg);
 394 }
 395
 396 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
 397                                     const struct hsdk_pll_cfg *cfg)
 398 {
 399         u32 val = 0;
 400
 401         /* Powerdown and Bypass bits should be cleared */
 402         val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
 403         val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
 404         val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
 405         val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
 406
 407         pr_debug("write configurarion: %#x\n", val);
 408
 409         hsdk_pll_write(clk, CGU_PLL_CTRL, val);
 410 }
 411
 412 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
 413 {
 414         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
 415 }
 416
 417 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
 418 {
 419         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
 420 }
 421
 422 static ulong pll_get(struct clk *sclk)
 423 {
 424         u32 val;
 425         u64 rate;
 426         u32 idiv, fbdiv, odiv;
 427         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 428         u32 parent_rate = clk->curr_domain.pll->parent_rate;
 429
 430         val = hsdk_pll_read(clk, CGU_PLL_CTRL);
 431
 432         pr_debug("current configurarion: %#x\n", val);
 433
 434         /* Check if PLL is bypassed */
 435         if (val & CGU_PLL_CTRL_BYPASS)
 436                 return parent_rate;
 437
 438         /* Check if PLL is disabled */
 439         if (val & CGU_PLL_CTRL_PD)
 440                 return 0;
 441
 442         /* input divider = reg.idiv + 1 */
 443         idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
 444         /* fb divider = 2*(reg.fbdiv + 1) */
 445         fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
 446         /* output divider = 2^(reg.odiv) */
 447         odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
 448
 449         rate = (u64)parent_rate * fbdiv;
 450         do_div(rate, idiv * odiv);
 451
 452         return rate;
 453 }
 454
 455 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
 456 {
 457         int i;
 458         unsigned long best_rate;
 459         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 460         const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
 461
 462         if (pll_cfg[0].rate == 0)
 463                 return -EINVAL;
 464
 465         best_rate = pll_cfg[0].rate;
 466
 467         for (i = 1; pll_cfg[i].rate != 0; i++) {
 468                 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
 469                         best_rate = pll_cfg[i].rate;
 470         }
 471
 472         pr_debug("chosen best rate: %lu\n", best_rate);
 473
 474         return best_rate;
 475 }
 476
 477 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
 478                                      unsigned long rate,
 479                                      const struct hsdk_pll_cfg *cfg)
 480 {
 481         hsdk_pll_set_cfg(clk, cfg);
 482
 483         /*
 484          * Wait until CGU relocks and check error status.
 485          * If after timeout CGU is unlocked yet return error.
 486          */
 487         udelay(HSDK_PLL_MAX_LOCK_TIME);
 488         if (!hsdk_pll_is_locked(clk))
 489                 return -ETIMEDOUT;
 490
 491         if (hsdk_pll_is_err(clk))
 492                 return -EINVAL;
 493
 494         return 0;
 495 }
 496
 497 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
 498                                      unsigned long rate,
 499                                      const struct hsdk_pll_cfg *cfg)
 500 {
 501         /*
 502          * When core clock exceeds 500MHz, the divider for the interface
 503          * clock must be programmed to div-by-2.
 504          */
 505         if (rate > CORE_IF_CLK_THRESHOLD_HZ)
 506                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
 507
 508         hsdk_pll_set_cfg(clk, cfg);
 509
 510         /*
 511          * Wait until CGU relocks and check error status.
 512          * If after timeout CGU is unlocked yet return error.
 513          */
 514         udelay(HSDK_PLL_MAX_LOCK_TIME);
 515         if (!hsdk_pll_is_locked(clk))
 516                 return -ETIMEDOUT;
 517
 518         if (hsdk_pll_is_err(clk))
 519                 return -EINVAL;
 520
 521         /*
 522          * Program divider to div-by-1 if we succesfuly set core clock below
 523          * 500MHz threshold.
 524          */
 525         if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
 526                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
 527
 528         return 0;
 529 }
 530
 531 static ulong pll_set(struct clk *sclk, ulong rate)
 532 {
 533         int i;
 534         unsigned long best_rate;
 535         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 536         const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
 537         const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
 538
 539         best_rate = hsdk_pll_round_rate(sclk, rate);
 540
 541         for (i = 0; pll_cfg[i].rate != 0; i++)
 542                 if (pll_cfg[i].rate == best_rate)
 543                         return pll->update_rate(clk, best_rate, &pll_cfg[i]);
 544
 545         pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
 546                pll->parent_rate);
 547
 548         return -EINVAL;
 549 }
 550
 551 static int idiv_off(struct clk *sclk)
 552 {
 553         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 554
 555         hsdk_idiv_write(clk, 0);
 556
 557         return 0;
 558 }
 559
 560 static ulong idiv_get(struct clk *sclk)
 561 {
 562         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 563         ulong parent_rate = pll_get(sclk);
 564         u32 div_factor = hsdk_idiv_read(clk);
 565
 566         div_factor &= CGU_IDIV_MASK;
 567
 568         pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
 569
 570         if (div_factor == 0)
 571                 return 0;
 572
 573         return parent_rate / div_factor;
 574 }
 575
 576 /* Special behavior: wen we set this clock we set both idiv and pll */
 577 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
 578 {
 579         ulong ret;
 580
 581         ret = pll_set(sclk, rate);
 582         idiv_set(sclk, rate);
 583
 584         return ret;
 585 }
 586
 587 /*
 588  * Special behavior:
 589  * when we set these clocks we set both PLL and all idiv dividers related to
 590  * this PLL domain.
 591  */
 592 static ulong common_div_clk_set(struct clk *sclk, ulong rate,
 593                                 const struct hsdk_div_full_cfg *cfg)
 594 {
 595         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 596         ulong pll_rate;
 597         int i, freq_idx = -1;
 598         ulong ret = 0;
 599
 600         pll_rate = pll_get(sclk);
 601
 602         for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
 603                 /* unused freq variations are filled with 0 */
 604                 if (!cfg->clk_rate[i])
 605                         break;
 606
 607                 if (cfg->clk_rate[i] == rate) {
 608                         freq_idx = i;
 609                         break;
 610                 }
 611         }
 612
 613         if (freq_idx < 0) {
 614                 pr_err("clk: invalid rate=%ld Hz\n", rate);
 615                 return -EINVAL;
 616         }
 617
 618         /* configure PLL before dividers */
 619         if (cfg->pll_rate[freq_idx] < pll_rate)
 620                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 621
 622         /* configure SYS dividers */
 623         for (i = 0; cfg->idiv[i].oft != 0; i++) {
 624                 clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
 625                 hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
 626         }
 627
 628         /* configure PLL after dividers */
 629         if (cfg->pll_rate[freq_idx] >= pll_rate)
 630                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 631
 632         return ret;
 633 }
 634
 635 static ulong axi_clk_set(struct clk *sclk, ulong rate)
 636 {
 637         return common_div_clk_set(sclk, rate, &axi_clk_cfg);
 638 }
 639
 640 static ulong tun_hsdk_set(struct clk *sclk, ulong rate)
 641 {
 642         return common_div_clk_set(sclk, rate, &hsdk_tun_clk_cfg);
 643 }
 644
 645 static ulong tun_h4xd_set(struct clk *sclk, ulong rate)
 646 {
 647         return common_div_clk_set(sclk, rate, &hsdk_4xd_tun_clk_cfg);
 648 }
 649
 650 static ulong idiv_set(struct clk *sclk, ulong rate)
 651 {
 652         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 653         ulong parent_rate = pll_get(sclk);
 654         u32 div_factor;
 655
 656         div_factor = parent_rate / rate;
 657         if (abs(rate - parent_rate / (div_factor + 1)) <=
 658             abs(rate - parent_rate / div_factor)) {
 659                 div_factor += 1;
 660         }
 661
 662         if (div_factor & ~CGU_IDIV_MASK) {
 663                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
 664                        rate, parent_rate, div_factor, CGU_IDIV_MASK);
 665
 666                 div_factor = CGU_IDIV_MASK;
 667         }
 668
 669         if (div_factor == 0) {
 670                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
 671                        rate, parent_rate, div_factor);
 672
 673                 div_factor = 1;
 674         }
 675
 676         hsdk_idiv_write(clk, div_factor);
 677
 678         return 0;
 679 }
 680
 681 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
 682 {
 683         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 684
 685         if (sclk->id >= CGU_MAX_CLOCKS)
 686                 return -EINVAL;
 687
 688         /* clocks missing in current map have their entry zeroed */
 689         if (!clk->map[sclk->id].pll_devdata)
 690                 return -EINVAL;
 691
 692         clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
 693         clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
 694         clk->curr_domain.spec_regs = clk->creg_regs;
 695         clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
 696
 697         return 0;
 698 }
 699
 700 static ulong hsdk_cgu_get_rate(struct clk *sclk)
 701 {
 702         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 703
 704         if (hsdk_prepare_clock_tree_branch(sclk))
 705                 return -EINVAL;
 706
 707         return clk->map[sclk->id].get_rate(sclk);
 708 }
 709
 710 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
 711 {
 712         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 713
 714         if (hsdk_prepare_clock_tree_branch(sclk))
 715                 return -EINVAL;
 716
 717         if (clk->map[sclk->id].set_rate)
 718                 return clk->map[sclk->id].set_rate(sclk, rate);
 719
 720         return -ENOTSUPP;
 721 }
 722
 723 static int hsdk_cgu_disable(struct clk *sclk)
 724 {
 725         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 726
 727         if (hsdk_prepare_clock_tree_branch(sclk))
 728                 return -EINVAL;
 729
 730         if (clk->map[sclk->id].disable)
 731                 return clk->map[sclk->id].disable(sclk);
 732
 733         return -ENOTSUPP;
 734 }
 735
 736 static const struct clk_ops hsdk_cgu_ops = {
 737         .set_rate = hsdk_cgu_set_rate,
 738         .get_rate = hsdk_cgu_get_rate,
 739         .disable = hsdk_cgu_disable,
 740 };
 741
 742 static int hsdk_cgu_clk_probe(struct udevice *dev)
 743 {
 744         struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
 745
 746         BUILD_BUG_ON(ARRAY_SIZE(hsdk_clk_map) != CGU_MAX_CLOCKS);
 747         BUILD_BUG_ON(ARRAY_SIZE(hsdk_4xd_clk_map) != CGU_MAX_CLOCKS);
 748
 749         /* Choose which clock map to use in runtime */
 750         if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF) == 0x52)
 751                 hsdk_clk->map = hsdk_clk_map;
 752         else
 753                 hsdk_clk->map = hsdk_4xd_clk_map;
 754
 755         hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
 756         if (!hsdk_clk->cgu_regs)
 757                 return -EINVAL;
 758
 759         hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
 760         if (!hsdk_clk->creg_regs)
 761                 return -EINVAL;
 762
 763         return 0;
 764 }
 765
 766 static const struct udevice_id hsdk_cgu_clk_id[] = {
 767         { .compatible = "snps,hsdk-cgu-clock" },
 768         { }
 769 };
 770
 771 U_BOOT_DRIVER(hsdk_cgu_clk) = {
 772         .name = "hsdk-cgu-clk",
 773         .id = UCLASS_CLK,
 774         .of_match = hsdk_cgu_clk_id,
 775         .probe = hsdk_cgu_clk_probe,
 776         .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
 777         .ops = &hsdk_cgu_ops,
 778 };