drivers/clk/clk-divider.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
   8  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   9  *
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <malloc.h>
  15 #include <clk-uclass.h>
  16 #include <dm/device.h>
  17 #include <dm/devres.h>
  18 #include <dm/uclass.h>
  19 #include <dm/lists.h>
  20 #include <dm/device-internal.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/err.h>
  23 #include <linux/log2.h>
  24 #include <div64.h>
  25 #include <clk.h>
  26 #include "clk.h"
  27
  28 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
  29
  30 static unsigned int _get_table_div(const struct clk_div_table *table,
  31                                    unsigned int val)
  32 {
  33         const struct clk_div_table *clkt;
  34
  35         for (clkt = table; clkt->div; clkt++)
  36                 if (clkt->val == val)
  37                         return clkt->div;
  38         return 0;
  39 }
  40
  41 static unsigned int _get_div(const struct clk_div_table *table,
  42                              unsigned int val, unsigned long flags, u8 width)
  43 {
  44         if (flags & CLK_DIVIDER_ONE_BASED)
  45                 return val;
  46         if (flags & CLK_DIVIDER_POWER_OF_TWO)
  47                 return 1 << val;
  48         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  49                 return val ? val : clk_div_mask(width) + 1;
  50         if (table)
  51                 return _get_table_div(table, val);
  52         return val + 1;
  53 }
  54
  55 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  56                                   unsigned int val,
  57                                   const struct clk_div_table *table,
  58                                   unsigned long flags, unsigned long width)
  59 {
  60         unsigned int div;
  61
  62         div = _get_div(table, val, flags, width);
  63         if (!div) {
  64                 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
  65                      "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  66                      clk_hw_get_name(hw));
  67                 return parent_rate;
  68         }
  69
  70         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
  71 }
  72
  73 static ulong clk_divider_recalc_rate(struct clk *clk)
  74 {
  75         struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
  76                         dev_get_clk_ptr(clk->dev) : clk);
  77         unsigned long parent_rate = clk_get_parent_rate(clk);
  78         unsigned int val;
  79
  80 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  81         val = divider->io_divider_val;
  82 #else
  83         val = readl(divider->reg);
  84 #endif
  85         val >>= divider->shift;
  86         val &= clk_div_mask(divider->width);
  87
  88         return divider_recalc_rate(clk, parent_rate, val, divider->table,
  89                                    divider->flags, divider->width);
  90 }
  91
  92 static bool _is_valid_table_div(const struct clk_div_table *table,
  93                                 unsigned int div)
  94 {
  95         const struct clk_div_table *clkt;
  96
  97         for (clkt = table; clkt->div; clkt++)
  98                 if (clkt->div == div)
  99                         return true;
 100         return false;
 101 }
 102
 103 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
 104                           unsigned long flags)
 105 {
 106         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 107                 return is_power_of_2(div);
 108         if (table)
 109                 return _is_valid_table_div(table, div);
 110         return true;
 111 }
 112
 113 static unsigned int _get_table_val(const struct clk_div_table *table,
 114                                    unsigned int div)
 115 {
 116         const struct clk_div_table *clkt;
 117
 118         for (clkt = table; clkt->div; clkt++)
 119                 if (clkt->div == div)
 120                         return clkt->val;
 121         return 0;
 122 }
 123
 124 static unsigned int _get_val(const struct clk_div_table *table,
 125                              unsigned int div, unsigned long flags, u8 width)
 126 {
 127         if (flags & CLK_DIVIDER_ONE_BASED)
 128                 return div;
 129         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 130                 return __ffs(div);
 131         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 132                 return (div == clk_div_mask(width) + 1) ? 0 : div;
 133         if (table)
 134                 return  _get_table_val(table, div);
 135         return div - 1;
 136 }
 137 int divider_get_val(unsigned long rate, unsigned long parent_rate,
 138                     const struct clk_div_table *table, u8 width,
 139                     unsigned long flags)
 140 {
 141         unsigned int div, value;
 142
 143         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 144
 145         if (!_is_valid_div(table, div, flags))
 146                 return -EINVAL;
 147
 148         value = _get_val(table, div, flags, width);
 149
 150         return min_t(unsigned int, value, clk_div_mask(width));
 151 }
 152
 153 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
 154 {
 155         struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
 156                         dev_get_clk_ptr(clk->dev) : clk);
 157         unsigned long parent_rate = clk_get_parent_rate(clk);
 158         int value;
 159         u32 val;
 160
 161         value = divider_get_val(rate, parent_rate, divider->table,
 162                                 divider->width, divider->flags);
 163         if (value < 0)
 164                 return value;
 165
 166         if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
 167                 val = clk_div_mask(divider->width) << (divider->shift + 16);
 168         } else {
 169                 val = readl(divider->reg);
 170                 val &= ~(clk_div_mask(divider->width) << divider->shift);
 171         }
 172         val |= (u32)value << divider->shift;
 173         writel(val, divider->reg);
 174
 175         return clk_get_rate(clk);
 176 }
 177
 178 const struct clk_ops clk_divider_ops = {
 179         .get_rate = clk_divider_recalc_rate,
 180         .set_rate = clk_divider_set_rate,
 181 };
 182
 183 static struct clk *_register_divider(struct device *dev, const char *name,
 184                 const char *parent_name, unsigned long flags,
 185                 void __iomem *reg, u8 shift, u8 width,
 186                 u8 clk_divider_flags, const struct clk_div_table *table)
 187 {
 188         struct clk_divider *div;
 189         struct clk *clk;
 190         int ret;
 191
 192         if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
 193                 if (width + shift > 16) {
 194                         pr_warn("divider value exceeds LOWORD field\n");
 195                         return ERR_PTR(-EINVAL);
 196                 }
 197         }
 198
 199         /* allocate the divider */
 200         div = kzalloc(sizeof(*div), GFP_KERNEL);
 201         if (!div)
 202                 return ERR_PTR(-ENOMEM);
 203
 204         /* struct clk_divider assignments */
 205         div->reg = reg;
 206         div->shift = shift;
 207         div->width = width;
 208         div->flags = clk_divider_flags;
 209         div->table = table;
 210 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
 211         div->io_divider_val = *(u32 *)reg;
 212 #endif
 213
 214         /* register the clock */
 215         clk = &div->clk;
 216
 217         ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
 218         if (ret) {
 219                 kfree(div);
 220                 return ERR_PTR(ret);
 221         }
 222
 223         return clk;
 224 }
 225
 226 struct clk *clk_register_divider(struct device *dev, const char *name,
 227                 const char *parent_name, unsigned long flags,
 228                 void __iomem *reg, u8 shift, u8 width,
 229                 u8 clk_divider_flags)
 230 {
 231         struct clk *clk;
 232
 233         clk =  _register_divider(dev, name, parent_name, flags, reg, shift,
 234                                  width, clk_divider_flags, NULL);
 235         if (IS_ERR(clk))
 236                 return ERR_CAST(clk);
 237         return clk;
 238 }
 239
 240 U_BOOT_DRIVER(ccf_clk_divider) = {
 241         .name   = UBOOT_DM_CLK_CCF_DIVIDER,
 242         .id     = UCLASS_CLK,
 243         .ops    = &clk_divider_ops,
 244         .flags = DM_FLAG_PRE_RELOC,
 245 };