1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
12 #define DIRUSFER 0x80010
13 #define DIRUCASER0 0x80040
14 #define DIRUSFMCR 0x80080
15 #define DIRUSFMAR 0x80084
17 #define DIRUSFMCR_SFID_SHIFT 16
19 /* Coherent cache agent interface */
20 #define CAIUIDR 0x00ffc
22 #define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15)
23 #define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16)
24 #define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0
25 #define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1
27 /* Coherent subsystem */
28 #define CSADSER0 0xff040
29 #define CSUIDR 0xffff8
32 #define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0)
33 #define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16)
34 #define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24)
36 #define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18)
38 #define DIR_REG_SZ 0x1000
39 #define CAIU_REG_SZ 0x1000
41 #define CCU_DIR_REG_ADDR(base, reg, dir) \
42 ((base) + (reg) + ((dir) * DIR_REG_SZ))
44 /* OCRAM firewall register */
45 #define OCRAM_FW_01 0x100204
46 #define OCRAM_SECURE_REGIONS 4
48 #define OCRAM_PRIVILEGED_MASK BIT(29)
49 #define OCRAM_SECURE_MASK BIT(30)
51 static void ncore_ccu_init_dirs(void __iomem *base)
56 u32 num_of_snoop_filters;
59 num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
60 num_of_snoop_filters =
61 CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
63 /* Initialize each snoop filter in each directory */
64 for (f = 0; f < num_of_snoop_filters; f++) {
65 reg = f << DIRUSFMCR_SFID_SHIFT;
66 for (i = 0; i < num_of_dirs; i++) {
67 /* Initialize all entries */
68 writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
70 /* Poll snoop filter maintenance operation active
73 ret = wait_for_bit_le32((const void *)
74 CCU_DIR_REG_ADDR(base,
76 BIT(0), false, 1000, false);
78 puts("CCU: Directory initialization failed!\n");
82 /* Enable snoop filter, a bit per snoop filter */
83 setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
89 static void ncore_ccu_init_coh_agent(void __iomem *base)
91 u32 num_of_coh_agent_intf;
97 num_of_coh_agent_intf =
98 CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
99 num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
101 for (i = 0; i < num_of_coh_agent_intf; i++) {
102 reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
103 if (CAIUIDR_CA_GET(reg)) {
104 /* Caching agent bit is enabled, enable caching agent
105 * snoop in each directory
107 for (dir = 0; dir < num_of_dirs; dir++) {
109 CCU_DIR_REG_ADDR(base, DIRUCASER0,
115 type = CAIUIDR_TYPE_GET(reg);
116 if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
117 type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
118 /* DVM support is enabled, enable ACE DVM snoop*/
119 setbits_le32((ulong)(base + CSADSER0),
125 static void ocram_bypass_firewall(void __iomem *base)
129 for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
130 clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
131 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
135 static int ncore_ccu_probe(struct udevice *dev)
140 addr = dev_read_addr(dev);
141 if (addr == FDT_ADDR_T_NONE)
144 base = (void __iomem *)addr;
146 ncore_ccu_init_dirs(base);
147 ncore_ccu_init_coh_agent(base);
148 ocram_bypass_firewall(base);
153 static const struct udevice_id ncore_ccu_ids[] = {
154 { .compatible = "arteris,ncore-ccu" },
158 U_BOOT_DRIVER(ncore_ccu) = {
161 .of_match = ncore_ccu_ids,
162 .probe = ncore_ccu_probe,
163 .flags = DM_FLAG_PRE_RELOC,