drivers/ata/sata_sil.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  * Author: Tang Yuantian <b29983@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <pci.h>
  12 #include <command.h>
  13 #include <asm/byteorder.h>
  14 #include <malloc.h>
  15 #include <asm/io.h>
  16 #include <fis.h>
  17 #include <sata.h>
  18 #include <libata.h>
  19 #include <sata.h>
  20 #include <linux/delay.h>
  21
  22 #if CONFIG_IS_ENABLED(BLK)
  23 #include <dm.h>
  24 #include <blk.h>
  25 #include <dm/device-internal.h>
  26 #endif
  27
  28 #include "sata_sil.h"
  29
  30 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  31
  32 /* just compatible ahci_ops */
  33 struct sil_ops {
  34         int *rev0;
  35         int *rev1;
  36         int (*scan)(struct udevice *dev);
  37 };
  38
  39 static struct sata_info sata_info;
  40
  41 static struct pci_device_id supported[] = {
  42         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
  43         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
  44         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
  45         {}
  46 };
  47
  48 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
  49 {
  50         printf("Status FIS dump:\n");
  51         printf("fis_type:               %02x\n", s->fis_type);
  52         printf("pm_port_i:              %02x\n", s->pm_port_i);
  53         printf("status:                 %02x\n", s->status);
  54         printf("error:                  %02x\n", s->error);
  55         printf("lba_low:                %02x\n", s->lba_low);
  56         printf("lba_mid:                %02x\n", s->lba_mid);
  57         printf("lba_high:               %02x\n", s->lba_high);
  58         printf("device:                 %02x\n", s->device);
  59         printf("lba_low_exp:            %02x\n", s->lba_low_exp);
  60         printf("lba_mid_exp:            %02x\n", s->lba_mid_exp);
  61         printf("lba_high_exp:           %02x\n", s->lba_high_exp);
  62         printf("res1:                   %02x\n", s->res1);
  63         printf("sector_count:           %02x\n", s->sector_count);
  64         printf("sector_count_exp:       %02x\n", s->sector_count_exp);
  65 }
  66
  67 static const char *sata_spd_string(unsigned int speed)
  68 {
  69         static const char * const spd_str[] = {
  70                 "1.5 Gbps",
  71                 "3.0 Gbps",
  72                 "6.0 Gbps",
  73         };
  74
  75         if ((speed - 1) > 2)
  76                 return "<unknown>";
  77
  78         return spd_str[speed - 1];
  79 }
  80
  81 static u32 ata_wait_register(void *reg, u32 mask,
  82                          u32 val, int timeout_msec)
  83 {
  84         u32 tmp;
  85
  86         tmp = readl(reg);
  87         while ((tmp & mask) == val && timeout_msec > 0) {
  88                 mdelay(1);
  89                 timeout_msec--;
  90                 tmp = readl(reg);
  91         }
  92
  93         return tmp;
  94 }
  95
  96 static void sil_config_port(void *port)
  97 {
  98         /* configure IRQ WoC */
  99         writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
 100
 101         /* zero error counters. */
 102         writew(0x8000, port + PORT_DECODE_ERR_THRESH);
 103         writew(0x8000, port + PORT_CRC_ERR_THRESH);
 104         writew(0x8000, port + PORT_HSHK_ERR_THRESH);
 105         writew(0x0000, port + PORT_DECODE_ERR_CNT);
 106         writew(0x0000, port + PORT_CRC_ERR_CNT);
 107         writew(0x0000, port + PORT_HSHK_ERR_CNT);
 108
 109         /* always use 64bit activation */
 110         writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
 111
 112         /* clear port multiplier enable and resume bits */
 113         writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
 114 }
 115
 116 static int sil_init_port(void *port)
 117 {
 118         u32 tmp;
 119
 120         writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
 121         ata_wait_register(port + PORT_CTRL_STAT,
 122                           PORT_CS_INIT, PORT_CS_INIT, 100);
 123         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 124                                 PORT_CS_RDY, 0, 100);
 125
 126         if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
 127                 return 1;
 128
 129         return 0;
 130 }
 131
 132 static void sil_read_fis(struct sil_sata *sata, int tag,
 133                          struct sata_fis_d2h *fis)
 134 {
 135         void *port = sata->port;
 136         struct sil_prb *prb;
 137         int i;
 138         u32 *src, *dst;
 139
 140         prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
 141         src = (u32 *)&prb->fis;
 142         dst = (u32 *)fis;
 143         for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
 144                 *dst++ = readl(src++);
 145 }
 146
 147 static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
 148                         int tag)
 149 {
 150         void *port = sata->port;
 151         u64 paddr = virt_to_bus(sata->devno, pcmd);
 152         u32 irq_mask, irq_stat;
 153         int rc;
 154
 155         writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
 156
 157         /* better to add momery barrior here */
 158         writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
 159         writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
 160
 161         irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
 162         irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
 163                         0, 10000);
 164
 165         /* clear IRQs */
 166         writel(irq_mask, port + PORT_IRQ_STAT);
 167         irq_stat >>= PORT_IRQ_RAW_SHIFT;
 168
 169         if (irq_stat & PORT_IRQ_COMPLETE)
 170                 rc = 0;
 171         else {
 172                 /* force port into known state */
 173                 sil_init_port(port);
 174                 if (irq_stat & PORT_IRQ_ERROR)
 175                         rc = 1; /* error */
 176                 else
 177                         rc = 2; /* busy */
 178         }
 179
 180         return rc;
 181 }
 182
 183 static int sil_cmd_set_feature(struct sil_sata *sata)
 184 {
 185         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 186         struct sata_fis_d2h fis;
 187         u8 udma_cap;
 188         int ret;
 189
 190         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 191         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 192         pcmd->prb.fis.pm_port_c = (1 << 7);
 193         pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
 194         pcmd->prb.fis.features = SETFEATURES_XFER;
 195
 196         /* First check the device capablity */
 197         udma_cap = (u8)(sata->udma & 0xff);
 198         debug("udma_cap %02x\n", udma_cap);
 199
 200         if (udma_cap == ATA_UDMA6)
 201                 pcmd->prb.fis.sector_count = XFER_UDMA_6;
 202         if (udma_cap == ATA_UDMA5)
 203                 pcmd->prb.fis.sector_count = XFER_UDMA_5;
 204         if (udma_cap == ATA_UDMA4)
 205                 pcmd->prb.fis.sector_count = XFER_UDMA_4;
 206         if (udma_cap == ATA_UDMA3)
 207                 pcmd->prb.fis.sector_count = XFER_UDMA_3;
 208
 209         ret = sil_exec_cmd(sata, pcmd, 0);
 210         if (ret) {
 211                 sil_read_fis(sata, 0, &fis);
 212                 printf("Err: exe cmd(0x%x).\n",
 213                                 readl(sata->port + PORT_SERROR));
 214                 sil_sata_dump_fis(&fis);
 215                 return 1;
 216         }
 217
 218         return 0;
 219 }
 220
 221 static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
 222 {
 223         if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 224                 sata->wcache = 1;
 225         if (ata_id_has_flush(id))
 226                 sata->flush = 1;
 227         if (ata_id_has_flush_ext(id))
 228                 sata->flush_ext = 1;
 229 }
 230
 231 static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
 232 {
 233 #ifdef CONFIG_LBA48
 234         /* Check if support LBA48 */
 235         if (ata_id_has_lba48(id)) {
 236                 sata->lba48 = 1;
 237                 debug("Device supports LBA48\n");
 238         } else {
 239                 debug("Device supports LBA28\n");
 240         }
 241 #endif
 242
 243         sil_sata_init_wcache(sata, id);
 244         sil_cmd_set_feature(sata);
 245 }
 246
 247 static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
 248 {
 249         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 250         struct sata_fis_d2h fis;
 251         int ret;
 252
 253         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 254         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 255         pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 256         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 257         pcmd->prb.fis.pm_port_c = (1 << 7);
 258         pcmd->prb.fis.command = ATA_CMD_ID_ATA;
 259         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
 260         pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
 261         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 262
 263         ret = sil_exec_cmd(sata, pcmd, 0);
 264         if (ret) {
 265                 sil_read_fis(sata, 0, &fis);
 266                 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
 267                 sil_sata_dump_fis(&fis);
 268                 return 1;
 269         }
 270         ata_swap_buf_le16(id, ATA_ID_WORDS);
 271
 272         return 0;
 273 }
 274
 275 static int sil_cmd_soft_reset(struct sil_sata *sata)
 276 {
 277         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 278         struct sata_fis_d2h fis;
 279         void *port = sata->port;
 280         int ret;
 281
 282         /* put the port into known state */
 283         if (sil_init_port(port)) {
 284                 printf("SRST: port %d not ready\n", sata->id);
 285                 return 1;
 286         }
 287
 288         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 289
 290         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
 291         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 292         pcmd->prb.fis.pm_port_c = 0xf;
 293
 294         ret = sil_exec_cmd(sata, &cmdb, 0);
 295         if (ret) {
 296                 sil_read_fis(sata, 0, &fis);
 297                 printf("SRST cmd error.\n");
 298                 sil_sata_dump_fis(&fis);
 299                 return 1;
 300         }
 301
 302         return 0;
 303 }
 304
 305 static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
 306                              u8 *buffer, int is_write)
 307 {
 308         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 309         struct sata_fis_d2h fis;
 310         u64 block;
 311         int ret;
 312
 313         block = (u64)start;
 314         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 315         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 316         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 317         pcmd->prb.fis.pm_port_c = (1 << 7);
 318         if (is_write) {
 319                 pcmd->prb.fis.command = ATA_CMD_WRITE;
 320                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 321         } else {
 322                 pcmd->prb.fis.command = ATA_CMD_READ;
 323                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 324         }
 325
 326         pcmd->prb.fis.device = ATA_LBA;
 327         pcmd->prb.fis.device |= (block >> 24) & 0xf;
 328         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 329         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 330         pcmd->prb.fis.lba_low = block & 0xff;
 331         pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
 332
 333         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 334         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 335         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 336
 337         ret = sil_exec_cmd(sata, pcmd, 0);
 338         if (ret) {
 339                 sil_read_fis(sata, 0, &fis);
 340                 printf("Err: rw cmd(0x%08x).\n",
 341                                 readl(sata->port + PORT_SERROR));
 342                 sil_sata_dump_fis(&fis);
 343                 return 1;
 344         }
 345
 346         return blkcnt;
 347 }
 348
 349 static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
 350                                  ulong blkcnt, u8 *buffer, int is_write)
 351 {
 352         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 353         struct sata_fis_d2h fis;
 354         u64 block;
 355         int ret;
 356
 357         block = (u64)start;
 358         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 359         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 360         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 361         pcmd->prb.fis.pm_port_c = (1 << 7);
 362         if (is_write) {
 363                 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
 364                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 365         } else {
 366                 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
 367                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 368         }
 369
 370         pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
 371         pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
 372         pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
 373         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 374         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 375         pcmd->prb.fis.lba_low = block & 0xff;
 376         pcmd->prb.fis.device = ATA_LBA;
 377         pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
 378         pcmd->prb.fis.sector_count = blkcnt & 0xff;
 379
 380         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 381         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 382         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 383
 384         ret = sil_exec_cmd(sata, pcmd, 0);
 385         if (ret) {
 386                 sil_read_fis(sata, 0, &fis);
 387                 printf("Err: rw ext cmd(0x%08x).\n",
 388                                 readl(sata->port + PORT_SERROR));
 389                 sil_sata_dump_fis(&fis);
 390                 return 1;
 391         }
 392
 393         return blkcnt;
 394 }
 395
 396 static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
 397                                lbaint_t blkcnt, const void *buffer,
 398                                int is_write)
 399 {
 400         ulong start, blks, max_blks;
 401         u8 *addr;
 402
 403         start = blknr;
 404         blks = blkcnt;
 405         addr = (u8 *)buffer;
 406
 407         max_blks = ATA_MAX_SECTORS;
 408         do {
 409                 if (blks > max_blks) {
 410                         sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
 411                         start += max_blks;
 412                         blks -= max_blks;
 413                         addr += ATA_SECT_SIZE * max_blks;
 414                 } else {
 415                         sil_sata_rw_cmd(sata, start, blks, addr, is_write);
 416                         start += blks;
 417                         blks = 0;
 418                         addr += ATA_SECT_SIZE * blks;
 419                 }
 420         } while (blks != 0);
 421
 422         return blkcnt;
 423 }
 424
 425 static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
 426                                lbaint_t blkcnt, const void *buffer,
 427                                int is_write)
 428 {
 429         ulong start, blks, max_blks;
 430         u8 *addr;
 431
 432         start = blknr;
 433         blks = blkcnt;
 434         addr = (u8 *)buffer;
 435
 436         max_blks = ATA_MAX_SECTORS_LBA48;
 437         do {
 438                 if (blks > max_blks) {
 439                         sil_sata_rw_cmd_ext(sata, start, max_blks,
 440                                             addr, is_write);
 441                         start += max_blks;
 442                         blks -= max_blks;
 443                         addr += ATA_SECT_SIZE * max_blks;
 444                 } else {
 445                         sil_sata_rw_cmd_ext(sata, start, blks,
 446                                             addr, is_write);
 447                         start += blks;
 448                         blks = 0;
 449                         addr += ATA_SECT_SIZE * blks;
 450                 }
 451         } while (blks != 0);
 452
 453         return blkcnt;
 454 }
 455
 456 static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
 457 {
 458         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 459
 460         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 461         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 462         pcmd->prb.fis.pm_port_c = (1 << 7);
 463         pcmd->prb.fis.command = ATA_CMD_FLUSH;
 464
 465         sil_exec_cmd(sata, pcmd, 0);
 466 }
 467
 468 static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
 469 {
 470         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 471
 472         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 473         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 474         pcmd->prb.fis.pm_port_c = (1 << 7);
 475         pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
 476
 477         sil_exec_cmd(sata, pcmd, 0);
 478 }
 479
 480 /*
 481  * SATA interface between low level driver and command layer
 482  */
 483 #if !CONFIG_IS_ENABLED(BLK)
 484 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
 485 {
 486         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 487 #else
 488 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 489                        void *buffer)
 490 {
 491         struct sil_sata_priv *priv = dev_get_platdata(dev);
 492         int port_number = priv->port_num;
 493         struct sil_sata *sata = priv->sil_sata_desc[port_number];
 494 #endif
 495         ulong rc;
 496
 497         if (sata->lba48)
 498                 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
 499         else
 500                 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
 501
 502         return rc;
 503 }
 504
 505 /*
 506  * SATA interface between low level driver and command layer
 507  */
 508 #if !CONFIG_IS_ENABLED(BLK)
 509 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
 510 {
 511         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 512 #else
 513 ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 514                  const void *buffer)
 515 {
 516         struct sil_sata_priv *priv = dev_get_platdata(dev);
 517         int port_number = priv->port_num;
 518         struct sil_sata *sata = priv->sil_sata_desc[port_number];
 519 #endif
 520         ulong rc;
 521
 522         if (sata->lba48) {
 523                 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
 524                 if (sata->wcache && sata->flush_ext)
 525                         sil_sata_cmd_flush_cache_ext(sata);
 526         } else {
 527                 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
 528                 if (sata->wcache && sata->flush)
 529                         sil_sata_cmd_flush_cache(sata);
 530         }
 531
 532         return rc;
 533 }
 534
 535 #if !CONFIG_IS_ENABLED(BLK)
 536 static int sil_init_sata(int dev)
 537 {
 538 #else
 539 static int sil_init_sata(struct udevice *uc_dev, int dev)
 540 {
 541         struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
 542 #endif
 543         struct sil_sata *sata;
 544         void *port;
 545         u32 tmp;
 546         int cnt;
 547
 548         printf("SATA#%d:\n", dev);
 549
 550         port = (void *)sata_info.iobase[1] +
 551                 PORT_REGS_SIZE * (dev - sata_info.portbase);
 552
 553         /* Initial PHY setting */
 554         writel(0x20c, port + PORT_PHY_CFG);
 555
 556         /* clear port RST */
 557         tmp = readl(port + PORT_CTRL_STAT);
 558         if (tmp & PORT_CS_PORT_RST) {
 559                 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
 560                 tmp = ata_wait_register(port + PORT_CTRL_STAT,
 561                                 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
 562                 if (tmp & PORT_CS_PORT_RST)
 563                         printf("Err: Failed to clear port RST\n");
 564         }
 565
 566         /* Check if device is present */
 567         for (cnt = 0; cnt < 100; cnt++) {
 568                 tmp = readl(port + PORT_SSTATUS);
 569                 if ((tmp & 0xF) == 0x3)
 570                         break;
 571                 mdelay(1);
 572         }
 573
 574         tmp = readl(port + PORT_SSTATUS);
 575         if ((tmp & 0xf) != 0x3) {
 576                 printf("        (No RDY)\n");
 577                 return 1;
 578         }
 579
 580         /* Wait for port ready */
 581         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 582                                 PORT_CS_RDY, PORT_CS_RDY, 100);
 583         if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
 584                 printf("%d port not ready.\n", dev);
 585                 return 1;
 586         }
 587
 588         /* configure port */
 589         sil_config_port(port);
 590
 591         /* Reset port */
 592         writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
 593         readl(port + PORT_CTRL_STAT);
 594         tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
 595                                 PORT_CS_DEV_RST, 100);
 596         if (tmp & PORT_CS_DEV_RST) {
 597                 printf("%d port reset failed.\n", dev);
 598                 return 1;
 599         }
 600
 601         sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
 602         if (!sata) {
 603                 printf("%d no memory.\n", dev);
 604                 return 1;
 605         }
 606         memset((void *)sata, 0, sizeof(struct sil_sata));
 607
 608         /* Save the private struct to block device struct */
 609 #if !CONFIG_IS_ENABLED(BLK)
 610         sata_dev_desc[dev].priv = (void *)sata;
 611 #else
 612         priv->sil_sata_desc[dev] = sata;
 613         priv->port_num = dev;
 614 #endif
 615         sata->id = dev;
 616         sata->port = port;
 617         sata->devno = sata_info.devno;
 618         sprintf(sata->name, "SATA#%d", dev);
 619         sil_cmd_soft_reset(sata);
 620         tmp = readl(port + PORT_SSTATUS);
 621         tmp = (tmp >> 4) & 0xf;
 622         printf("        (%s)\n", sata_spd_string(tmp));
 623
 624         return 0;
 625 }
 626
 627 #if !CONFIG_IS_ENABLED(BLK)
 628 /*
 629  * SATA interface between low level driver and command layer
 630  */
 631 int init_sata(int dev)
 632 {
 633         static int init_done, idx;
 634         pci_dev_t devno;
 635         u16 word;
 636
 637         if (init_done == 1 && dev < sata_info.maxport)
 638                 goto init_start;
 639
 640         init_done = 1;
 641
 642         /* Find PCI device(s) */
 643         devno = pci_find_devices(supported, idx++);
 644         if (devno == -1)
 645                 return 1;
 646
 647         pci_read_config_word(devno, PCI_DEVICE_ID, &word);
 648
 649         /* get the port count */
 650         word &= 0xf;
 651
 652         sata_info.portbase = 0;
 653         sata_info.maxport = sata_info.portbase + word;
 654         sata_info.devno = devno;
 655
 656         /* Read out all BARs */
 657         sata_info.iobase[0] = (ulong)pci_map_bar(devno,
 658                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 659         sata_info.iobase[1] = (ulong)pci_map_bar(devno,
 660                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 661
 662         /* mask out the unused bits */
 663         sata_info.iobase[0] &= 0xffffff80;
 664         sata_info.iobase[1] &= 0xfffffc00;
 665
 666         /* Enable Bus Mastering and memory region */
 667         pci_write_config_word(devno, PCI_COMMAND,
 668                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 669
 670         /* Check if mem accesses and Bus Mastering are enabled. */
 671         pci_read_config_word(devno, PCI_COMMAND, &word);
 672         if (!(word & PCI_COMMAND_MEMORY) ||
 673             (!(word & PCI_COMMAND_MASTER))) {
 674                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 675                 debug("PCI command: %04x\n", word);
 676                 return 1;
 677         }
 678
 679         /* GPIO off */
 680         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 681         /* clear global reset & mask interrupts during initialization */
 682         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 683
 684 init_start:
 685         return sil_init_sata(dev);
 686 }
 687
 688 int reset_sata(int dev)
 689 {
 690         return 0;
 691 }
 692
 693 /*
 694  * SATA interface between low level driver and command layer
 695  */
 696 int scan_sata(int dev)
 697 {
 698         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 699 #else
 700 static int scan_sata(struct udevice *blk_dev, int dev)
 701 {
 702         struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
 703         struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
 704         struct sil_sata *sata = priv->sil_sata_desc[dev];
 705 #endif
 706         unsigned char serial[ATA_ID_SERNO_LEN + 1];
 707         unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
 708         unsigned char product[ATA_ID_PROD_LEN + 1];
 709         u16 *id;
 710
 711         id = (u16 *)malloc(ATA_ID_WORDS * 2);
 712         if (!id) {
 713                 printf("Id malloc failed\n");
 714                 return 1;
 715         }
 716         sil_cmd_identify_device(sata, id);
 717
 718         sil_sata_set_feature_by_id(sata, id);
 719
 720         /* Serial number */
 721         ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 722
 723         /* Firmware version */
 724         ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 725
 726         /* Product model */
 727         ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 728
 729 #if !CONFIG_IS_ENABLED(BLK)
 730         memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
 731         memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
 732         memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
 733         /* Totoal sectors */
 734         sata_dev_desc[dev].lba = ata_id_n_sectors(id);
 735 #ifdef CONFIG_LBA48
 736         sata_dev_desc[dev].lba48 = sata->lba48;
 737 #endif
 738 #else
 739         memcpy(desc->product, serial, sizeof(serial));
 740         memcpy(desc->revision, firmware, sizeof(firmware));
 741         memcpy(desc->vendor, product, sizeof(product));
 742         desc->lba = ata_id_n_sectors(id);
 743 #ifdef CONFIG_LBA48
 744         desc->lba48 = sata->lba48;
 745 #endif
 746 #endif
 747
 748 #ifdef DEBUG
 749         ata_dump_id(id);
 750 #endif
 751         free((void *)id);
 752
 753         return 0;
 754 }
 755
 756 #if CONFIG_IS_ENABLED(BLK)
 757 static const struct blk_ops sata_sil_blk_ops = {
 758         .read   = sata_read,
 759         .write  = sata_write,
 760 };
 761
 762 U_BOOT_DRIVER(sata_sil_driver) = {
 763         .name = "sata_sil_blk",
 764         .id = UCLASS_BLK,
 765         .ops = &sata_sil_blk_ops,
 766         .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
 767 };
 768
 769 static int sil_unbind_device(struct udevice *dev)
 770 {
 771         int ret;
 772
 773         ret = device_remove(dev, DM_REMOVE_NORMAL);
 774         if (ret)
 775                 return ret;
 776
 777         ret = device_unbind(dev);
 778         if (ret)
 779                 return ret;
 780
 781         return 0;
 782 }
 783
 784 static int sil_pci_probe(struct udevice *dev)
 785 {
 786         struct udevice *blk;
 787         int failed_number;
 788         char sata_name[10];
 789         pci_dev_t devno;
 790         u16 word;
 791         int ret;
 792         int i;
 793
 794         failed_number = 0;
 795
 796         /* Get PCI device number */
 797         devno = dm_pci_get_bdf(dev);
 798         if (devno == -1)
 799                 return 1;
 800
 801         dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
 802
 803         /* get the port count */
 804         word &= 0xf;
 805
 806         sata_info.portbase = 0;
 807         sata_info.maxport = sata_info.portbase + word;
 808         sata_info.devno = devno;
 809
 810         /* Read out all BARs */
 811         sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
 812                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 813         sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
 814                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 815
 816         /* mask out the unused bits */
 817         sata_info.iobase[0] &= 0xffffff80;
 818         sata_info.iobase[1] &= 0xfffffc00;
 819
 820         /* Enable Bus Mastering and memory region */
 821         dm_pci_write_config16(dev, PCI_COMMAND,
 822                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 823
 824         /* Check if mem accesses and Bus Mastering are enabled. */
 825         dm_pci_read_config16(dev, PCI_COMMAND, &word);
 826         if (!(word & PCI_COMMAND_MEMORY) ||
 827             (!(word & PCI_COMMAND_MASTER))) {
 828                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 829                 debug("PCI command: %04x\n", word);
 830                 return 1;
 831         }
 832
 833         /* GPIO off */
 834         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 835         /* clear global reset & mask interrupts during initialization */
 836         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 837
 838         for (i = sata_info.portbase; i < sata_info.maxport; i++) {
 839                 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
 840                 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
 841                                          IF_TYPE_SATA, -1, 512, 0, &blk);
 842                 if (ret) {
 843                         debug("Can't create device\n");
 844                         return ret;
 845                 }
 846
 847                 ret = sil_init_sata(blk, i);
 848                 if (ret) {
 849                         ret = sil_unbind_device(blk);
 850                         if (ret)
 851                                 return ret;
 852
 853                         failed_number++;
 854                         continue;
 855                 }
 856
 857                 ret = scan_sata(blk, i);
 858                 if (ret) {
 859                         ret = sil_unbind_device(blk);
 860                         if (ret)
 861                                 return ret;
 862
 863                         failed_number++;
 864                         continue;
 865                 }
 866         }
 867
 868         if (failed_number == sata_info.maxport)
 869                 return -ENODEV;
 870         else
 871                 return 0;
 872 }
 873
 874 static int sil_pci_remove(struct udevice *dev)
 875 {
 876         int i;
 877         struct sil_sata *sata;
 878         struct sil_sata_priv *priv;
 879
 880         priv = dev_get_priv(dev);
 881
 882         for (i = sata_info.portbase; i < sata_info.maxport; i++) {
 883                 sata = priv->sil_sata_desc[i];
 884                 if (sata)
 885                         free(sata);
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int sata_sil_scan(struct udevice *dev)
 892 {
 893         /* Nothing to do here */
 894
 895         return 0;
 896 }
 897
 898 struct sil_ops sata_sil_ops = {
 899         .scan = sata_sil_scan,
 900 };
 901
 902 static const struct udevice_id sil_pci_ids[] = {
 903         { .compatible = "sil-pci-sample" },
 904         { }
 905 };
 906
 907 U_BOOT_DRIVER(sil_ahci_pci) = {
 908         .name   = "sil_ahci_pci",
 909         .id     = UCLASS_AHCI,
 910         .of_match = sil_pci_ids,
 911         .ops = &sata_sil_ops,
 912         .probe = sil_pci_probe,
 913         .remove = sil_pci_remove,
 914         .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
 915 };
 916
 917 U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
 918 #endif