1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Terry Lv <r65388@freescale.com>
11 #include <dwc_ahsata.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/sata.h>
21 #include <linux/bitops.h>
22 #include <linux/ctype.h>
23 #include <linux/errno.h>
24 #include "dwc_ahsata_priv.h"
26 struct sata_port_regs {
50 struct sata_host_regs {
79 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
80 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
82 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
84 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
86 return base + 0x100 + (port * 0x80);
89 static int waiting_for_cmd_completed(u8 *offset,
97 ((status = readl(offset)) & sign) && i < timeout_msec;
101 return (i < timeout_msec) ? 0 : -1;
104 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
106 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
108 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
109 writel(0x02060b14, &host_mmio->oobr);
114 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
116 u32 tmp, cap_save, num_ports;
117 int i, j, timeout = 1000;
118 struct sata_port_regs *port_mmio = NULL;
119 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
120 int clk = mxc_get_clock(MXC_SATA_CLK);
122 cap_save = readl(&host_mmio->cap);
123 cap_save |= SATA_HOST_CAP_SSS;
125 /* global controller reset */
126 tmp = readl(&host_mmio->ghc);
127 if ((tmp & SATA_HOST_GHC_HR) == 0)
128 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
130 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
134 debug("controller reset failed (0x%x)\n", tmp);
139 writel(clk / 1000, &host_mmio->timer1ms);
141 ahci_setup_oobr(uc_priv, 0);
143 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
144 writel(cap_save, &host_mmio->cap);
145 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
146 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
149 * Determine which Ports are implemented by the DWC_ahsata,
150 * by reading the PI register. This bit map value aids the
151 * software to determine how many Ports are available and
152 * which Port registers need to be initialized.
154 uc_priv->cap = readl(&host_mmio->cap);
155 uc_priv->port_map = readl(&host_mmio->pi);
157 /* Determine how many command slots the HBA supports */
158 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
160 debug("cap 0x%x port_map 0x%x n_ports %d\n",
161 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
163 for (i = 0; i < uc_priv->n_ports; i++) {
164 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
165 port_mmio = uc_priv->port[i].port_mmio;
167 /* Ensure that the DWC_ahsata is in idle state */
168 tmp = readl(&port_mmio->cmd);
171 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
172 * are all cleared, the Port is in an idle state.
174 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
175 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
178 * System software places a Port into the idle state by
179 * clearing P#CMD.ST and waiting for P#CMD.CR to return
182 tmp &= ~SATA_PORT_CMD_ST;
183 writel_with_flush(tmp, &port_mmio->cmd);
186 * spec says 500 msecs for each bit, so
187 * this is slightly incorrect.
192 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
197 debug("port reset failed (0x%x)\n", tmp);
203 tmp = readl(&port_mmio->cmd);
204 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
206 /* Wait for spin-up to finish */
208 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
212 debug("Spin-Up can't finish!\n");
216 for (j = 0; j < 100; ++j) {
218 tmp = readl(&port_mmio->ssts);
219 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
220 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
224 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
226 while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
230 debug("Can't find DIAG_X set!\n");
235 * For each implemented Port, clear the P#SERR
236 * register, by writing ones to each implemented\
239 tmp = readl(&port_mmio->serr);
240 debug("P#SERR 0x%x\n",
242 writel(tmp, &port_mmio->serr);
244 /* Ack any pending irq events for this port */
245 tmp = readl(&host_mmio->is);
246 debug("IS 0x%x\n", tmp);
248 writel(tmp, &host_mmio->is);
250 writel(1 << i, &host_mmio->is);
252 /* set irq mask (enables interrupts) */
253 writel(DEF_PORT_IRQ, &port_mmio->ie);
255 /* register linkup ports */
256 tmp = readl(&port_mmio->ssts);
257 debug("Port %d status: 0x%x\n", i, tmp);
258 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
259 uc_priv->link_port_map |= (0x01 << i);
262 tmp = readl(&host_mmio->ghc);
263 debug("GHC 0x%x\n", tmp);
264 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
265 tmp = readl(&host_mmio->ghc);
266 debug("GHC 0x%x\n", tmp);
271 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
273 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
274 u32 vers, cap, impl, speed;
278 vers = readl(&host_mmio->vs);
280 impl = uc_priv->port_map;
282 speed = (cap & SATA_HOST_CAP_ISS_MASK)
283 >> SATA_HOST_CAP_ISS_OFFSET;
293 printf("AHCI %02x%02x.%02x%02x "
294 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
299 ((cap >> 8) & 0x1f) + 1,
308 cap & (1 << 31) ? "64bit " : "",
309 cap & (1 << 30) ? "ncq " : "",
310 cap & (1 << 28) ? "ilck " : "",
311 cap & (1 << 27) ? "stag " : "",
312 cap & (1 << 26) ? "pm " : "",
313 cap & (1 << 25) ? "led " : "",
314 cap & (1 << 24) ? "clo " : "",
315 cap & (1 << 19) ? "nz " : "",
316 cap & (1 << 18) ? "only " : "",
317 cap & (1 << 17) ? "pmp " : "",
318 cap & (1 << 15) ? "pio " : "",
319 cap & (1 << 14) ? "slum " : "",
320 cap & (1 << 13) ? "part " : "");
323 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
324 unsigned char *buf, int buf_len)
326 struct ahci_ioports *pp = &uc_priv->port[port];
327 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
328 u32 sg_count, max_bytes;
331 max_bytes = MAX_DATA_BYTES_PER_SG;
332 sg_count = ((buf_len - 1) / max_bytes) + 1;
333 if (sg_count > AHCI_MAX_SG) {
334 printf("Error:Too much sg!\n");
338 for (i = 0; i < sg_count; i++) {
340 cpu_to_le32((u32)buf + i * max_bytes);
341 ahci_sg->addr_hi = 0;
342 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
347 buf_len -= max_bytes;
353 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
355 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
356 AHCI_CMD_SLOT_SZ * cmd_slot);
358 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
359 cmd_hdr->opts = cpu_to_le32(opts);
361 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
362 #ifdef CONFIG_PHYS_64BIT
363 pp->cmd_slot->tbl_addr_hi =
364 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
368 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
370 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
371 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
374 struct ahci_ioports *pp = &uc_priv->port[port];
375 struct sata_port_regs *port_mmio = pp->port_mmio;
377 int sg_count = 0, cmd_slot = 0;
379 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
380 if (32 == cmd_slot) {
381 printf("Can't find empty command slot!\n");
385 /* Check xfer length */
386 if (buf_len > MAX_BYTES_PER_TRANS) {
387 printf("Max transfer length is %dB\n\r",
388 MAX_BYTES_PER_TRANS);
392 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
394 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
395 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
398 flush_cache((ulong)buf, buf_len);
400 ahci_fill_cmd_slot(pp, cmd_slot, opts);
402 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
403 writel_with_flush(1 << cmd_slot, &port_mmio->ci);
405 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
407 printf("timeout exit!\n");
410 invalidate_dcache_range((int)(pp->cmd_slot),
411 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
412 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
413 pp->cmd_slot->status);
415 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
420 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
422 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
423 struct sata_fis_h2d *cfis = &h2d;
425 memset(cfis, 0, sizeof(struct sata_fis_h2d));
426 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
427 cfis->pm_port_c = 1 << 7;
428 cfis->command = ATA_CMD_SET_FEATURES;
429 cfis->features = SETFEATURES_XFER;
430 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
432 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
435 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
437 struct ahci_ioports *pp = &uc_priv->port[port];
438 struct sata_port_regs *port_mmio = pp->port_mmio;
441 int timeout = 10000000;
443 debug("Enter start port: %d\n", port);
444 port_status = readl(&port_mmio->ssts);
445 debug("Port %d status: %x\n", port, port_status);
446 if ((port_status & 0xf) != 0x03) {
447 printf("No Link on this port!\n");
451 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
453 printf("No mem for table!\n");
457 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
458 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
461 * First item in chunk of DMA memory: 32-slot command table,
462 * 32 bytes each in size
464 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
465 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
466 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
469 * Second item: Received-FIS area, 256-Byte aligned
472 mem += AHCI_RX_FIS_SZ;
475 * Third item: data area for storing a single command
476 * and its scatter-gather table
479 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
481 mem += AHCI_CMD_TBL_HDR;
483 writel_with_flush(0x00004444, &port_mmio->dmacr);
484 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
485 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
486 writel_with_flush(pp->rx_fis, &port_mmio->fb);
489 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
492 /* Wait device ready */
493 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
494 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
498 debug("Device not ready for BSY, DRQ and"
503 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
504 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
505 PORT_CMD_START, &port_mmio->cmd);
507 debug("Exit start port %d\n", port);
512 static void dwc_ahsata_print_info(struct blk_desc *pdev)
514 printf("SATA Device Info:\n\r");
515 printf("S/N: %s\n\rProduct model number: %s\n\r"
516 "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
517 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
520 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
522 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
523 struct sata_fis_h2d *cfis = &h2d;
524 u8 port = uc_priv->hard_port_no;
526 memset(cfis, 0, sizeof(struct sata_fis_h2d));
528 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
529 cfis->pm_port_c = 0x80; /* is command */
530 cfis->command = ATA_CMD_ID_ATA;
532 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
534 ata_swap_buf_le16(id, ATA_ID_WORDS);
537 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
539 uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
540 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
541 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
544 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
545 u32 blkcnt, u8 *buffer, int is_write)
547 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
548 struct sata_fis_h2d *cfis = &h2d;
549 u8 port = uc_priv->hard_port_no;
554 memset(cfis, 0, sizeof(struct sata_fis_h2d));
556 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
557 cfis->pm_port_c = 0x80; /* is command */
558 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
559 cfis->device = ATA_LBA;
561 cfis->device |= (block >> 24) & 0xf;
562 cfis->lba_high = (block >> 16) & 0xff;
563 cfis->lba_mid = (block >> 8) & 0xff;
564 cfis->lba_low = block & 0xff;
565 cfis->sector_count = (u8)(blkcnt & 0xff);
567 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
568 ATA_SECT_SIZE * blkcnt, is_write) > 0)
574 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
576 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
577 struct sata_fis_h2d *cfis = &h2d;
578 u8 port = uc_priv->hard_port_no;
580 memset(cfis, 0, sizeof(struct sata_fis_h2d));
582 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
583 cfis->pm_port_c = 0x80; /* is command */
584 cfis->command = ATA_CMD_FLUSH;
586 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
589 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
590 lbaint_t blkcnt, u8 *buffer, int is_write)
592 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
593 struct sata_fis_h2d *cfis = &h2d;
594 u8 port = uc_priv->hard_port_no;
599 memset(cfis, 0, sizeof(struct sata_fis_h2d));
601 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
602 cfis->pm_port_c = 0x80; /* is command */
604 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
607 cfis->lba_high_exp = (block >> 40) & 0xff;
608 cfis->lba_mid_exp = (block >> 32) & 0xff;
609 cfis->lba_low_exp = (block >> 24) & 0xff;
610 cfis->lba_high = (block >> 16) & 0xff;
611 cfis->lba_mid = (block >> 8) & 0xff;
612 cfis->lba_low = block & 0xff;
613 cfis->device = ATA_LBA;
614 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
615 cfis->sector_count = blkcnt & 0xff;
617 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
618 ATA_SECT_SIZE * blkcnt, is_write) > 0)
624 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
626 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
627 struct sata_fis_h2d *cfis = &h2d;
628 u8 port = uc_priv->hard_port_no;
630 memset(cfis, 0, sizeof(struct sata_fis_h2d));
632 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
633 cfis->pm_port_c = 0x80; /* is command */
634 cfis->command = ATA_CMD_FLUSH_EXT;
636 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
639 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
641 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
642 uc_priv->flags |= SATA_FLAG_WCACHE;
643 if (ata_id_has_flush(id))
644 uc_priv->flags |= SATA_FLAG_FLUSH;
645 if (ata_id_has_flush_ext(id))
646 uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
649 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
650 lbaint_t blkcnt, const void *buffer,
661 max_blks = ATA_MAX_SECTORS_LBA48;
664 if (blks > max_blks) {
665 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
671 addr += ATA_SECT_SIZE * max_blks;
673 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
678 addr += ATA_SECT_SIZE * blks;
685 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
686 lbaint_t blkcnt, const void *buffer,
697 max_blks = ATA_MAX_SECTORS;
699 if (blks > max_blks) {
700 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
706 addr += ATA_SECT_SIZE * max_blks;
708 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
713 addr += ATA_SECT_SIZE * blks;
720 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
725 linkmap = uc_priv->link_port_map;
728 printf("No port device detected!\n");
732 for (i = 0; i < uc_priv->n_ports; i++) {
733 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
734 if (ahci_port_start(uc_priv, (u8)i)) {
735 printf("Can not start port %d\n", i);
738 uc_priv->hard_port_no = i;
746 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
747 struct blk_desc *pdev)
749 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
750 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
751 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
752 u8 port = uc_priv->hard_port_no;
753 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
755 /* Identify device to get information */
756 dwc_ahsata_identify(uc_priv, id);
759 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
760 memcpy(pdev->product, serial, sizeof(serial));
762 /* Firmware version */
763 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
764 memcpy(pdev->revision, firmware, sizeof(firmware));
767 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
768 memcpy(pdev->vendor, product, sizeof(product));
771 pdev->lba = ata_id_n_sectors(id);
773 pdev->type = DEV_TYPE_HARDDISK;
774 pdev->blksz = ATA_SECT_SIZE;
777 /* Check if support LBA48 */
778 if (ata_id_has_lba48(id)) {
780 debug("Device support LBA48\n\r");
783 /* Get the NCQ queue depth from device */
784 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
785 uc_priv->flags |= ata_id_queue_depth(id);
787 /* Get the xfer mode from device */
788 dwc_ahsata_xfer_mode(uc_priv, id);
790 /* Get the write cache status from device */
791 dwc_ahsata_init_wcache(uc_priv, id);
793 /* Set the xfer mode to highest speed */
794 ahci_set_feature(uc_priv, port);
796 dwc_ahsata_print_info(pdev);
802 * SATA interface between low level driver and command layer
804 static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
805 struct blk_desc *desc, ulong blknr,
806 lbaint_t blkcnt, void *buffer)
811 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
814 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
820 static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
821 struct blk_desc *desc, ulong blknr,
822 lbaint_t blkcnt, const void *buffer)
825 u32 flags = uc_priv->flags;
828 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
830 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
831 dwc_ahsata_flush_cache_ext(uc_priv);
833 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
835 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
836 dwc_ahsata_flush_cache(uc_priv);
842 #if !CONFIG_IS_ENABLED(AHCI)
843 static int ahci_init_one(int pdev)
846 struct ahci_uc_priv *uc_priv = NULL;
848 uc_priv = malloc(sizeof(struct ahci_uc_priv));
852 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
855 uc_priv->host_flags = ATA_FLAG_SATA
861 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
863 /* initialize adapter */
864 rc = ahci_host_init(uc_priv);
868 ahci_print_info(uc_priv);
870 /* Save the uc_private struct to block device struct */
871 sata_dev_desc[pdev].priv = uc_priv;
881 int init_sata(int dev)
883 struct ahci_uc_priv *uc_priv = NULL;
885 #if defined(CONFIG_MX6)
886 if (!is_mx6dq() && !is_mx6dqp())
889 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
890 printf("The sata index %d is out of ranges\n\r", dev);
896 uc_priv = sata_dev_desc[dev].priv;
898 return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
901 int reset_sata(int dev)
903 struct ahci_uc_priv *uc_priv;
904 struct sata_host_regs *host_mmio;
906 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
907 printf("The sata index %d is out of ranges\n\r", dev);
911 uc_priv = sata_dev_desc[dev].priv;
913 /* not initialized, so nothing to reset */
916 host_mmio = uc_priv->mmio_base;
917 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
918 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
922 memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc));
927 int sata_port_status(int dev, int port)
929 struct sata_port_regs *port_mmio;
930 struct ahci_uc_priv *uc_priv = NULL;
932 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
935 if (sata_dev_desc[dev].priv == NULL)
938 uc_priv = sata_dev_desc[dev].priv;
939 port_mmio = uc_priv->port[port].port_mmio;
941 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
945 * SATA interface between low level driver and command layer
947 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
949 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
951 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
955 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
957 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
959 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
963 int scan_sata(int dev)
965 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
966 struct blk_desc *pdev = &sata_dev_desc[dev];
968 return dwc_ahsata_scan_common(uc_priv, pdev);
970 #endif /* CONFIG_IS_ENABLED(AHCI) */
972 #if CONFIG_IS_ENABLED(AHCI)
974 int dwc_ahsata_port_status(struct udevice *dev, int port)
976 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
977 struct sata_port_regs *port_mmio;
979 port_mmio = uc_priv->port[port].port_mmio;
980 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
983 int dwc_ahsata_bus_reset(struct udevice *dev)
985 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
986 struct sata_host_regs *host_mmio = uc_priv->mmio_base;
988 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
989 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
995 int dwc_ahsata_scan(struct udevice *dev)
997 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
998 struct blk_desc *desc;
1003 * Create only one block device and do detection
1004 * to make sure that there won't be a lot of
1005 * block devices created
1007 device_find_first_child(dev, &blk);
1009 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
1010 IF_TYPE_SATA, -1, 512, 0, &blk);
1012 debug("Can't create device\n");
1017 desc = dev_get_uclass_platdata(blk);
1018 ret = dwc_ahsata_scan_common(uc_priv, desc);
1020 debug("%s: Failed to scan bus\n", __func__);
1027 int dwc_ahsata_probe(struct udevice *dev)
1029 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1032 #if defined(CONFIG_MX6)
1035 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1036 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1037 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
1039 /* initialize adapter */
1040 ret = ahci_host_init(uc_priv);
1044 ahci_print_info(uc_priv);
1046 return dwc_ahci_start_ports(uc_priv);
1049 static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
1050 lbaint_t blkcnt, void *buffer)
1052 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1053 struct udevice *dev = dev_get_parent(blk);
1054 struct ahci_uc_priv *uc_priv;
1056 uc_priv = dev_get_uclass_priv(dev);
1057 return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
1060 static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
1061 lbaint_t blkcnt, const void *buffer)
1063 struct blk_desc *desc = dev_get_uclass_platdata(blk);
1064 struct udevice *dev = dev_get_parent(blk);
1065 struct ahci_uc_priv *uc_priv;
1067 uc_priv = dev_get_uclass_priv(dev);
1068 return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
1071 static const struct blk_ops dwc_ahsata_blk_ops = {
1072 .read = dwc_ahsata_read,
1073 .write = dwc_ahsata_write,
1076 U_BOOT_DRIVER(dwc_ahsata_blk) = {
1077 .name = "dwc_ahsata_blk",
1079 .ops = &dwc_ahsata_blk_ops,
1082 #if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
1083 struct ahci_ops dwc_ahsata_ahci_ops = {
1084 .port_status = dwc_ahsata_port_status,
1085 .reset = dwc_ahsata_bus_reset,
1086 .scan = dwc_ahsata_scan,
1089 static const struct udevice_id dwc_ahsata_ahci_ids[] = {
1090 { .compatible = "fsl,imx6q-ahci" },
1094 U_BOOT_DRIVER(dwc_ahsata_ahci) = {
1095 .name = "dwc_ahsata_ahci",
1097 .of_match = dwc_ahsata_ahci_ids,
1098 .ops = &dwc_ahsata_ahci_ops,
1099 .probe = dwc_ahsata_probe,