1 .. SPDX-License-Identifier: GPL-2.0+
6 The B4860QDS is a Freescale reference board that hosts the B4860 SoC
11 The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
12 StarCore and Power Architecture® cores. It targets the broadband wireless
13 infrastructure and builds upon the proven success of the existing multicore
14 DSPs and Power CPUs. It is designed to bolster the rapidly changing and
15 expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
17 The B4860 is a highly-integrated StarCore and Power Architecture processor that
20 * Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
21 clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
22 for wireless base station applications
23 * Four dual-thread e6500 Power Architecture processors organized in one
24 cluster-each core runs up to 1.8 GHz
25 * Two DDR3/3L controllers for high-speed, industry-standard memory interface
26 each runs at up to 1866.67 MHz
27 * MAPLE-B3 hardware acceleration-for forward error correction schemes including
28 Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
29 equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
30 FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
32 * CoreNet fabric that fully supports coherency using MESI protocol between the
33 e6500 cores, SC3900 FVP cores, memories and external interfaces.
34 CoreNet fabric interconnect runs at 667 MHz and supports coherent and
35 non-coherent out of order transactions with prioritization and bandwidth
36 allocation amongst CoreNet endpoints.
37 * Data Path Acceleration Architecture, which includes the following:
39 * Frame Manager (FMan), which supports in-line packet parsing and general
40 classification to enable policing and QoS-based packet distribution
41 * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
42 of queue management, task management, load distribution, flow ordering,
43 buffer management, and allocation tasks from the cores
44 * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
45 IPsec, SSL, and 802.16
46 * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
47 and outbound). Supports types 5, 6 (outbound only)
49 * Large internal cache memory with snooping and stashing capabilities for
50 bandwidth saving and high utilization of processor elements. The 9856-Kbyte
51 internal memory space includes the following:
53 * 32 Kbyte L1 ICache per e6500/SC3900 core
54 * 32 Kbyte L1 DCache per e6500/SC3900 core
55 * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
56 * 2048 Kbyte unified L2 cache for the e6500 cluster
57 * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
59 * Sixteen 10-GHz SerDes lanes serving:
61 * Two Serial RapidIO interfaces
62 * Each supports up to 4 lanes and a total of up to 8 lanes
64 * Up to 8-lanes Common Public Radio Interface (CPRI) controller for
65 glue-less antenna connection
66 * Two 10-Gbit Ethernet controllers (10GEC)
67 * Six 1G/2.5-Gbit Ethernet controllers for network communications
68 * PCI Express controller
71 * Various system peripherals
76 - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
77 ECC, 4 GB of memory in two ranks of 2 GB.
78 - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
79 ECC, 2 GB of memory. Single rank.
80 - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
82 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
84 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
85 B4860 UART port is available over USB-to-UART translator USB2SER or over
87 - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
88 copper connectors for Stand-alone mode and to the 1000Base-X over AMC
89 MicroTCA connector ports 0 and 2 for AMC mode.
90 - The B4860 configuration may be loaded from nine bits coded reset configuration
91 reset source. The RCW source is set by appropriate DIP-switches.
92 - 16-bit NOR Flash / PROMJet
93 - QIXIS 8-bit NOR Flash Emulator
96 - Long address I2C EEPROM
97 - Available debug interfaces are:
99 - On-board eCWTAP controller with ETH and USB I/F
100 - JTAG/COP 16-pin header for any external TAP controller
101 - External JTAG source over AMC to support B2B configuration
102 - 70-pin Aurora debug connector
104 - QIXIS (FPGA) logic:
105 - 2 KB internal memory space including
107 - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
108 DDRCLK1,2 and RTCCLK.
109 - Two 8T49N222A SerDes ref clock devices support two SerDes port clock
110 frequency - total four refclk, including CPRI clock scheme.
116 B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
117 and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
118 and reduced target frequencies.
120 Key differences between B4860 and B4420
121 ---------------------------------------
125 1. Less e6500 cores: 1 cluster with 2 e6500 cores
126 2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
129 5. 3 SGMII interfaces
133 B4860QDS Default Settings
134 -------------------------
141 SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
142 SW2 ON ON ON ON ON ON OFF OFF
143 SW3 OFF OFF OFF ON OFF OFF ON OFF
144 SW5 OFF OFF OFF OFF OFF OFF ON ON
148 - PCIe slots modes: All the PCIe devices work as Root Complex.
149 - Boot location: NOR flash.
151 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
152 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
166 B4420QDS Default Settings
167 -------------------------
174 SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
175 SW2 ON OFF ON OFF ON ON OFF OFF
176 SW3 OFF OFF OFF ON OFF OFF ON OFF
177 SW5 OFF OFF OFF OFF OFF OFF ON ON
181 - PCIe slots modes: All the PCIe devices work as Root Complex.
182 - Boot location: NOR flash.
184 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
185 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
199 Memory map on B4860QDS
200 ----------------------
201 The addresses in brackets are physical addresses.
203 ============= ============= =============== =======
204 Start Address End Address Description Size
205 ============= ============= =============== =======
206 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
207 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
208 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
209 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
210 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
211 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
212 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
213 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
214 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
215 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
216 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
217 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
218 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
219 0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
220 0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
221 0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
222 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
223 0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
224 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
225 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
226 0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
227 0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
228 0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
229 0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
230 ============= ============= =============== =======
232 Memory map on B4420QDS
233 ----------------------
234 The addresses in brackets are physical addresses.
236 ============= ============= =============== =======
237 Start Address End Address Description Size
238 ============= ============= =============== =======
239 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
240 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
241 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
242 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
243 0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
244 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
245 0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
246 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
247 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
248 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
249 0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
250 0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
251 0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
252 0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
253 0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
254 0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
255 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
256 0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
257 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
258 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
259 0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
260 0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
261 0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
262 ============= ============= =============== =======
264 NOR Flash memory Map on B4860 and B4420QDS
265 ------------------------------------------
267 ============= ============= ============================== =========
268 Start End Definition Size
269 ============= ============= ============================== =========
270 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
271 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
272 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
273 0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
274 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
275 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
276 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
277 0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
278 0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
279 0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
280 0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
281 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
282 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
283 0xEC000000 0xEC01FFFF RCW (current bank) 128KB
284 ============= ============= ============================== =========
286 Various Software configurations/environment variables/commands
287 --------------------------------------------------------------
288 The below commands apply to both B4860QDS and B4420QDS.
290 U-Boot environment variable hwconfig
291 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
293 The default hwconfig is:
297 hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
299 Note: For USB gadget set "dr_mode=peripheral"
304 fsl_fman_ucode_B4860_106_3_6.bin
306 Switching to alternate bank
307 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
309 Commands for switching to alternate bank.
311 1. To change from vbank0 to vbank2
315 => qixis_reset altbank (it will boot using vbank2)
317 2. To change from vbank2 to vbank0
321 => qixis reset (it will boot using vbank0)
323 To change personality of board
324 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
326 For changing personality from B4860 to B4420
329 2. Flash vbank2 with b4420 rcw and U-Boot
330 3. Give following commands to uboot prompt
334 => mw.b ffdf0040 0x30;
335 => mw.b ffdf0010 0x00;
336 => mw.b ffdf0062 0x02;
337 => mw.b ffdf0050 0x02;
338 => mw.b ffdf0010 0x30;
343 - Power off cycle will lead to default switch settings.
344 - 0xffdf0000 is the address of the QIXIS FPGA.
346 Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
347 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
349 To change from NOR to NAND boot give following command on uboot prompt
353 => mw.b ffdf0040 0x30
354 => mw.b ffdf0010 0x00
355 => mw.b 0xffdf0050 0x08
356 => mw.b 0xffdf0060 0x82
357 => mw.b ffdf0061 0x00
358 => mw.b ffdf0010 0x30
361 To change from NAND to NOR boot give following command on uboot prompt:
365 => mw.b ffdf0040 0x30
366 => mw.b ffdf0010 0x00
367 => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
368 => mw.b 0xffdf0060 0x12
369 => mw.b ffdf0061 0x01
370 => mw.b ffdf0010 0x30
375 - Power off cycle will lead to default switch settings.
376 - 0xffdf0000 is the address of the QIXIS FPGA.
378 Ethernet interfaces for B4860QDS
379 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
381 Serdes protocosl tested:
382 * 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
383 * 0x2a, 0xb2 (serdes1, serdes2)
385 When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
386 SGMII on SGMII riser card.
388 Under U-Boot these network interfaces are recognized as::
390 FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
392 On Linux the interfaces are renamed as::
399 RCW and Ethernet interfaces for B4420QDS
400 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
402 Serdes protocosl tested:
403 * 0x18, 0x9e (serdes1, serdes2)
405 Under U-Boot these network interfaces are recognized as::
407 FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
409 On Linux the interfaces are renamed as::
414 NAND boot with 2 Stage boot loader
415 ----------------------------------
416 PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
417 SPL further initialise DDR using SPD and environment variables and copy
418 U-Boot(768 KB) from flash to DDR.
419 Finally SPL transer control to U-Boot for futher booting.
421 SPL has following features:
422 - Executes within 256K
423 - No relocation required
425 Run time view of SPL framework during boot:
427 +----------------------------------------------+
429 +----------------------------------------------+
430 |Secure boot | 0xFFFC0000 (32KB) |
432 +----------------------------------------------+
433 |GD, BD | 0xFFFC8000 (4KB) |
434 +----------------------------------------------+
435 |ENV | 0xFFFC9000 (8KB) |
436 +----------------------------------------------+
437 |HEAP | 0xFFFCB000 (30KB) |
438 +----------------------------------------------+
439 |STACK | 0xFFFD8000 (22KB) |
440 +----------------------------------------------+
441 |U-Boot SPL | 0xFFFD8000 (160KB) |
442 +----------------------------------------------+
444 NAND Flash memory Map on B4860 and B4420QDS
445 -------------------------------------------
447 ============= ============= ============================= =====
448 Start End Definition Size
449 ============= ============= ============================= =====
450 0x000000 0x0FFFFF U-Boot 1MB
451 0x140000 0x15FFFF U-Boot env 128KB
452 0x1A0000 0x1BFFFF FMAN Ucode 128KB
453 ============= ============= ============================= =====