cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Zuepke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33
  34 .globl _start
  35 _start: b       reset
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction: .word undefined_instruction
  45 _software_interrupt:    .word software_interrupt
  46 _prefetch_abort:        .word prefetch_abort
  47 _data_abort:            .word data_abort
  48 _not_used:              .word not_used
  49 _irq:                   .word irq
  50 _fiq:                   .word fiq
  51
  52         .balignl 16,0xdeadbeef
  53
  54
  55 /*
  56  * Startup Code (reset vector)
  57  *
  58  * do important init only if we don't start from RAM!
  59  * - relocate armboot to ram
  60  * - setup stack
  61  * - jump to second stage
  62  */
  63
  64 _TEXT_BASE:
  65         .word   TEXT_BASE
  66
  67 .globl _armboot_start
  68 _armboot_start:
  69         .word _start
  70
  71 /*
  72  * These are defined in the board-specific linker script.
  73  */
  74 .globl _bss_start
  75 _bss_start:
  76         .word __bss_start
  77
  78 .globl _bss_end
  79 _bss_end:
  80         .word _end
  81
  82 #ifdef CONFIG_USE_IRQ
  83 /* IRQ stack memory (calculated at run-time) */
  84 .globl IRQ_STACK_START
  85 IRQ_STACK_START:
  86         .word   0x0badc0de
  87
  88 /* IRQ stack memory (calculated at run-time) */
  89 .globl FIQ_STACK_START
  90 FIQ_STACK_START:
  91         .word 0x0badc0de
  92 #endif
  93
  94
  95 /****************************************************************************/
  96 /*                                                                          */
  97 /* the actual reset code                                                    */
  98 /*                                                                          */
  99 /****************************************************************************/
 100
 101 reset:
 102         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 103         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 104         orr     r0,r0,#0x13
 105         msr     cpsr,r0
 106
 107         /*
 108          * we do sys-critical inits only at reboot,
 109          * not when booting from ram!
 110          */
 111 #ifdef CONFIG_INIT_CRITICAL
 112         bl      cpu_init_crit           /* we do sys-critical inits         */
 113 #endif
 114
 115 relocate:                               /* relocate U-Boot to RAM           */
 116         adr     r0, _start              /* r0 <- current position of code   */
 117         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 118         cmp     r0, r1                  /* don't reloc during debug         */
 119         beq     stack_setup
 120
 121         ldr     r2, _armboot_start
 122         ldr     r3, _bss_start
 123         sub     r2, r3, r2              /* r2 <- size of armboot            */
 124         add     r2, r0, r2              /* r2 <- source end address         */
 125
 126 copy_loop:
 127         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 128         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 129         cmp     r0, r2                  /* until source end addreee [r2]    */
 130         ble     copy_loop
 131
 132         /* Set up the stack                                                 */
 133 stack_setup:
 134         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 135         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 136         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 137 #ifdef CONFIG_USE_IRQ
 138         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 139 #endif
 140         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 141
 142 clear_bss:
 143         ldr     r0, _bss_start          /* find start of bss segment        */
 144         add     r0, r0, #4              /* start at first byte of bss       */
 145         ldr     r1, _bss_end            /* stop here                        */
 146         mov     r2, #0x00000000         /* clear                            */
 147
 148 clbss_l:str     r2, [r0]                /* clear loop...                    */
 149         add     r0, r0, #4
 150         cmp     r0, r1
 151         bne     clbss_l
 152
 153         ldr     pc, _start_armboot
 154
 155 _start_armboot: .word start_armboot
 156
 157
 158 /****************************************************************************/
 159 /*                                                                          */
 160 /* CPU_init_critical registers                                              */
 161 /*                                                                          */
 162 /* - setup important registers                                              */
 163 /* - setup memory timing                                                    */
 164 /*                                                                          */
 165 /****************************************************************************/
 166
 167 /* Interrupt-Controller base address                                        */
 168 IC_BASE:           .word           0x40d00000
 169 #define ICMR    0x04
 170
 171 /* Reset-Controller */
 172 RST_BASE:       .word   0x40f00030
 173 #define RCSR    0x00
 174
 175 /* Operating System Timer */
 176 OSTIMER_BASE:   .word   0x40a00000
 177 #define OSMR3   0x0C
 178 #define OSCR    0x10
 179 #define OWER    0x18
 180 #define OIER    0x1C
 181
 182 /* Clock Manager Registers                                                  */
 183 #ifdef CFG_CPUSPEED
 184 CC_BASE:        .word   0x41300000
 185 #define CCCR    0x00
 186 cpuspeed:       .word   CFG_CPUSPEED
 187 #else
 188 #error "You have to define CFG_CPUSPEED!!"
 189 #endif
 190
 191
 192         /* RS: ???                                                          */
 193         .macro CPWAIT
 194         mrc  p15,0,r0,c2,c0,0
 195         mov  r0,r0
 196         sub  pc,pc,#4
 197         .endm
 198
 199
 200 cpu_init_crit:
 201
 202         /* mask all IRQs                                                    */
 203         ldr     r0, IC_BASE
 204         mov     r1, #0x00
 205         str     r1, [r0, #ICMR]
 206
 207 #if defined(CFG_CPUSPEED)
 208
 209         /* set clock speed */
 210         ldr     r0, CC_BASE
 211         ldr     r1, cpuspeed
 212         str     r1, [r0, #CCCR]
 213         mov     r0, #2
 214         mcr     p14, 0, r0, c6, c0, 0
 215
 216 setspeed_done:
 217 #endif
 218
 219         /*
 220          * before relocating, we have to setup RAM timing
 221          * because memory timing is board-dependend, you will
 222          * find a memsetup.S in your board directory.
 223          */
 224         mov     ip,     lr
 225         bl      memsetup
 226         mov     lr,     ip
 227
 228         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 229
 230         ldr     r0, =0x2001             /* enable access to all coproc.     */
 231         mcr     p15, 0, r0, c15, c1, 0
 232         CPWAIT
 233
 234         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 235         CPWAIT
 236
 237         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 238         CPWAIT
 239
 240         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 241         CPWAIT
 242
 243         /* Enable the Icache                                                */
 244 /*
 245         mrc     p15, 0, r0, c1, c0, 0
 246         orr     r0, r0, #0x1800
 247         mcr     p15, 0, r0, c1, c0, 0
 248         CPWAIT
 249 */
 250         mov     pc, lr
 251
 252
 253 /****************************************************************************/
 254 /*                                                                          */
 255 /* Interrupt handling                                                       */
 256 /*                                                                          */
 257 /****************************************************************************/
 258
 259 /* IRQ stack frame                                                          */
 260
 261 #define S_FRAME_SIZE    72
 262
 263 #define S_OLD_R0        68
 264 #define S_PSR           64
 265 #define S_PC            60
 266 #define S_LR            56
 267 #define S_SP            52
 268
 269 #define S_IP            48
 270 #define S_FP            44
 271 #define S_R10           40
 272 #define S_R9            36
 273 #define S_R8            32
 274 #define S_R7            28
 275 #define S_R6            24
 276 #define S_R5            20
 277 #define S_R4            16
 278 #define S_R3            12
 279 #define S_R2            8
 280 #define S_R1            4
 281 #define S_R0            0
 282
 283 #define MODE_SVC 0x13
 284
 285         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 286
 287         .macro  bad_save_user_regs
 288         sub     sp, sp, #S_FRAME_SIZE
 289         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 290         add     r8, sp, #S_PC
 291
 292         ldr     r2, _armboot_start
 293         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 294         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 295         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 296         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 297
 298         add     r5, sp, #S_SP
 299         mov     r1, lr
 300         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 301         mov     r0, sp
 302         .endm
 303
 304
 305         /* use irq_save_user_regs / irq_restore_user_regs for                */
 306         /* IRQ/FIQ handling                                                  */
 307
 308         .macro  irq_save_user_regs
 309         sub     sp, sp, #S_FRAME_SIZE
 310         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 311         add     r8, sp, #S_PC
 312         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 313         str     lr, [r8, #0]                    /* Save calling PC           */
 314         mrs     r6, spsr
 315         str     r6, [r8, #4]                    /* Save CPSR                 */
 316         str     r0, [r8, #8]                    /* Save OLD_R0               */
 317         mov     r0, sp
 318         .endm
 319
 320         .macro  irq_restore_user_regs
 321         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 322         mov     r0, r0
 323         ldr     lr, [sp, #S_PC]                 @ Get PC
 324         add     sp, sp, #S_FRAME_SIZE
 325         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 326         .endm
 327
 328         .macro get_bad_stack
 329         ldr     r13, _armboot_start             @ setup our mode stack
 330         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 331         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 332
 333         str     lr, [r13]                       @ save caller lr / spsr
 334         mrs     lr, spsr
 335         str     lr, [r13, #4]
 336
 337         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 338         msr     spsr_c, r13
 339         mov     lr, pc
 340         movs    pc, lr
 341         .endm
 342
 343         .macro get_irq_stack                    @ setup IRQ stack
 344         ldr     sp, IRQ_STACK_START
 345         .endm
 346
 347         .macro get_fiq_stack                    @ setup FIQ stack
 348         ldr     sp, FIQ_STACK_START
 349         .endm
 350
 351
 352 /****************************************************************************/
 353 /*                                                                          */
 354 /* exception handlers                                                       */
 355 /*                                                                          */
 356 /****************************************************************************/
 357
 358         .align  5
 359 undefined_instruction:
 360         get_bad_stack
 361         bad_save_user_regs
 362         bl      do_undefined_instruction
 363
 364         .align  5
 365 software_interrupt:
 366         get_bad_stack
 367         bad_save_user_regs
 368         bl      do_software_interrupt
 369
 370         .align  5
 371 prefetch_abort:
 372         get_bad_stack
 373         bad_save_user_regs
 374         bl      do_prefetch_abort
 375
 376         .align  5
 377 data_abort:
 378         get_bad_stack
 379         bad_save_user_regs
 380         bl      do_data_abort
 381
 382         .align  5
 383 not_used:
 384         get_bad_stack
 385         bad_save_user_regs
 386         bl      do_not_used
 387
 388 #ifdef CONFIG_USE_IRQ
 389
 390         .align  5
 391 irq:
 392         get_irq_stack
 393         irq_save_user_regs
 394         bl      do_irq
 395         irq_restore_user_regs
 396
 397         .align  5
 398 fiq:
 399         get_fiq_stack
 400         irq_save_user_regs              /* someone ought to write a more    */
 401         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 402         irq_restore_user_regs
 403
 404 #else
 405
 406         .align  5
 407 irq:
 408         get_bad_stack
 409         bad_save_user_regs
 410         bl      do_irq
 411
 412         .align  5
 413 fiq:
 414         get_bad_stack
 415         bad_save_user_regs
 416         bl      do_fiq
 417
 418 #endif
 419
 420 /****************************************************************************/
 421 /*                                                                          */
 422 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 423 /* perform a watchdog timeout for a soft reset.                             */
 424 /*                                                                          */
 425 /****************************************************************************/
 426
 427         .align  5
 428 .globl reset_cpu
 429
 430         /* FIXME: this code is PXA250 specific. How is this handled on      */
 431         /*        other XScale processors?                                  */
 432
 433 reset_cpu:
 434
 435         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 436
 437         ldr     r0, OSTIMER_BASE
 438         ldr     r1, [r0, #OWER]
 439         orr     r1, r1, #0x0001                 /* bit0: WME                */
 440         str     r1, [r0, #OWER]
 441
 442         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 443         /* the match register as well.                                      */
 444
 445         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 446         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 447         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 448         str     r1, [r0, #OSMR3]
 449
 450 reset_endless:
 451
 452         b       reset_endless