cpu/pxa/start.S

   1 /*
   2  *  armboot - Startup Code for XScale
   3  *
   4  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   5  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   6  *  Copyright (C) 2000  Wolfgang Denk <wd@denx.de>
   7  *  Copyright (C) 2001  Alex Zuepke <azu@sysgo.de>
   8  *  Copyright (C) 2002  Kyle Harris <kharris@nexus-tech.net>
   9  *  Copyright (C) 2003  Robert Schwebel <r.schwebel@pengutronix.de>
  10  *  Copyright (C) 2003  Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <config.h>
  32 #include <version.h>
  33 #include <asm/arch/pxa-regs.h>
  34
  35 .globl _start
  36 _start: b       reset
  37         ldr     pc, _undefined_instruction
  38         ldr     pc, _software_interrupt
  39         ldr     pc, _prefetch_abort
  40         ldr     pc, _data_abort
  41         ldr     pc, _not_used
  42         ldr     pc, _irq
  43         ldr     pc, _fiq
  44
  45 _undefined_instruction: .word undefined_instruction
  46 _software_interrupt:    .word software_interrupt
  47 _prefetch_abort:        .word prefetch_abort
  48 _data_abort:            .word data_abort
  49 _not_used:              .word not_used
  50 _irq:                   .word irq
  51 _fiq:                   .word fiq
  52
  53         .balignl 16,0xdeadbeef
  54
  55
  56 /*
  57  * Startup Code (reset vector)
  58  *
  59  * do important init only if we don't start from RAM!
  60  * - relocate armboot to ram
  61  * - setup stack
  62  * - jump to second stage
  63  */
  64
  65 _TEXT_BASE:
  66         .word   TEXT_BASE
  67
  68 .globl _armboot_start
  69 _armboot_start:
  70         .word _start
  71
  72 /*
  73  * These are defined in the board-specific linker script.
  74  */
  75 .globl _bss_start
  76 _bss_start:
  77         .word __bss_start
  78
  79 .globl _bss_end
  80 _bss_end:
  81         .word _end
  82
  83 #ifdef CONFIG_USE_IRQ
  84 /* IRQ stack memory (calculated at run-time) */
  85 .globl IRQ_STACK_START
  86 IRQ_STACK_START:
  87         .word   0x0badc0de
  88
  89 /* IRQ stack memory (calculated at run-time) */
  90 .globl FIQ_STACK_START
  91 FIQ_STACK_START:
  92         .word 0x0badc0de
  93 #endif
  94
  95
  96 /****************************************************************************/
  97 /*                                                                          */
  98 /* the actual reset code                                                    */
  99 /*                                                                          */
 100 /****************************************************************************/
 101
 102 reset:
 103         mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 104         bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 105         orr     r0,r0,#0x13
 106         msr     cpsr,r0
 107
 108         /*
 109          * we do sys-critical inits only at reboot,
 110          * not when booting from ram!
 111          */
 112 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 113         bl      cpu_init_crit           /* we do sys-critical inits         */
 114 #endif
 115
 116 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 117 relocate:                               /* relocate U-Boot to RAM           */
 118         adr     r0, _start              /* r0 <- current position of code   */
 119         ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 120         cmp     r0, r1                  /* don't reloc during debug         */
 121         beq     stack_setup
 122
 123         ldr     r2, _armboot_start
 124         ldr     r3, _bss_start
 125         sub     r2, r3, r2              /* r2 <- size of armboot            */
 126         add     r2, r0, r2              /* r2 <- source end address         */
 127
 128 copy_loop:
 129         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 130         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 131         cmp     r0, r2                  /* until source end addreee [r2]    */
 132         ble     copy_loop
 133 #endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 134
 135         /* Set up the stack                                                 */
 136 stack_setup:
 137         ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 138         sub     r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
 139         sub     r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
 140 #ifdef CONFIG_USE_IRQ
 141         sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 142 #endif
 143         sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 144
 145 clear_bss:
 146         ldr     r0, _bss_start          /* find start of bss segment        */
 147         ldr     r1, _bss_end            /* stop here                        */
 148         mov     r2, #0x00000000         /* clear                            */
 149
 150 clbss_l:str     r2, [r0]                /* clear loop...                    */
 151         add     r0, r0, #4
 152         cmp     r0, r1
 153         ble     clbss_l
 154
 155         ldr     pc, _start_armboot
 156
 157 _start_armboot: .word start_armboot
 158
 159
 160 /****************************************************************************/
 161 /*                                                                          */
 162 /* CPU_init_critical registers                                              */
 163 /*                                                                          */
 164 /* - setup important registers                                              */
 165 /* - setup memory timing                                                    */
 166 /*                                                                          */
 167 /****************************************************************************/
 168
 169 /* Interrupt-Controller base address                                        */
 170 IC_BASE:           .word           0x40d00000
 171 #define ICMR    0x04
 172
 173 /* Reset-Controller */
 174 RST_BASE:       .word   0x40f00030
 175 #define RCSR    0x00
 176
 177 /* Operating System Timer */
 178 OSTIMER_BASE:   .word   0x40a00000
 179 #define OSMR3   0x0C
 180 #define OSCR    0x10
 181 #define OWER    0x18
 182 #define OIER    0x1C
 183
 184 /* Clock Manager Registers                                                  */
 185 #ifdef CFG_CPUSPEED
 186 CC_BASE:        .word   0x41300000
 187 #define CCCR    0x00
 188 cpuspeed:       .word   CFG_CPUSPEED
 189 #else
 190 #error "You have to define CFG_CPUSPEED!!"
 191 #endif
 192
 193
 194         /* takes care the CP15 update has taken place */
 195         .macro CPWAIT reg
 196         mrc  p15,0,\reg,c2,c0,0
 197         mov  \reg,\reg
 198         sub  pc,pc,#4
 199         .endm
 200
 201
 202 cpu_init_crit:
 203
 204         /* mask all IRQs                                                    */
 205 #ifndef CONFIG_CPU_MONAHANS
 206
 207         ldr     r0, IC_BASE
 208         mov     r1, #0x00
 209         str     r1, [r0, #ICMR]
 210 #else
 211         /* Step 1 - Enable CP6 permission */
 212         mrc     p15, 0, r1, c15, c1, 0  @ read CPAR
 213         orr     r1, r1, #0x40
 214                 mcr     p15, 0, r1, c15, c1, 0
 215         CPWAIT  r1
 216
 217         /* Step 2 - Mask ICMR & ICMR2 */
 218         mov     r1, #0
 219         mcr     p6, 0, r1, c1, c0, 0    @ ICMR
 220         mcr     p6, 0, r1, c7, c0, 0    @ ICMR2
 221
 222         /* turn off all clocks but the ones we will definitly require */
 223         ldr     r1, =CKENA
 224         ldr     r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
 225         str     r2, [r1]
 226         ldr     r1, =CKENB
 227         ldr     r2, =(CKENB_6_IRQ)
 228         str     r2, [r1]
 229
 230 #endif
 231
 232 #ifndef CONFIG_CPU_MONAHANS
 233 #ifdef CFG_CPUSPEED
 234
 235         /* set clock speed tbd@mk: required for monahans? */
 236         ldr     r0, CC_BASE
 237         ldr     r1, cpuspeed
 238         str     r1, [r0, #CCCR]
 239         mov     r0, #2
 240         mcr     p14, 0, r0, c6, c0, 0
 241
 242 setspeed_done:
 243
 244 #endif /* CFG_CPUSPEED */
 245 #endif /* CONFIG_CPU_MONAHANS */
 246
 247
 248         /*
 249          * before relocating, we have to setup RAM timing
 250          * because memory timing is board-dependend, you will
 251          * find a lowlevel_init.S in your board directory.
 252          */
 253         mov     ip,     lr
 254         bl      lowlevel_init
 255         mov     lr,     ip
 256
 257         /* Memory interfaces are working. Disable MMU and enable I-cache.   */
 258         /* mk: hmm, this is not in the monahans docs, leave it now but
 259          *     check here if it doesn't work :-) */
 260
 261         ldr     r0, =0x2001             /* enable access to all coproc.     */
 262         mcr     p15, 0, r0, c15, c1, 0
 263         CPWAIT r0
 264
 265         mcr     p15, 0, r0, c7, c10, 4  /* drain the write & fill buffers   */
 266         CPWAIT r0
 267
 268         mcr     p15, 0, r0, c7, c7, 0   /* flush Icache, Dcache and BTB     */
 269         CPWAIT r0
 270
 271         mcr     p15, 0, r0, c8, c7, 0   /* flush instuction and data TLBs   */
 272         CPWAIT r0
 273
 274         /* Enable the Icache                                                */
 275 /*
 276         mrc     p15, 0, r0, c1, c0, 0
 277         orr     r0, r0, #0x1800
 278         mcr     p15, 0, r0, c1, c0, 0
 279         CPWAIT
 280 */
 281         mov     pc, lr
 282
 283
 284 /****************************************************************************/
 285 /*                                                                          */
 286 /* Interrupt handling                                                       */
 287 /*                                                                          */
 288 /****************************************************************************/
 289
 290 /* IRQ stack frame                                                          */
 291
 292 #define S_FRAME_SIZE    72
 293
 294 #define S_OLD_R0        68
 295 #define S_PSR           64
 296 #define S_PC            60
 297 #define S_LR            56
 298 #define S_SP            52
 299
 300 #define S_IP            48
 301 #define S_FP            44
 302 #define S_R10           40
 303 #define S_R9            36
 304 #define S_R8            32
 305 #define S_R7            28
 306 #define S_R6            24
 307 #define S_R5            20
 308 #define S_R4            16
 309 #define S_R3            12
 310 #define S_R2            8
 311 #define S_R1            4
 312 #define S_R0            0
 313
 314 #define MODE_SVC 0x13
 315
 316         /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 317
 318         .macro  bad_save_user_regs
 319         sub     sp, sp, #S_FRAME_SIZE
 320         stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 321         add     r8, sp, #S_PC
 322
 323         ldr     r2, _armboot_start
 324         sub     r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 325         sub     r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 326         ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 327         add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 328
 329         add     r5, sp, #S_SP
 330         mov     r1, lr
 331         stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 332         mov     r0, sp
 333         .endm
 334
 335
 336         /* use irq_save_user_regs / irq_restore_user_regs for                */
 337         /* IRQ/FIQ handling                                                  */
 338
 339         .macro  irq_save_user_regs
 340         sub     sp, sp, #S_FRAME_SIZE
 341         stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 342         add     r8, sp, #S_PC
 343         stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 344         str     lr, [r8, #0]                    /* Save calling PC           */
 345         mrs     r6, spsr
 346         str     r6, [r8, #4]                    /* Save CPSR                 */
 347         str     r0, [r8, #8]                    /* Save OLD_R0               */
 348         mov     r0, sp
 349         .endm
 350
 351         .macro  irq_restore_user_regs
 352         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 353         mov     r0, r0
 354         ldr     lr, [sp, #S_PC]                 @ Get PC
 355         add     sp, sp, #S_FRAME_SIZE
 356         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 357         .endm
 358
 359         .macro get_bad_stack
 360         ldr     r13, _armboot_start             @ setup our mode stack
 361         sub     r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
 362         sub     r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 363
 364         str     lr, [r13]                       @ save caller lr / spsr
 365         mrs     lr, spsr
 366         str     lr, [r13, #4]
 367
 368         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 369         msr     spsr_c, r13
 370         mov     lr, pc
 371         movs    pc, lr
 372         .endm
 373
 374         .macro get_irq_stack                    @ setup IRQ stack
 375         ldr     sp, IRQ_STACK_START
 376         .endm
 377
 378         .macro get_fiq_stack                    @ setup FIQ stack
 379         ldr     sp, FIQ_STACK_START
 380         .endm
 381
 382
 383 /****************************************************************************/
 384 /*                                                                          */
 385 /* exception handlers                                                       */
 386 /*                                                                          */
 387 /****************************************************************************/
 388
 389         .align  5
 390 undefined_instruction:
 391         get_bad_stack
 392         bad_save_user_regs
 393         bl      do_undefined_instruction
 394
 395         .align  5
 396 software_interrupt:
 397         get_bad_stack
 398         bad_save_user_regs
 399         bl      do_software_interrupt
 400
 401         .align  5
 402 prefetch_abort:
 403         get_bad_stack
 404         bad_save_user_regs
 405         bl      do_prefetch_abort
 406
 407         .align  5
 408 data_abort:
 409         get_bad_stack
 410         bad_save_user_regs
 411         bl      do_data_abort
 412
 413         .align  5
 414 not_used:
 415         get_bad_stack
 416         bad_save_user_regs
 417         bl      do_not_used
 418
 419 #ifdef CONFIG_USE_IRQ
 420
 421         .align  5
 422 irq:
 423         get_irq_stack
 424         irq_save_user_regs
 425         bl      do_irq
 426         irq_restore_user_regs
 427
 428         .align  5
 429 fiq:
 430         get_fiq_stack
 431         irq_save_user_regs              /* someone ought to write a more    */
 432         bl      do_fiq                  /* effiction fiq_save_user_regs     */
 433         irq_restore_user_regs
 434
 435 #else
 436
 437         .align  5
 438 irq:
 439         get_bad_stack
 440         bad_save_user_regs
 441         bl      do_irq
 442
 443         .align  5
 444 fiq:
 445         get_bad_stack
 446         bad_save_user_regs
 447         bl      do_fiq
 448
 449 #endif
 450
 451 /****************************************************************************/
 452 /*                                                                          */
 453 /* Reset function: the PXA250 doesn't have a reset function, so we have to  */
 454 /* perform a watchdog timeout for a soft reset.                             */
 455 /*                                                                          */
 456 /****************************************************************************/
 457
 458         .align  5
 459 .globl reset_cpu
 460
 461         /* FIXME: this code is PXA250 specific. How is this handled on      */
 462         /*        other XScale processors?                                  */
 463
 464 reset_cpu:
 465
 466         /* We set OWE:WME (watchdog enable) and wait until timeout happens  */
 467
 468         ldr     r0, OSTIMER_BASE
 469         ldr     r1, [r0, #OWER]
 470         orr     r1, r1, #0x0001                 /* bit0: WME                */
 471         str     r1, [r0, #OWER]
 472
 473         /* OS timer does only wrap every 1165 seconds, so we have to set    */
 474         /* the match register as well.                                      */
 475
 476         ldr     r1, [r0, #OSCR]                 /* read OS timer            */
 477         add     r1, r1, #0x800                  /* let OSMR3 match after    */
 478         add     r1, r1, #0x800                  /* 4096*(1/3.6864MHz)=1ms   */
 479         str     r1, [r0, #OSMR3]
 480
 481 reset_endless:
 482
 483         b       reset_endless