cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those are 440SP/SPe.
   5  *
   6  * (C) Copyright 2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * COPYRIGHT   AMCC   CORPORATION 2004
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  *
  29  */
  30
  31 /* define DEBUG for debugging output (obviously ;-)) */
  32 #if 0
  33 #define DEBUG
  34 #endif
  35
  36 #include <common.h>
  37 #include <ppc4xx.h>
  38 #include <i2c.h>
  39 #include <asm/io.h>
  40 #include <asm/processor.h>
  41 #include <asm/mmu.h>
  42
  43 #if defined(CONFIG_SPD_EEPROM) &&                               \
  44         (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
  45
  46 #ifndef TRUE
  47 #define TRUE            1
  48 #endif
  49 #ifndef FALSE
  50 #define FALSE           0
  51 #endif
  52
  53 #define SDRAM_DDR1      1
  54 #define SDRAM_DDR2      2
  55 #define SDRAM_NONE      0
  56
  57 #define MAXDIMMS        2
  58 #define MAXRANKS        4
  59 #define MAXBXCF         4
  60 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  61
  62 #define ONE_BILLION     1000000000
  63
  64 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  65
  66 #if defined(DEBUG)
  67 static void ppc440sp_sdram_register_dump(void);
  68 #endif
  69
  70 /*-----------------------------------------------------------------------------+
  71  * Defines
  72  *-----------------------------------------------------------------------------*/
  73 /* Defines for the Read Cycle Delay test */
  74 #define NUMMEMTESTS 8
  75 #define NUMMEMWORDS 8
  76
  77 /* Private Structure Definitions */
  78
  79 /* enum only to ease code for cas latency setting */
  80 typedef enum ddr_cas_id {
  81         DDR_CAS_2      = 20,
  82         DDR_CAS_2_5    = 25,
  83         DDR_CAS_3      = 30,
  84         DDR_CAS_4      = 40,
  85         DDR_CAS_5      = 50
  86 } ddr_cas_id_t;
  87
  88 /*-----------------------------------------------------------------------------+
  89  * Prototypes
  90  *-----------------------------------------------------------------------------*/
  91 static unsigned long sdram_memsize(void);
  92 void program_tlb(u32 start, u32 size);
  93 static void get_spd_info(unsigned long *dimm_populated,
  94                          unsigned char *iic0_dimm_addr,
  95                          unsigned long num_dimm_banks);
  96 static void check_mem_type(unsigned long *dimm_populated,
  97                            unsigned char *iic0_dimm_addr,
  98                            unsigned long num_dimm_banks);
  99 static void check_frequency(unsigned long *dimm_populated,
 100                             unsigned char *iic0_dimm_addr,
 101                             unsigned long num_dimm_banks);
 102 static void check_rank_number(unsigned long *dimm_populated,
 103                               unsigned char *iic0_dimm_addr,
 104                               unsigned long num_dimm_banks);
 105 static void check_voltage_type(unsigned long *dimm_populated,
 106                                unsigned char *iic0_dimm_addr,
 107                                unsigned long num_dimm_banks);
 108 static void program_memory_queue(unsigned long *dimm_populated,
 109                                  unsigned char *iic0_dimm_addr,
 110                                  unsigned long num_dimm_banks);
 111 static void program_codt(unsigned long *dimm_populated,
 112                          unsigned char *iic0_dimm_addr,
 113                          unsigned long num_dimm_banks);
 114 static void program_mode(unsigned long *dimm_populated,
 115                          unsigned char *iic0_dimm_addr,
 116                          unsigned long num_dimm_banks,
 117                          ddr_cas_id_t *selected_cas);
 118 static void program_tr(unsigned long *dimm_populated,
 119                        unsigned char *iic0_dimm_addr,
 120                        unsigned long num_dimm_banks);
 121 static void program_rtr(unsigned long *dimm_populated,
 122                         unsigned char *iic0_dimm_addr,
 123                         unsigned long num_dimm_banks);
 124 static void program_bxcf(unsigned long *dimm_populated,
 125                          unsigned char *iic0_dimm_addr,
 126                          unsigned long num_dimm_banks);
 127 static void program_copt1(unsigned long *dimm_populated,
 128                           unsigned char *iic0_dimm_addr,
 129                           unsigned long num_dimm_banks);
 130 static void program_initplr(unsigned long *dimm_populated,
 131                             unsigned char *iic0_dimm_addr,
 132                             unsigned long num_dimm_banks,
 133                             ddr_cas_id_t selected_cas);
 134 static unsigned long is_ecc_enabled(void);
 135 static void program_ecc(unsigned long *dimm_populated,
 136                         unsigned char *iic0_dimm_addr,
 137                         unsigned long num_dimm_banks);
 138 static void program_ecc_addr(unsigned long start_address,
 139                              unsigned long num_bytes);
 140
 141 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 142 static void     test(void);
 143 #else
 144 static void     DQS_calibration_process(void);
 145 #endif
 146 static void program_DQS_calibration(unsigned long *dimm_populated,
 147                                     unsigned char *iic0_dimm_addr,
 148                                     unsigned long num_dimm_banks);
 149
 150 static u32 mfdcr_any(u32 dcr)
 151 {
 152         u32 val;
 153
 154         switch (dcr) {
 155         case SDRAM_R0BAS + 0:
 156                 val = mfdcr(SDRAM_R0BAS + 0);
 157                 break;
 158         case SDRAM_R0BAS + 1:
 159                 val = mfdcr(SDRAM_R0BAS + 1);
 160                 break;
 161         case SDRAM_R0BAS + 2:
 162                 val = mfdcr(SDRAM_R0BAS + 2);
 163                 break;
 164         case SDRAM_R0BAS + 3:
 165                 val = mfdcr(SDRAM_R0BAS + 3);
 166                 break;
 167         default:
 168                 printf("DCR %d not defined in case statement!!!\n", dcr);
 169                 val = 0; /* just to satisfy the compiler */
 170         }
 171
 172         return val;
 173 }
 174
 175 static void mtdcr_any(u32 dcr, u32 val)
 176 {
 177         switch (dcr) {
 178         case SDRAM_R0BAS + 0:
 179                 mtdcr(SDRAM_R0BAS + 0, val);
 180                 break;
 181         case SDRAM_R0BAS + 1:
 182                 mtdcr(SDRAM_R0BAS + 1, val);
 183                 break;
 184         case SDRAM_R0BAS + 2:
 185                 mtdcr(SDRAM_R0BAS + 2, val);
 186                 break;
 187         case SDRAM_R0BAS + 3:
 188                 mtdcr(SDRAM_R0BAS + 3, val);
 189                 break;
 190         default:
 191                 printf("DCR %d not defined in case statement!!!\n", dcr);
 192         }
 193 }
 194
 195 static void wait_ddr_idle(void)
 196 {
 197         u32 val;
 198
 199         do {
 200                 mfsdram(SDRAM_MCSTAT, val);
 201         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
 202 }
 203
 204 static unsigned char spd_read(uchar chip, uint addr)
 205 {
 206         unsigned char data[2];
 207
 208         if (i2c_probe(chip) == 0)
 209                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 210                         return data[0];
 211
 212         return 0;
 213 }
 214
 215 /*-----------------------------------------------------------------------------+
 216  * sdram_memsize
 217  *-----------------------------------------------------------------------------*/
 218 static unsigned long sdram_memsize(void)
 219 {
 220         unsigned long mem_size;
 221         unsigned long mcopt2;
 222         unsigned long mcstat;
 223         unsigned long mb0cf;
 224         unsigned long sdsz;
 225         unsigned long i;
 226
 227         mem_size = 0;
 228
 229         mfsdram(SDRAM_MCOPT2, mcopt2);
 230         mfsdram(SDRAM_MCSTAT, mcstat);
 231
 232         /* DDR controller must be enabled and not in self-refresh. */
 233         /* Otherwise memsize is zero. */
 234         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 235             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 236             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 237                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 238                 for (i = 0; i < 4; i++) {
 239                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 240                         /* Banks enabled */
 241                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 242                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 243
 244                                 switch(sdsz) {
 245                                 case SDRAM_RXBAS_SDSZ_8:
 246                                         mem_size+=8;
 247                                         break;
 248                                 case SDRAM_RXBAS_SDSZ_16:
 249                                         mem_size+=16;
 250                                         break;
 251                                 case SDRAM_RXBAS_SDSZ_32:
 252                                         mem_size+=32;
 253                                         break;
 254                                 case SDRAM_RXBAS_SDSZ_64:
 255                                         mem_size+=64;
 256                                         break;
 257                                 case SDRAM_RXBAS_SDSZ_128:
 258                                         mem_size+=128;
 259                                         break;
 260                                 case SDRAM_RXBAS_SDSZ_256:
 261                                         mem_size+=256;
 262                                         break;
 263                                 case SDRAM_RXBAS_SDSZ_512:
 264                                         mem_size+=512;
 265                                         break;
 266                                 case SDRAM_RXBAS_SDSZ_1024:
 267                                         mem_size+=1024;
 268                                         break;
 269                                 case SDRAM_RXBAS_SDSZ_2048:
 270                                         mem_size+=2048;
 271                                         break;
 272                                 case SDRAM_RXBAS_SDSZ_4096:
 273                                         mem_size+=4096;
 274                                         break;
 275                                 default:
 276                                         mem_size=0;
 277                                         break;
 278                                 }
 279                         }
 280                 }
 281         }
 282
 283         mem_size *= 1024 * 1024;
 284         return(mem_size);
 285 }
 286
 287 /*-----------------------------------------------------------------------------+
 288  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 289  * Note: This routine runs from flash with a stack set up in the chip's
 290  * sram space.  It is important that the routine does not require .sbss, .bss or
 291  * .data sections.  It also cannot call routines that require these sections.
 292  *-----------------------------------------------------------------------------*/
 293 /*-----------------------------------------------------------------------------
 294  * Function:     initdram
 295  * Description:  Configures SDRAM memory banks for DDR operation.
 296  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 297  *               via the IIC bus and then configures the DDR SDRAM memory
 298  *               banks appropriately. If Auto Memory Configuration is
 299  *               not used, it is assumed that no DIMM is plugged
 300  *-----------------------------------------------------------------------------*/
 301 long int initdram(int board_type)
 302 {
 303         unsigned char spd0[MAX_SPD_BYTES];
 304         unsigned char spd1[MAX_SPD_BYTES];
 305         unsigned char *dimm_spd[MAXDIMMS];
 306         unsigned long dimm_populated[MAXDIMMS];
 307         unsigned char iic0_dimm_addr[MAXDIMMS];
 308         unsigned long num_dimm_banks;               /* on board dimm banks */
 309         unsigned long val;
 310         ddr_cas_id_t  selected_cas;
 311         unsigned long dram_size = 0;
 312
 313         num_dimm_banks = sizeof(iic0_dimm_addr);
 314
 315         /*------------------------------------------------------------------
 316          * Set up an array of SPD matrixes.
 317          *-----------------------------------------------------------------*/
 318         dimm_spd[0] = spd0;
 319         dimm_spd[1] = spd1;
 320
 321         /*------------------------------------------------------------------
 322          * Set up an array of iic0 dimm addresses.
 323          *-----------------------------------------------------------------*/
 324         iic0_dimm_addr[0] = IIC0_DIMM0_ADDR;
 325         iic0_dimm_addr[1] = IIC0_DIMM1_ADDR;
 326
 327         /*------------------------------------------------------------------
 328          * Reset the DDR-SDRAM controller.
 329          *-----------------------------------------------------------------*/
 330         mtsdr(SDR0_SRST, 0x00200000);
 331         mtsdr(SDR0_SRST, 0x00000000);
 332
 333         /*
 334          * Make sure I2C controller is initialized
 335          * before continuing.
 336          */
 337
 338         /* switch to correct I2C bus */
 339         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 340         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 341
 342         /*------------------------------------------------------------------
 343          * Clear out the serial presence detect buffers.
 344          * Perform IIC reads from the dimm.  Fill in the spds.
 345          * Check to see if the dimm slots are populated
 346          *-----------------------------------------------------------------*/
 347         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 348
 349         /*------------------------------------------------------------------
 350          * Check the memory type for the dimms plugged.
 351          *-----------------------------------------------------------------*/
 352         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 353
 354         /*------------------------------------------------------------------
 355          * Check the frequency supported for the dimms plugged.
 356          *-----------------------------------------------------------------*/
 357         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 358
 359         /*------------------------------------------------------------------
 360          * Check the total rank number.
 361          *-----------------------------------------------------------------*/
 362         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 363
 364         /*------------------------------------------------------------------
 365          * Check the voltage type for the dimms plugged.
 366          *-----------------------------------------------------------------*/
 367         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 368
 369         /*------------------------------------------------------------------
 370          * Program SDRAM controller options 2 register
 371          * Except Enabling of the memory controller.
 372          *-----------------------------------------------------------------*/
 373         mfsdram(SDRAM_MCOPT2, val);
 374         mtsdram(SDRAM_MCOPT2,
 375                 (val &
 376                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 377                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 378                    SDRAM_MCOPT2_ISIE_MASK))
 379                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 380                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 381                    SDRAM_MCOPT2_ISIE_ENABLE));
 382
 383         /*------------------------------------------------------------------
 384          * Program SDRAM controller options 1 register
 385          * Note: Does not enable the memory controller.
 386          *-----------------------------------------------------------------*/
 387         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 388
 389         /*------------------------------------------------------------------
 390          * Set the SDRAM Controller On Die Termination Register
 391          *-----------------------------------------------------------------*/
 392         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 393
 394         /*------------------------------------------------------------------
 395          * Program SDRAM refresh register.
 396          *-----------------------------------------------------------------*/
 397         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 398
 399         /*------------------------------------------------------------------
 400          * Program SDRAM mode register.
 401          *-----------------------------------------------------------------*/
 402         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks, &selected_cas);
 403
 404         /*------------------------------------------------------------------
 405          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 406          *-----------------------------------------------------------------*/
 407         mfsdram(SDRAM_WRDTR, val);
 408         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 409                 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 410
 411         /*------------------------------------------------------------------
 412          * Set the SDRAM Clock Timing Register
 413          *-----------------------------------------------------------------*/
 414         mfsdram(SDRAM_CLKTR, val);
 415         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
 416
 417         /*------------------------------------------------------------------
 418          * Program the BxCF registers.
 419          *-----------------------------------------------------------------*/
 420         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 421
 422         /*------------------------------------------------------------------
 423          * Program SDRAM timing registers.
 424          *-----------------------------------------------------------------*/
 425         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 426
 427         /*------------------------------------------------------------------
 428          * Set the Extended Mode register
 429          *-----------------------------------------------------------------*/
 430         mfsdram(SDRAM_MEMODE, val);
 431         mtsdram(SDRAM_MEMODE,
 432                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 433                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 434                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 435                  | SDRAM_MEMODE_RTT_75OHM | SDRAM_MEMODE_DQS_ENABLE));
 436
 437         /*------------------------------------------------------------------
 438          * Program Initialization preload registers.
 439          *-----------------------------------------------------------------*/
 440         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 441                         selected_cas);
 442
 443         /*------------------------------------------------------------------
 444          * Delay to ensure 200usec have elapsed since reset.
 445          *-----------------------------------------------------------------*/
 446         udelay(400);
 447
 448         /*------------------------------------------------------------------
 449          * Set the memory queue core base addr.
 450          *-----------------------------------------------------------------*/
 451         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 452
 453         /*------------------------------------------------------------------
 454          * Program SDRAM controller options 2 register
 455          * Enable the memory controller.
 456          *-----------------------------------------------------------------*/
 457         mfsdram(SDRAM_MCOPT2, val);
 458         mtsdram(SDRAM_MCOPT2,
 459                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 460                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 461                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 462
 463         /*------------------------------------------------------------------
 464          * Wait for SDRAM_CFG0_DC_EN to complete.
 465          *-----------------------------------------------------------------*/
 466         do {
 467                 mfsdram(SDRAM_MCSTAT, val);
 468         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 469
 470         /* get installed memory size */
 471         dram_size = sdram_memsize();
 472
 473         /* and program tlb entries for this size (dynamic) */
 474         program_tlb(0, dram_size);
 475
 476 #if 1 /* TODO: ECC support will come later */
 477         /*------------------------------------------------------------------
 478          * If ecc is enabled, initialize the parity bits.
 479          *-----------------------------------------------------------------*/
 480         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 481 #endif
 482
 483         /*------------------------------------------------------------------
 484          * DQS calibration.
 485          *-----------------------------------------------------------------*/
 486         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 487
 488 #ifdef DEBUG
 489         ppc440sp_sdram_register_dump();
 490 #endif
 491
 492         return dram_size;
 493 }
 494
 495 static void get_spd_info(unsigned long *dimm_populated,
 496                          unsigned char *iic0_dimm_addr,
 497                          unsigned long num_dimm_banks)
 498 {
 499         unsigned long dimm_num;
 500         unsigned long dimm_found;
 501         unsigned char num_of_bytes;
 502         unsigned char total_size;
 503
 504         dimm_found = FALSE;
 505         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 506                 num_of_bytes = 0;
 507                 total_size = 0;
 508
 509                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 510                 debug("\nspd_read(0x%x) returned %d\n",
 511                       iic0_dimm_addr[dimm_num], num_of_bytes);
 512                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 513                 debug("spd_read(0x%x) returned %d\n",
 514                       iic0_dimm_addr[dimm_num], total_size);
 515
 516                 if ((num_of_bytes != 0) && (total_size != 0)) {
 517                         dimm_populated[dimm_num] = TRUE;
 518                         dimm_found = TRUE;
 519                         debug("DIMM slot %lu: populated\n", dimm_num);
 520                 } else {
 521                         dimm_populated[dimm_num] = FALSE;
 522                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 523                 }
 524         }
 525
 526         if (dimm_found == FALSE) {
 527                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 528                 hang();
 529         }
 530 }
 531
 532 #ifdef CONFIG_ADD_RAM_INFO
 533 void board_add_ram_info(int use_default)
 534 {
 535         if (is_ecc_enabled())
 536                 puts(" (ECC enabled)");
 537         else
 538                 puts(" (ECC not enabled)");
 539 }
 540 #endif
 541
 542 /*------------------------------------------------------------------
 543  * For the memory DIMMs installed, this routine verifies that they
 544  * really are DDR specific DIMMs.
 545  *-----------------------------------------------------------------*/
 546 static void check_mem_type(unsigned long *dimm_populated,
 547                            unsigned char *iic0_dimm_addr,
 548                            unsigned long num_dimm_banks)
 549 {
 550         unsigned long dimm_num;
 551         unsigned long dimm_type;
 552
 553         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 554                 if (dimm_populated[dimm_num] == TRUE) {
 555                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 556                         switch (dimm_type) {
 557                         case 1:
 558                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 559                                        "slot %d.\n", (unsigned int)dimm_num);
 560                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 561                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 562                                 hang();
 563                                 break;
 564                         case 2:
 565                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 566                                        (unsigned int)dimm_num);
 567                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 568                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 569                                 hang();
 570                                 break;
 571                         case 3:
 572                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 573                                        (unsigned int)dimm_num);
 574                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 575                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 576                                 hang();
 577                                 break;
 578                         case 4:
 579                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 580                                        (unsigned int)dimm_num);
 581                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 582                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 583                                 hang();
 584                                 break;
 585                         case 5:
 586                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 587                                        (unsigned int)dimm_num);
 588                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 589                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 590                                 hang();
 591                                 break;
 592                         case 6:
 593                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 594                                        (unsigned int)dimm_num);
 595                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 596                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 597                                 hang();
 598                                 break;
 599                         case 7:
 600                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 601                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 602                                 break;
 603                         case 8:
 604                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 605                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 606                                 break;
 607                         default:
 608                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 609                                        (unsigned int)dimm_num);
 610                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 611                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 612                                 hang();
 613                                 break;
 614                         }
 615                 }
 616         }
 617         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 618                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 619                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 620                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 621                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 622                         hang();
 623                 }
 624         }
 625 }
 626
 627 /*------------------------------------------------------------------
 628  * For the memory DIMMs installed, this routine verifies that
 629  * frequency previously calculated is supported.
 630  *-----------------------------------------------------------------*/
 631 static void check_frequency(unsigned long *dimm_populated,
 632                             unsigned char *iic0_dimm_addr,
 633                             unsigned long num_dimm_banks)
 634 {
 635         unsigned long dimm_num;
 636         unsigned long tcyc_reg;
 637         unsigned long cycle_time;
 638         unsigned long calc_cycle_time;
 639         unsigned long sdram_freq;
 640         unsigned long sdr_ddrpll;
 641         PPC440_SYS_INFO board_cfg;
 642
 643         /*------------------------------------------------------------------
 644          * Get the board configuration info.
 645          *-----------------------------------------------------------------*/
 646         get_sys_info(&board_cfg);
 647
 648         mfsdr(sdr_ddr0, sdr_ddrpll);
 649         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 650
 651         /*
 652          * calc_cycle_time is calculated from DDR frequency set by board/chip
 653          * and is expressed in multiple of 10 picoseconds
 654          * to match the way DIMM cycle time is calculated below.
 655          */
 656         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 657
 658         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 659                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 660                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 661                         /*
 662                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 663                          * the higher order nibble (bits 4-7) designates the cycle time
 664                          * to a granularity of 1ns;
 665                          * the value presented by the lower order nibble (bits 0-3)
 666                          * has a granularity of .1ns and is added to the value designated
 667                          * by the higher nibble. In addition, four lines of the lower order
 668                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 669                          */
 670                          /* Convert from hex to decimal */
 671                         if ((tcyc_reg & 0x0F) == 0x0D)
 672                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 673                         else if ((tcyc_reg & 0x0F) == 0x0C)
 674                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 675                         else if ((tcyc_reg & 0x0F) == 0x0B)
 676                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 677                         else if ((tcyc_reg & 0x0F) == 0x0A)
 678                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 679                         else
 680                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 681                                         ((tcyc_reg & 0x0F)*10);
 682
 683                         if  (cycle_time > (calc_cycle_time + 10)) {
 684                                 /*
 685                                  * the provided sdram cycle_time is too small
 686                                  * for the available DIMM cycle_time.
 687                                  * The additionnal 100ps is here to accept a small incertainty.
 688                                  */
 689                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 690                                        "slot %d \n while calculated cycle time is %d ps.\n",
 691                                        (unsigned int)(cycle_time*10),
 692                                        (unsigned int)dimm_num,
 693                                        (unsigned int)(calc_cycle_time*10));
 694                                 printf("Replace the DIMM, or change DDR frequency via "
 695                                        "strapping bits.\n\n");
 696                                 hang();
 697                         }
 698                 }
 699         }
 700 }
 701
 702 /*------------------------------------------------------------------
 703  * For the memory DIMMs installed, this routine verifies two
 704  * ranks/banks maximum are availables.
 705  *-----------------------------------------------------------------*/
 706 static void check_rank_number(unsigned long *dimm_populated,
 707                               unsigned char *iic0_dimm_addr,
 708                               unsigned long num_dimm_banks)
 709 {
 710         unsigned long dimm_num;
 711         unsigned long dimm_rank;
 712         unsigned long total_rank = 0;
 713
 714         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 715                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 716                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 717                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 718                                 dimm_rank = (dimm_rank & 0x0F) +1;
 719                         else
 720                                 dimm_rank = dimm_rank & 0x0F;
 721
 722
 723                         if (dimm_rank > MAXRANKS) {
 724                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 725                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 726                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 727                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 728                                 hang();
 729                         } else
 730                                 total_rank += dimm_rank;
 731                 }
 732                 if (total_rank > MAXRANKS) {
 733                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 734                                "for all slots.\n", (unsigned int)total_rank);
 735                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 736                         printf("Remove one of the DIMM modules.\n\n");
 737                         hang();
 738                 }
 739         }
 740 }
 741
 742 /*------------------------------------------------------------------
 743  * only support 2.5V modules.
 744  * This routine verifies this.
 745  *-----------------------------------------------------------------*/
 746 static void check_voltage_type(unsigned long *dimm_populated,
 747                                unsigned char *iic0_dimm_addr,
 748                                unsigned long num_dimm_banks)
 749 {
 750         unsigned long dimm_num;
 751         unsigned long voltage_type;
 752
 753         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 754                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 755                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 756                         switch (voltage_type) {
 757                         case 0x00:
 758                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 759                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 760                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 761                                        (unsigned int)dimm_num);
 762                                 hang();
 763                                 break;
 764                         case 0x01:
 765                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 766                                 printf("This DIMM is LVTTL.\n");
 767                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 768                                        (unsigned int)dimm_num);
 769                                 hang();
 770                                 break;
 771                         case 0x02:
 772                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 773                                 printf("This DIMM is 1.5 Volt.\n");
 774                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 775                                        (unsigned int)dimm_num);
 776                                 hang();
 777                                 break;
 778                         case 0x03:
 779                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 780                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 781                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 782                                        (unsigned int)dimm_num);
 783                                 hang();
 784                                 break;
 785                         case 0x04:
 786                                 /* 2.5 Voltage only for DDR1 */
 787                                 break;
 788                         case 0x05:
 789                                 /* 1.8 Voltage only for DDR2 */
 790                                 break;
 791                         default:
 792                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 793                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 794                                        (unsigned int)dimm_num);
 795                                 hang();
 796                                 break;
 797                         }
 798                 }
 799         }
 800 }
 801
 802 /*-----------------------------------------------------------------------------+
 803  * program_copt1.
 804  *-----------------------------------------------------------------------------*/
 805 static void program_copt1(unsigned long *dimm_populated,
 806                           unsigned char *iic0_dimm_addr,
 807                           unsigned long num_dimm_banks)
 808 {
 809         unsigned long dimm_num;
 810         unsigned long mcopt1;
 811         unsigned long ecc_enabled;
 812         unsigned long ecc = 0;
 813         unsigned long data_width = 0;
 814         unsigned long dimm_32bit;
 815         unsigned long dimm_64bit;
 816         unsigned long registered = 0;
 817         unsigned long attribute = 0;
 818         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 819         unsigned long bankcount;
 820         unsigned long ddrtype;
 821         unsigned long val;
 822
 823         ecc_enabled = TRUE;
 824         dimm_32bit = FALSE;
 825         dimm_64bit = FALSE;
 826         buf0 = FALSE;
 827         buf1 = FALSE;
 828
 829         /*------------------------------------------------------------------
 830          * Set memory controller options reg 1, SDRAM_MCOPT1.
 831          *-----------------------------------------------------------------*/
 832         mfsdram(SDRAM_MCOPT1, val);
 833         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 834                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 835                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 836                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 837                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 838                          SDRAM_MCOPT1_DREF_MASK);
 839
 840         mcopt1 |= SDRAM_MCOPT1_QDEP;
 841         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 842         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 843         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 844         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 845         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 846
 847         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 848                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 849                         /* test ecc support */
 850                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 851                         if (ecc != 0x02) /* ecc not supported */
 852                                 ecc_enabled = FALSE;
 853
 854                         /* test bank count */
 855                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 856                         if (bankcount == 0x04) /* bank count = 4 */
 857                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 858                         else /* bank count = 8 */
 859                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 860
 861                         /* test DDR type */
 862                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 863                         /* test for buffered/unbuffered, registered, differential clocks */
 864                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 865                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 866
 867                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 868                         if (dimm_num == 0) {
 869                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 870                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 871                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 872                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 873                                 if (registered == 1) { /* DDR2 always buffered */
 874                                         /* TODO: what about above  comments ? */
 875                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 876                                         buf0 = TRUE;
 877                                 } else {
 878                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 879                                         if ((attribute & 0x02) == 0x00) {
 880                                                 /* buffered not supported */
 881                                                 buf0 = FALSE;
 882                                         } else {
 883                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 884                                                 buf0 = TRUE;
 885                                         }
 886                                 }
 887                         }
 888                         else if (dimm_num == 1) {
 889                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 890                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 891                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 892                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 893                                 if (registered == 1) {
 894                                         /* DDR2 always buffered */
 895                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 896                                         buf1 = TRUE;
 897                                 } else {
 898                                         if ((attribute & 0x02) == 0x00) {
 899                                                 /* buffered not supported */
 900                                                 buf1 = FALSE;
 901                                         } else {
 902                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 903                                                 buf1 = TRUE;
 904                                         }
 905                                 }
 906                         }
 907
 908                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
 909                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
 910                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
 911
 912                         switch (data_width) {
 913                         case 72:
 914                         case 64:
 915                                 dimm_64bit = TRUE;
 916                                 break;
 917                         case 40:
 918                         case 32:
 919                                 dimm_32bit = TRUE;
 920                                 break;
 921                         default:
 922                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
 923                                        data_width);
 924                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
 925                                 break;
 926                         }
 927                 }
 928         }
 929
 930         /* verify matching properties */
 931         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
 932                 if (buf0 != buf1) {
 933                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
 934                         hang();
 935                 }
 936         }
 937
 938         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
 939                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
 940                 hang();
 941         }
 942         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
 943                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
 944         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
 945                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
 946         } else {
 947                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
 948                 hang();
 949         }
 950
 951         if (ecc_enabled == TRUE)
 952                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
 953         else
 954                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
 955
 956         mtsdram(SDRAM_MCOPT1, mcopt1);
 957 }
 958
 959 /*-----------------------------------------------------------------------------+
 960  * program_codt.
 961  *-----------------------------------------------------------------------------*/
 962 static void program_codt(unsigned long *dimm_populated,
 963                          unsigned char *iic0_dimm_addr,
 964                          unsigned long num_dimm_banks)
 965 {
 966         unsigned long codt;
 967         unsigned long modt0 = 0;
 968         unsigned long modt1 = 0;
 969         unsigned long modt2 = 0;
 970         unsigned long modt3 = 0;
 971         unsigned char dimm_num;
 972         unsigned char dimm_rank;
 973         unsigned char total_rank = 0;
 974         unsigned char total_dimm = 0;
 975         unsigned char dimm_type = 0;
 976         unsigned char firstSlot = 0;
 977
 978         /*------------------------------------------------------------------
 979          * Set the SDRAM Controller On Die Termination Register
 980          *-----------------------------------------------------------------*/
 981         mfsdram(SDRAM_CODT, codt);
 982         codt |= (SDRAM_CODT_IO_NMODE
 983                  & (~SDRAM_CODT_DQS_SINGLE_END
 984                     & ~SDRAM_CODT_CKSE_SINGLE_END
 985                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
 986                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
 987
 988         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 989                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 990                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
 991                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
 992                                 dimm_rank = (dimm_rank & 0x0F) + 1;
 993                                 dimm_type = SDRAM_DDR2;
 994                         } else {
 995                                 dimm_rank = dimm_rank & 0x0F;
 996                                 dimm_type = SDRAM_DDR1;
 997                         }
 998
 999                         total_rank +=  dimm_rank;
1000                         total_dimm ++;
1001                         if ((dimm_num == 0) && (total_dimm == 1))
1002                                 firstSlot = TRUE;
1003                         else
1004                                 firstSlot = FALSE;
1005                 }
1006         }
1007         if (dimm_type == SDRAM_DDR2) {
1008                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1009                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1010                         if (total_rank == 1) {
1011                                 codt |= 0x00800000;
1012                                 modt0 = 0x01000000;
1013                                 modt1 = 0x00000000;
1014                                 modt2 = 0x00000000;
1015                                 modt3 = 0x00000000;
1016                         }
1017                         if (total_rank == 2) {
1018                                 codt |= 0x02800000;
1019                                 modt0 = 0x06000000;
1020                                 modt1 = 0x01800000;
1021                                 modt2 = 0x00000000;
1022                                 modt3 = 0x00000000;
1023                         }
1024                 } else {
1025                         if (total_rank == 1) {
1026                                 codt |= 0x00800000;
1027                                 modt0 = 0x01000000;
1028                                 modt1 = 0x00000000;
1029                                 modt2 = 0x00000000;
1030                                 modt3 = 0x00000000;
1031                         }
1032                         if (total_rank == 2) {
1033                                 codt |= 0x02800000;
1034                                 modt0 = 0x06000000;
1035                                 modt1 = 0x01800000;
1036                                 modt2 = 0x00000000;
1037                                 modt3 = 0x00000000;
1038                         }
1039                 }
1040                 if (total_dimm == 2) {
1041                         if (total_rank == 2) {
1042                                 codt |= 0x08800000;
1043                                 modt0 = 0x18000000;
1044                                 modt1 = 0x00000000;
1045                                 modt2 = 0x01800000;
1046                                 modt3 = 0x00000000;
1047                         }
1048                         if (total_rank == 4) {
1049                                 codt |= 0x2a800000;
1050                                 modt0 = 0x18000000;
1051                                 modt1 = 0x18000000;
1052                                 modt2 = 0x01800000;
1053                                 modt3 = 0x01800000;
1054                         }
1055                 }
1056         } else {
1057                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1058                 modt0 = 0x00000000;
1059                 modt1 = 0x00000000;
1060                 modt2 = 0x00000000;
1061                 modt3 = 0x00000000;
1062
1063                 if (total_dimm == 1) {
1064                         if (total_rank == 1)
1065                                 codt |= 0x00800000;
1066                         if (total_rank == 2)
1067                                 codt |= 0x02800000;
1068                 }
1069                 if (total_dimm == 2) {
1070                         if (total_rank == 2)
1071                                 codt |= 0x08800000;
1072                         if (total_rank == 4)
1073                                 codt |= 0x2a800000;
1074                 }
1075         }
1076
1077         debug("nb of dimm %d\n", total_dimm);
1078         debug("nb of rank %d\n", total_rank);
1079         if (total_dimm == 1)
1080                 debug("dimm in slot %d\n", firstSlot);
1081
1082         mtsdram(SDRAM_CODT, codt);
1083         mtsdram(SDRAM_MODT0, modt0);
1084         mtsdram(SDRAM_MODT1, modt1);
1085         mtsdram(SDRAM_MODT2, modt2);
1086         mtsdram(SDRAM_MODT3, modt3);
1087 }
1088
1089 /*-----------------------------------------------------------------------------+
1090  * program_initplr.
1091  *-----------------------------------------------------------------------------*/
1092 static void program_initplr(unsigned long *dimm_populated,
1093                             unsigned char *iic0_dimm_addr,
1094                             unsigned long num_dimm_banks,
1095                             ddr_cas_id_t selected_cas)
1096 {
1097         unsigned long MR_CAS_value = 0;
1098
1099         /******************************************************
1100          ** Assumption: if more than one DIMM, all DIMMs are the same
1101          **             as already checked in check_memory_type
1102          ******************************************************/
1103
1104         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1105                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1106                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1107                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1108                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1109                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1110                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1111                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1112                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1113         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1114                 switch (selected_cas) {
1115                         /*
1116                          * The CAS latency is a field of the Mode Reg
1117                          * that need to be set from caller input.
1118                          * CAS bits in Mode Reg are starting at bit 4 at least for the Micron DDR2
1119                          * this is the reason of the shift.
1120                          */
1121                 case DDR_CAS_3:
1122                         MR_CAS_value = 3 << 4;
1123                         break;
1124                 case DDR_CAS_4:
1125                         MR_CAS_value = 4 << 4;
1126                         break;
1127                 case DDR_CAS_5:
1128                         MR_CAS_value = 5 << 4;
1129                         break;
1130                 default:
1131                         printf("ERROR: ucode error on selected_cas value %d", (unsigned char)selected_cas);
1132                         hang();
1133                         break;
1134                 }
1135
1136                 mtsdram(SDRAM_INITPLR0,  0xB5380000);                   /* NOP */
1137                 mtsdram(SDRAM_INITPLR1,  0x82100400);                   /* precharge 8 DDR clock cycle */
1138                 mtsdram(SDRAM_INITPLR2,  0x80820000);                   /* EMR2 */
1139                 mtsdram(SDRAM_INITPLR3,  0x80830000);                   /* EMR3 */
1140                 mtsdram(SDRAM_INITPLR4,  0x80810000);                   /* EMR DLL ENABLE */
1141                 mtsdram(SDRAM_INITPLR5,  0x80800502 | MR_CAS_value);    /* MR w/ DLL reset */
1142                 mtsdram(SDRAM_INITPLR6,  0x82100400);                   /* precharge 8 DDR clock cycle */
1143                 mtsdram(SDRAM_INITPLR7,  0x8a080000);                   /* Refresh  50 DDR clock cycle */
1144                 mtsdram(SDRAM_INITPLR8,  0x8a080000);                   /* Refresh  50 DDR clock cycle */
1145                 mtsdram(SDRAM_INITPLR9,  0x8a080000);                   /* Refresh  50 DDR clock cycle */
1146                 mtsdram(SDRAM_INITPLR10, 0x8a080000);                   /* Refresh  50 DDR clock cycle */
1147                 mtsdram(SDRAM_INITPLR11, 0x80800402 | MR_CAS_value);    /* MR w/o DLL reset */
1148                 mtsdram(SDRAM_INITPLR12, 0x80810380);                   /* EMR OCD Default */
1149                 mtsdram(SDRAM_INITPLR13, 0x80810000);                   /* EMR OCD Exit */
1150         } else {
1151                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1152                 hang();
1153         }
1154 }
1155
1156 /*------------------------------------------------------------------
1157  * This routine programs the SDRAM_MMODE register.
1158  * the selected_cas is an output parameter, that will be passed
1159  * by caller to call the above program_initplr( )
1160  *-----------------------------------------------------------------*/
1161 static void program_mode(unsigned long *dimm_populated,
1162                          unsigned char *iic0_dimm_addr,
1163                          unsigned long num_dimm_banks,
1164                          ddr_cas_id_t *selected_cas)
1165 {
1166         unsigned long dimm_num;
1167         unsigned long sdram_ddr1;
1168         unsigned long t_wr_ns;
1169         unsigned long t_wr_clk;
1170         unsigned long cas_bit;
1171         unsigned long cas_index;
1172         unsigned long sdram_freq;
1173         unsigned long ddr_check;
1174         unsigned long mmode;
1175         unsigned long tcyc_reg;
1176         unsigned long cycle_2_0_clk;
1177         unsigned long cycle_2_5_clk;
1178         unsigned long cycle_3_0_clk;
1179         unsigned long cycle_4_0_clk;
1180         unsigned long cycle_5_0_clk;
1181         unsigned long max_2_0_tcyc_ns_x_100;
1182         unsigned long max_2_5_tcyc_ns_x_100;
1183         unsigned long max_3_0_tcyc_ns_x_100;
1184         unsigned long max_4_0_tcyc_ns_x_100;
1185         unsigned long max_5_0_tcyc_ns_x_100;
1186         unsigned long cycle_time_ns_x_100[3];
1187         PPC440_SYS_INFO board_cfg;
1188         unsigned char cas_2_0_available;
1189         unsigned char cas_2_5_available;
1190         unsigned char cas_3_0_available;
1191         unsigned char cas_4_0_available;
1192         unsigned char cas_5_0_available;
1193         unsigned long sdr_ddrpll;
1194
1195         /*------------------------------------------------------------------
1196          * Get the board configuration info.
1197          *-----------------------------------------------------------------*/
1198         get_sys_info(&board_cfg);
1199
1200         mfsdr(sdr_ddr0, sdr_ddrpll);
1201         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1202
1203         /*------------------------------------------------------------------
1204          * Handle the timing.  We need to find the worst case timing of all
1205          * the dimm modules installed.
1206          *-----------------------------------------------------------------*/
1207         t_wr_ns = 0;
1208         cas_2_0_available = TRUE;
1209         cas_2_5_available = TRUE;
1210         cas_3_0_available = TRUE;
1211         cas_4_0_available = TRUE;
1212         cas_5_0_available = TRUE;
1213         max_2_0_tcyc_ns_x_100 = 10;
1214         max_2_5_tcyc_ns_x_100 = 10;
1215         max_3_0_tcyc_ns_x_100 = 10;
1216         max_4_0_tcyc_ns_x_100 = 10;
1217         max_5_0_tcyc_ns_x_100 = 10;
1218         sdram_ddr1 = TRUE;
1219
1220         /* loop through all the DIMM slots on the board */
1221         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1222                 /* If a dimm is installed in a particular slot ... */
1223                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1224                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1225                                 sdram_ddr1 = TRUE;
1226                         else
1227                                 sdram_ddr1 = FALSE;
1228
1229                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1230                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1231
1232                         /* For a particular DIMM, grab the three CAS values it supports */
1233                         for (cas_index = 0; cas_index < 3; cas_index++) {
1234                                 switch (cas_index) {
1235                                 case 0:
1236                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1237                                         break;
1238                                 case 1:
1239                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1240                                         break;
1241                                 default:
1242                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1243                                         break;
1244                                 }
1245
1246                                 if ((tcyc_reg & 0x0F) >= 10) {
1247                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1248                                                 /* Convert from hex to decimal */
1249                                                 cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1250                                         } else {
1251                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1252                                                        "in slot %d\n", (unsigned int)dimm_num);
1253                                                 hang();
1254                                         }
1255                                 } else {
1256                                         /* Convert from hex to decimal */
1257                                         cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) +
1258                                                 ((tcyc_reg & 0x0F)*10);
1259                                 }
1260                         }
1261
1262                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1263                         /* supported for a particular DIMM. */
1264                         cas_index = 0;
1265
1266                         if (sdram_ddr1) {
1267                                 /*
1268                                  * DDR devices use the following bitmask for CAS latency:
1269                                  *  Bit   7    6    5    4    3    2    1    0
1270                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1271                                  */
1272                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1273                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1274                                         cas_index++;
1275                                 } else {
1276                                         if (cas_index != 0)
1277                                                 cas_index++;
1278                                         cas_4_0_available = FALSE;
1279                                 }
1280
1281                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1282                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1283                                         cas_index++;
1284                                 } else {
1285                                         if (cas_index != 0)
1286                                                 cas_index++;
1287                                         cas_3_0_available = FALSE;
1288                                 }
1289
1290                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1291                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1292                                         cas_index++;
1293                                 } else {
1294                                         if (cas_index != 0)
1295                                                 cas_index++;
1296                                         cas_2_5_available = FALSE;
1297                                 }
1298
1299                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1300                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1301                                         cas_index++;
1302                                 } else {
1303                                         if (cas_index != 0)
1304                                                 cas_index++;
1305                                         cas_2_0_available = FALSE;
1306                                 }
1307                         } else {
1308                                 /*
1309                                  * DDR2 devices use the following bitmask for CAS latency:
1310                                  *  Bit   7    6    5    4    3    2    1    0
1311                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1312                                  */
1313                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1314                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1315                                         cas_index++;
1316                                 } else {
1317                                         if (cas_index != 0)
1318                                                 cas_index++;
1319                                         cas_5_0_available = FALSE;
1320                                 }
1321
1322                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1323                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1324                                         cas_index++;
1325                                 } else {
1326                                         if (cas_index != 0)
1327                                                 cas_index++;
1328                                         cas_4_0_available = FALSE;
1329                                 }
1330
1331                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
1332                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
1333                                         cas_index++;
1334                                 } else {
1335                                         if (cas_index != 0)
1336                                                 cas_index++;
1337                                         cas_3_0_available = FALSE;
1338                                 }
1339                         }
1340                 }
1341         }
1342
1343         /*------------------------------------------------------------------
1344          * Set the SDRAM mode, SDRAM_MMODE
1345          *-----------------------------------------------------------------*/
1346         mfsdram(SDRAM_MMODE, mmode);
1347         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1348
1349         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100);
1350         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100);
1351         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100);
1352         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100);
1353         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100);
1354
1355         if (sdram_ddr1 == TRUE) { /* DDR1 */
1356                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1357                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1358                         *selected_cas = DDR_CAS_2;
1359                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1360                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1361                         *selected_cas = DDR_CAS_2_5;
1362                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1363                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1364                         *selected_cas = DDR_CAS_3;
1365                 } else {
1366                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1367                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1368                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1369                         hang();
1370                 }
1371         } else { /* DDR2 */
1372                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1373                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1374                         *selected_cas = DDR_CAS_3;
1375                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1376                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1377                         *selected_cas = DDR_CAS_4;
1378                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1379                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1380                         *selected_cas = DDR_CAS_5;
1381                 } else {
1382                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1383                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1384                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1385                         hang();
1386                 }
1387         }
1388
1389         if (sdram_ddr1 == TRUE)
1390                 mmode |= SDRAM_MMODE_WR_DDR1;
1391         else {
1392
1393                 /* loop through all the DIMM slots on the board */
1394                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1395                         /* If a dimm is installed in a particular slot ... */
1396                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1397                                 t_wr_ns = max(t_wr_ns,
1398                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1399                 }
1400
1401                 /*
1402                  * convert from nanoseconds to ddr clocks
1403                  * round up if necessary
1404                  */
1405                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1406                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1407                 if (sdram_freq != ddr_check)
1408                         t_wr_clk++;
1409
1410                 switch (t_wr_clk) {
1411                 case 0:
1412                 case 1:
1413                 case 2:
1414                 case 3:
1415                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1416                         break;
1417                 case 4:
1418                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1419                         break;
1420                 case 5:
1421                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1422                         break;
1423                 default:
1424                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1425                         break;
1426                 }
1427         }
1428
1429         mtsdram(SDRAM_MMODE, mmode);
1430 }
1431
1432 /*-----------------------------------------------------------------------------+
1433  * program_rtr.
1434  *-----------------------------------------------------------------------------*/
1435 static void program_rtr(unsigned long *dimm_populated,
1436                         unsigned char *iic0_dimm_addr,
1437                         unsigned long num_dimm_banks)
1438 {
1439         PPC440_SYS_INFO board_cfg;
1440         unsigned long max_refresh_rate;
1441         unsigned long dimm_num;
1442         unsigned long refresh_rate_type;
1443         unsigned long refresh_rate;
1444         unsigned long rint;
1445         unsigned long sdram_freq;
1446         unsigned long sdr_ddrpll;
1447         unsigned long val;
1448
1449         /*------------------------------------------------------------------
1450          * Get the board configuration info.
1451          *-----------------------------------------------------------------*/
1452         get_sys_info(&board_cfg);
1453
1454         /*------------------------------------------------------------------
1455          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1456          *-----------------------------------------------------------------*/
1457         mfsdr(sdr_ddr0, sdr_ddrpll);
1458         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1459
1460         max_refresh_rate = 0;
1461         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1462                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1463
1464                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1465                         refresh_rate_type &= 0x7F;
1466                         switch (refresh_rate_type) {
1467                         case 0:
1468                                 refresh_rate =  15625;
1469                                 break;
1470                         case 1:
1471                                 refresh_rate =   3906;
1472                                 break;
1473                         case 2:
1474                                 refresh_rate =   7812;
1475                                 break;
1476                         case 3:
1477                                 refresh_rate =  31250;
1478                                 break;
1479                         case 4:
1480                                 refresh_rate =  62500;
1481                                 break;
1482                         case 5:
1483                                 refresh_rate = 125000;
1484                                 break;
1485                         default:
1486                                 refresh_rate = 0;
1487                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1488                                        (unsigned int)dimm_num);
1489                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1490                                 hang();
1491                                 break;
1492                         }
1493
1494                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1495                 }
1496         }
1497
1498         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1499         mfsdram(SDRAM_RTR, val);
1500         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1501                 (SDRAM_RTR_RINT_ENCODE(rint)));
1502 }
1503
1504 /*------------------------------------------------------------------
1505  * This routine programs the SDRAM_TRx registers.
1506  *-----------------------------------------------------------------*/
1507 static void program_tr(unsigned long *dimm_populated,
1508                        unsigned char *iic0_dimm_addr,
1509                        unsigned long num_dimm_banks)
1510 {
1511         unsigned long dimm_num;
1512         unsigned long sdram_ddr1;
1513         unsigned long t_rp_ns;
1514         unsigned long t_rcd_ns;
1515         unsigned long t_rrd_ns;
1516         unsigned long t_ras_ns;
1517         unsigned long t_rc_ns;
1518         unsigned long t_rfc_ns;
1519         unsigned long t_wpc_ns;
1520         unsigned long t_wtr_ns;
1521         unsigned long t_rpc_ns;
1522         unsigned long t_rp_clk;
1523         unsigned long t_rcd_clk;
1524         unsigned long t_rrd_clk;
1525         unsigned long t_ras_clk;
1526         unsigned long t_rc_clk;
1527         unsigned long t_rfc_clk;
1528         unsigned long t_wpc_clk;
1529         unsigned long t_wtr_clk;
1530         unsigned long t_rpc_clk;
1531         unsigned long sdtr1, sdtr2, sdtr3;
1532         unsigned long ddr_check;
1533         unsigned long sdram_freq;
1534         unsigned long sdr_ddrpll;
1535
1536         PPC440_SYS_INFO board_cfg;
1537
1538         /*------------------------------------------------------------------
1539          * Get the board configuration info.
1540          *-----------------------------------------------------------------*/
1541         get_sys_info(&board_cfg);
1542
1543         mfsdr(sdr_ddr0, sdr_ddrpll);
1544         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1545
1546         /*------------------------------------------------------------------
1547          * Handle the timing.  We need to find the worst case timing of all
1548          * the dimm modules installed.
1549          *-----------------------------------------------------------------*/
1550         t_rp_ns = 0;
1551         t_rrd_ns = 0;
1552         t_rcd_ns = 0;
1553         t_ras_ns = 0;
1554         t_rc_ns = 0;
1555         t_rfc_ns = 0;
1556         t_wpc_ns = 0;
1557         t_wtr_ns = 0;
1558         t_rpc_ns = 0;
1559         sdram_ddr1 = TRUE;
1560
1561         /* loop through all the DIMM slots on the board */
1562         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1563                 /* If a dimm is installed in a particular slot ... */
1564                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1565                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1566                                 sdram_ddr1 = TRUE;
1567                         else
1568                                 sdram_ddr1 = FALSE;
1569
1570                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1571                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1572                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1573                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1574                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1575                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1576                 }
1577         }
1578
1579         /*------------------------------------------------------------------
1580          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1581          *-----------------------------------------------------------------*/
1582         mfsdram(SDRAM_SDTR1, sdtr1);
1583         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1584                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1585
1586         /* default values */
1587         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1588         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1589
1590         /* normal operations */
1591         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1592         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1593
1594         mtsdram(SDRAM_SDTR1, sdtr1);
1595
1596         /*------------------------------------------------------------------
1597          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1598          *-----------------------------------------------------------------*/
1599         mfsdram(SDRAM_SDTR2, sdtr2);
1600         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1601                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1602                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1603                    SDRAM_SDTR2_RRD_MASK);
1604
1605         /*
1606          * convert t_rcd from nanoseconds to ddr clocks
1607          * round up if necessary
1608          */
1609         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1610         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1611         if (sdram_freq != ddr_check)
1612                 t_rcd_clk++;
1613
1614         switch (t_rcd_clk) {
1615         case 0:
1616         case 1:
1617                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1618                 break;
1619         case 2:
1620                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1621                 break;
1622         case 3:
1623                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1624                 break;
1625         case 4:
1626                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1627                 break;
1628         default:
1629                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1630                 break;
1631         }
1632
1633         if (sdram_ddr1 == TRUE) { /* DDR1 */
1634                 if (sdram_freq < 200000000) {
1635                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1636                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1637                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1638                 } else {
1639                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1640                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1641                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1642                 }
1643         } else { /* DDR2 */
1644                 /* loop through all the DIMM slots on the board */
1645                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1646                         /* If a dimm is installed in a particular slot ... */
1647                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1648                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1649                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1650                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1651                         }
1652                 }
1653
1654                 /*
1655                  * convert from nanoseconds to ddr clocks
1656                  * round up if necessary
1657                  */
1658                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1659                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1660                 if (sdram_freq != ddr_check)
1661                         t_wpc_clk++;
1662
1663                 switch (t_wpc_clk) {
1664                 case 0:
1665                 case 1:
1666                 case 2:
1667                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1668                         break;
1669                 case 3:
1670                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1671                         break;
1672                 case 4:
1673                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1674                         break;
1675                 case 5:
1676                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1677                         break;
1678                 default:
1679                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1680                         break;
1681                 }
1682
1683                 /*
1684                  * convert from nanoseconds to ddr clocks
1685                  * round up if necessary
1686                  */
1687                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1688                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1689                 if (sdram_freq != ddr_check)
1690                         t_wtr_clk++;
1691
1692                 switch (t_wtr_clk) {
1693                 case 0:
1694                 case 1:
1695                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1696                         break;
1697                 case 2:
1698                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1699                         break;
1700                 case 3:
1701                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1702                         break;
1703                 default:
1704                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1705                         break;
1706                 }
1707
1708                 /*
1709                  * convert from nanoseconds to ddr clocks
1710                  * round up if necessary
1711                  */
1712                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1713                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1714                 if (sdram_freq != ddr_check)
1715                         t_rpc_clk++;
1716
1717                 switch (t_rpc_clk) {
1718                 case 0:
1719                 case 1:
1720                 case 2:
1721                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1722                         break;
1723                 case 3:
1724                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1725                         break;
1726                 default:
1727                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1728                         break;
1729                 }
1730         }
1731
1732         /* default value */
1733         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1734
1735         /*
1736          * convert t_rrd from nanoseconds to ddr clocks
1737          * round up if necessary
1738          */
1739         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1740         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1741         if (sdram_freq != ddr_check)
1742                 t_rrd_clk++;
1743
1744         if (t_rrd_clk == 3)
1745                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1746         else
1747                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1748
1749         /*
1750          * convert t_rp from nanoseconds to ddr clocks
1751          * round up if necessary
1752          */
1753         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1754         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1755         if (sdram_freq != ddr_check)
1756                 t_rp_clk++;
1757
1758         switch (t_rp_clk) {
1759         case 0:
1760         case 1:
1761         case 2:
1762         case 3:
1763                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1764                 break;
1765         case 4:
1766                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1767                 break;
1768         case 5:
1769                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1770                 break;
1771         case 6:
1772                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1773                 break;
1774         default:
1775                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1776                 break;
1777         }
1778
1779         mtsdram(SDRAM_SDTR2, sdtr2);
1780
1781         /*------------------------------------------------------------------
1782          * Set the SDRAM Timing Reg 3, SDRAM_TR3
1783          *-----------------------------------------------------------------*/
1784         mfsdram(SDRAM_SDTR3, sdtr3);
1785         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
1786                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1787
1788         /*
1789          * convert t_ras from nanoseconds to ddr clocks
1790          * round up if necessary
1791          */
1792         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1793         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1794         if (sdram_freq != ddr_check)
1795                 t_ras_clk++;
1796
1797         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1798
1799         /*
1800          * convert t_rc from nanoseconds to ddr clocks
1801          * round up if necessary
1802          */
1803         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1804         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1805         if (sdram_freq != ddr_check)
1806                 t_rc_clk++;
1807
1808         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1809
1810         /* default xcs value */
1811         sdtr3 |= SDRAM_SDTR3_XCS;
1812
1813         /*
1814          * convert t_rfc from nanoseconds to ddr clocks
1815          * round up if necessary
1816          */
1817         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1818         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
1819         if (sdram_freq != ddr_check)
1820                 t_rfc_clk++;
1821
1822         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
1823
1824         mtsdram(SDRAM_SDTR3, sdtr3);
1825 }
1826
1827 /*-----------------------------------------------------------------------------+
1828  * program_bxcf.
1829  *-----------------------------------------------------------------------------*/
1830 static void program_bxcf(unsigned long *dimm_populated,
1831                          unsigned char *iic0_dimm_addr,
1832                          unsigned long num_dimm_banks)
1833 {
1834         unsigned long dimm_num;
1835         unsigned long num_col_addr;
1836         unsigned long num_ranks;
1837         unsigned long num_banks;
1838         unsigned long mode;
1839         unsigned long ind_rank;
1840         unsigned long ind;
1841         unsigned long ind_bank;
1842         unsigned long bank_0_populated;
1843
1844         /*------------------------------------------------------------------
1845          * Set the BxCF regs.  First, wipe out the bank config registers.
1846          *-----------------------------------------------------------------*/
1847         mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
1848         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1849         mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
1850         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1851         mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
1852         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1853         mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
1854         mtdcr(SDRAMC_CFGDATA, 0x00000000);
1855
1856         mode = SDRAM_BXCF_M_BE_ENABLE;
1857
1858         bank_0_populated = 0;
1859
1860         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1861                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1862                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1863                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
1864                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
1865                                 num_ranks = (num_ranks & 0x0F) +1;
1866                         else
1867                                 num_ranks = num_ranks & 0x0F;
1868
1869                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
1870
1871                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
1872                                 if (num_banks == 4)
1873                                         ind = 0;
1874                                 else
1875                                         ind = 5;
1876                                 switch (num_col_addr) {
1877                                 case 0x08:
1878                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
1879                                         break;
1880                                 case 0x09:
1881                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
1882                                         break;
1883                                 case 0x0A:
1884                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
1885                                         break;
1886                                 case 0x0B:
1887                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
1888                                         break;
1889                                 case 0x0C:
1890                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
1891                                         break;
1892                                 default:
1893                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
1894                                                (unsigned int)dimm_num);
1895                                         printf("ERROR: Unsupported value for number of "
1896                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
1897                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
1898                                         hang();
1899                                 }
1900                         }
1901
1902                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
1903                                 bank_0_populated = 1;
1904
1905                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
1906                                 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
1907                                 mtdcr(SDRAMC_CFGDATA, mode);
1908                         }
1909                 }
1910         }
1911 }
1912
1913 /*------------------------------------------------------------------
1914  * program memory queue.
1915  *-----------------------------------------------------------------*/
1916 static void program_memory_queue(unsigned long *dimm_populated,
1917                                  unsigned char *iic0_dimm_addr,
1918                                  unsigned long num_dimm_banks)
1919 {
1920         unsigned long dimm_num;
1921         unsigned long rank_base_addr;
1922         unsigned long rank_reg;
1923         unsigned long rank_size_bytes;
1924         unsigned long rank_size_id;
1925         unsigned long num_ranks;
1926         unsigned long baseadd_size;
1927         unsigned long i;
1928         unsigned long bank_0_populated = 0;
1929
1930         /*------------------------------------------------------------------
1931          * Reset the rank_base_address.
1932          *-----------------------------------------------------------------*/
1933         rank_reg   = SDRAM_R0BAS;
1934
1935         rank_base_addr = 0x00000000;
1936
1937         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1938                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1939                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
1940                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
1941                                 num_ranks = (num_ranks & 0x0F) + 1;
1942                         else
1943                                 num_ranks = num_ranks & 0x0F;
1944
1945                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1946
1947                         /*------------------------------------------------------------------
1948                          * Set the sizes
1949                          *-----------------------------------------------------------------*/
1950                         baseadd_size = 0;
1951                         rank_size_bytes = 1024 * 1024 * rank_size_id;
1952                         switch (rank_size_id) {
1953                         case 0x02:
1954                                 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
1955                                 break;
1956                         case 0x04:
1957                                 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
1958                                 break;
1959                         case 0x08:
1960                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
1961                                 break;
1962                         case 0x10:
1963                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
1964                                 break;
1965                         case 0x20:
1966                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
1967                                 break;
1968                         case 0x40:
1969                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
1970                                 break;
1971                         case 0x80:
1972                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
1973                                 break;
1974                         default:
1975                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
1976                                        (unsigned int)dimm_num);
1977                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1978                                        (unsigned int)rank_size_id);
1979                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1980                                 hang();
1981                         }
1982
1983                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
1984                                 bank_0_populated = 1;
1985
1986                         for (i = 0; i < num_ranks; i++) {
1987                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
1988                                           (rank_base_addr & SDRAM_RXBAS_SDBA_MASK) |
1989                                           baseadd_size);
1990                                 rank_base_addr += rank_size_bytes;
1991                         }
1992                 }
1993         }
1994 }
1995
1996 /*-----------------------------------------------------------------------------+
1997  * is_ecc_enabled.
1998  *-----------------------------------------------------------------------------*/
1999 static unsigned long is_ecc_enabled(void)
2000 {
2001         unsigned long dimm_num;
2002         unsigned long ecc;
2003         unsigned long val;
2004
2005         ecc = 0;
2006         /* loop through all the DIMM slots on the board */
2007         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2008                 mfsdram(SDRAM_MCOPT1, val);
2009                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2010         }
2011
2012         return(ecc);
2013 }
2014
2015 /*-----------------------------------------------------------------------------+
2016  * program_ecc.
2017  *-----------------------------------------------------------------------------*/
2018 static void program_ecc(unsigned long *dimm_populated,
2019                         unsigned char *iic0_dimm_addr,
2020                         unsigned long num_dimm_banks)
2021 {
2022         unsigned long mcopt1;
2023         unsigned long mcopt2;
2024         unsigned long mcstat;
2025         unsigned long dimm_num;
2026         unsigned long ecc;
2027
2028         ecc = 0;
2029         /* loop through all the DIMM slots on the board */
2030         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2031                 /* If a dimm is installed in a particular slot ... */
2032                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2033                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2034         }
2035         if (ecc == 0)
2036                 return;
2037
2038         mfsdram(SDRAM_MCOPT1, mcopt1);
2039         mfsdram(SDRAM_MCOPT2, mcopt2);
2040
2041         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2042                 /* DDR controller must be enabled and not in self-refresh. */
2043                 mfsdram(SDRAM_MCSTAT, mcstat);
2044                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2045                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2046                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2047                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2048
2049                         program_ecc_addr(0, sdram_memsize());
2050                 }
2051         }
2052
2053         return;
2054 }
2055
2056 /*-----------------------------------------------------------------------------+
2057  * program_ecc_addr.
2058  *-----------------------------------------------------------------------------*/
2059 static void program_ecc_addr(unsigned long start_address,
2060                              unsigned long num_bytes)
2061 {
2062         unsigned long current_address;
2063         unsigned long end_address;
2064         unsigned long address_increment;
2065         unsigned long mcopt1;
2066
2067         current_address = start_address;
2068         mfsdram(SDRAM_MCOPT1, mcopt1);
2069         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2070                 mtsdram(SDRAM_MCOPT1,
2071                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2072                 sync();
2073                 eieio();
2074                 wait_ddr_idle();
2075
2076                 /* ECC bit set method for non-cached memory */
2077                 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2078                         address_increment = 4;
2079                 else
2080                         address_increment = 8;
2081                 end_address = current_address + num_bytes;
2082
2083                 while (current_address < end_address) {
2084                         *((unsigned long *)current_address) = 0x00000000;
2085                         current_address += address_increment;
2086                 }
2087                 sync();
2088                 eieio();
2089                 wait_ddr_idle();
2090
2091                 mtsdram(SDRAM_MCOPT1,
2092                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK);
2093                 sync();
2094                 eieio();
2095                 wait_ddr_idle();
2096         }
2097 }
2098
2099 /*-----------------------------------------------------------------------------+
2100  * program_DQS_calibration.
2101  *-----------------------------------------------------------------------------*/
2102 static void program_DQS_calibration(unsigned long *dimm_populated,
2103                                     unsigned char *iic0_dimm_addr,
2104                                     unsigned long num_dimm_banks)
2105 {
2106         unsigned long val;
2107
2108 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2109         mtsdram(SDRAM_RQDC, 0x80000037);
2110         mtsdram(SDRAM_RDCC, 0x40000000);
2111         mtsdram(SDRAM_RFDC, 0x000001DF);
2112
2113         test();
2114 #else
2115         /*------------------------------------------------------------------
2116          * Program RDCC register
2117          * Read sample cycle auto-update enable
2118          *-----------------------------------------------------------------*/
2119
2120         /*
2121          * Modified for the Katmai platform:  with some DIMMs, the DDR2
2122          * controller automatically selects the T2 read cycle, but this
2123          * proves unreliable.  Go ahead and force the DDR2 controller
2124          * to use the T4 sample and disable the automatic update of the
2125          * RDSS field.
2126          */
2127         mfsdram(SDRAM_RDCC, val);
2128         mtsdram(SDRAM_RDCC,
2129                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2130                 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2131
2132         /*------------------------------------------------------------------
2133          * Program RQDC register
2134          * Internal DQS delay mechanism enable
2135          *-----------------------------------------------------------------*/
2136         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2137
2138         /*------------------------------------------------------------------
2139          * Program RFDC register
2140          * Set Feedback Fractional Oversample
2141          * Auto-detect read sample cycle enable
2142          *-----------------------------------------------------------------*/
2143         mfsdram(SDRAM_RFDC, val);
2144         mtsdram(SDRAM_RFDC,
2145                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2146                          SDRAM_RFDC_RFFD_MASK))
2147                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2148                    SDRAM_RFDC_RFFD_ENCODE(0)));
2149
2150         DQS_calibration_process();
2151 #endif
2152 }
2153
2154 static u32 short_mem_test(void)
2155 {
2156         u32 *membase;
2157         u32 bxcr_num;
2158         u32 bxcf;
2159         int i;
2160         int j;
2161         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2162                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2163                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2164                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2165                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2166                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2167                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2168                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2169                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2170                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2171                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2172                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2173                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2174                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2175                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2176                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2177                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2178
2179         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2180                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2181
2182                 /* Banks enabled */
2183                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2184
2185                         /* Bank is enabled */
2186                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2187
2188                         /*------------------------------------------------------------------
2189                          * Run the short memory test.
2190                          *-----------------------------------------------------------------*/
2191                         for (i = 0; i < NUMMEMTESTS; i++) {
2192                                 for (j = 0; j < NUMMEMWORDS; j++) {
2193                                         membase[j] = test[i][j];
2194                                         ppcDcbf((u32)&(membase[j]));
2195                                 }
2196                                 sync();
2197                                 for (j = 0; j < NUMMEMWORDS; j++) {
2198                                         if (membase[j] != test[i][j]) {
2199                                                 ppcDcbf((u32)&(membase[j]));
2200                                                 break;
2201                                         }
2202                                         ppcDcbf((u32)&(membase[j]));
2203                                 }
2204                                 sync();
2205                                 if (j < NUMMEMWORDS)
2206                                         break;
2207                         }
2208                         if (i < NUMMEMTESTS)
2209                                 break;
2210                 }       /* if bank enabled */
2211         }               /* for bxcf_num */
2212
2213         return bxcr_num;
2214 }
2215
2216 #ifndef HARD_CODED_DQS
2217 /*-----------------------------------------------------------------------------+
2218  * DQS_calibration_process.
2219  *-----------------------------------------------------------------------------*/
2220 static void DQS_calibration_process(void)
2221 {
2222         unsigned long ecc_temp;
2223         unsigned long rfdc_reg;
2224         unsigned long rffd;
2225         unsigned long rqdc_reg;
2226         unsigned long rqfd;
2227         unsigned long bxcr_num;
2228         unsigned long val;
2229         long rqfd_average;
2230         long rffd_average;
2231         long max_start;
2232         long min_end;
2233         unsigned long begin_rqfd[MAXRANKS];
2234         unsigned long begin_rffd[MAXRANKS];
2235         unsigned long end_rqfd[MAXRANKS];
2236         unsigned long end_rffd[MAXRANKS];
2237         char window_found;
2238         unsigned long dlycal;
2239         unsigned long dly_val;
2240         unsigned long max_pass_length;
2241         unsigned long current_pass_length;
2242         unsigned long current_fail_length;
2243         unsigned long current_start;
2244         long max_end;
2245         unsigned char fail_found;
2246         unsigned char pass_found;
2247
2248         /*------------------------------------------------------------------
2249          * Test to determine the best read clock delay tuning bits.
2250          *
2251          * Before the DDR controller can be used, the read clock delay needs to be
2252          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2253          * This value cannot be hardcoded into the program because it changes
2254          * depending on the board's setup and environment.
2255          * To do this, all delay values are tested to see if they
2256          * work or not.  By doing this, you get groups of fails with groups of
2257          * passing values.  The idea is to find the start and end of a passing
2258          * window and take the center of it to use as the read clock delay.
2259          *
2260          * A failure has to be seen first so that when we hit a pass, we know
2261          * that it is truely the start of the window.  If we get passing values
2262          * to start off with, we don't know if we are at the start of the window.
2263          *
2264          * The code assumes that a failure will always be found.
2265          * If a failure is not found, there is no easy way to get the middle
2266          * of the passing window.  I guess we can pretty much pick any value
2267          * but some values will be better than others.  Since the lowest speed
2268          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2269          * from experimentation it is safe to say you will always have a failure.
2270          *-----------------------------------------------------------------*/
2271         mfsdram(SDRAM_MCOPT1, ecc_temp);
2272         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2273         mfsdram(SDRAM_MCOPT1, val);
2274         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2275                 SDRAM_MCOPT1_MCHK_NON);
2276
2277         max_start = 0;
2278         min_end = 0;
2279         begin_rqfd[0] = 0;
2280         begin_rffd[0] = 0;
2281         begin_rqfd[1] = 0;
2282         begin_rffd[1] = 0;
2283         end_rqfd[0] = 0;
2284         end_rffd[0] = 0;
2285         end_rqfd[1] = 0;
2286         end_rffd[1] = 0;
2287         window_found = FALSE;
2288
2289         max_pass_length = 0;
2290         max_start = 0;
2291         max_end = 0;
2292         current_pass_length = 0;
2293         current_fail_length = 0;
2294         current_start = 0;
2295         window_found = FALSE;
2296         fail_found = FALSE;
2297         pass_found = FALSE;
2298
2299         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2300         /* rqdc_reg = mfsdram(SDRAM_RQDC) & ~(SDRAM_RQDC_RQFD_MASK); */
2301
2302         /*
2303          * get the delay line calibration register value
2304          */
2305         mfsdram(SDRAM_DLCR, dlycal);
2306         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2307
2308         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2309                 mfsdram(SDRAM_RFDC, rfdc_reg);
2310                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2311
2312                 /*------------------------------------------------------------------
2313                  * Set the timing reg for the test.
2314                  *-----------------------------------------------------------------*/
2315                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2316
2317                 /* do the small memory test */
2318                 bxcr_num = short_mem_test();
2319
2320                 /*------------------------------------------------------------------
2321                  * See if the rffd value passed.
2322                  *-----------------------------------------------------------------*/
2323                 if (bxcr_num == MAXBXCF) {
2324                         if (fail_found == TRUE) {
2325                                 pass_found = TRUE;
2326                                 if (current_pass_length == 0)
2327                                         current_start = rffd;
2328
2329                                 current_fail_length = 0;
2330                                 current_pass_length++;
2331
2332                                 if (current_pass_length > max_pass_length) {
2333                                         max_pass_length = current_pass_length;
2334                                         max_start = current_start;
2335                                         max_end = rffd;
2336                                 }
2337                         }
2338                 } else {
2339                         current_pass_length = 0;
2340                         current_fail_length++;
2341
2342                         if (current_fail_length >= (dly_val >> 2)) {
2343                                 if (fail_found == FALSE) {
2344                                         fail_found = TRUE;
2345                                 } else if (pass_found == TRUE) {
2346                                         window_found = TRUE;
2347                                         break;
2348                                 }
2349                         }
2350                 }
2351         }               /* for rffd */
2352
2353
2354         /*------------------------------------------------------------------
2355          * Set the average RFFD value
2356          *-----------------------------------------------------------------*/
2357         rffd_average = ((max_start + max_end) >> 1);
2358
2359         if (rffd_average < 0)
2360                 rffd_average = 0;
2361
2362         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2363                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2364         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2365         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2366
2367         max_pass_length = 0;
2368         max_start = 0;
2369         max_end = 0;
2370         current_pass_length = 0;
2371         current_fail_length = 0;
2372         current_start = 0;
2373         window_found = FALSE;
2374         fail_found = FALSE;
2375         pass_found = FALSE;
2376
2377         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2378                 mfsdram(SDRAM_RQDC, rqdc_reg);
2379                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2380
2381                 /*------------------------------------------------------------------
2382                  * Set the timing reg for the test.
2383                  *-----------------------------------------------------------------*/
2384                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2385
2386                 /* do the small memory test */
2387                 bxcr_num = short_mem_test();
2388
2389                 /*------------------------------------------------------------------
2390                  * See if the rffd value passed.
2391                  *-----------------------------------------------------------------*/
2392                 if (bxcr_num == MAXBXCF) {
2393                         if (fail_found == TRUE) {
2394                                 pass_found = TRUE;
2395                                 if (current_pass_length == 0)
2396                                         current_start = rqfd;
2397
2398                                 current_fail_length = 0;
2399                                 current_pass_length++;
2400
2401                                 if (current_pass_length > max_pass_length) {
2402                                         max_pass_length = current_pass_length;
2403                                         max_start = current_start;
2404                                         max_end = rqfd;
2405                                 }
2406                         }
2407                 } else {
2408                         current_pass_length = 0;
2409                         current_fail_length++;
2410
2411                         if (fail_found == FALSE) {
2412                                 fail_found = TRUE;
2413                         } else if (pass_found == TRUE) {
2414                                 window_found = TRUE;
2415                                 break;
2416                         }
2417                 }
2418         }
2419
2420         /*------------------------------------------------------------------
2421          * Make sure we found the valid read passing window.  Halt if not
2422          *-----------------------------------------------------------------*/
2423         if (window_found == FALSE) {
2424                 printf("ERROR: Cannot determine a common read delay for the "
2425                        "DIMM(s) installed.\n");
2426                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2427                 hang();
2428         }
2429
2430         rqfd_average = ((max_start + max_end) >> 1);
2431
2432         if (rqfd_average < 0)
2433                 rqfd_average = 0;
2434
2435         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2436                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2437
2438         /*------------------------------------------------------------------
2439          * Restore the ECC variable to what it originally was
2440          *-----------------------------------------------------------------*/
2441         mfsdram(SDRAM_MCOPT1, val);
2442         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | ecc_temp);
2443
2444         mtsdram(SDRAM_RQDC,
2445                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2446                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2447
2448         mfsdram(SDRAM_DLCR, val);
2449         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2450         mfsdram(SDRAM_RQDC, val);
2451         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2452         mfsdram(SDRAM_RFDC, val);
2453         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2454 }
2455 #else /* calibration test with hardvalues */
2456 /*-----------------------------------------------------------------------------+
2457  * DQS_calibration_process.
2458  *-----------------------------------------------------------------------------*/
2459 static void test(void)
2460 {
2461         unsigned long dimm_num;
2462         unsigned long ecc_temp;
2463         unsigned long i, j;
2464         unsigned long *membase;
2465         unsigned long bxcf[MAXRANKS];
2466         unsigned long val;
2467         char window_found;
2468         char begin_found[MAXDIMMS];
2469         char end_found[MAXDIMMS];
2470         char search_end[MAXDIMMS];
2471         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2472                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2473                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2474                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2475                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2476                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2477                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2478                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2479                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2480                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2481                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2482                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2483                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2484                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2485                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2486                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2487                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2488
2489         /*------------------------------------------------------------------
2490          * Test to determine the best read clock delay tuning bits.
2491          *
2492          * Before the DDR controller can be used, the read clock delay needs to be
2493          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2494          * This value cannot be hardcoded into the program because it changes
2495          * depending on the board's setup and environment.
2496          * To do this, all delay values are tested to see if they
2497          * work or not.  By doing this, you get groups of fails with groups of
2498          * passing values.  The idea is to find the start and end of a passing
2499          * window and take the center of it to use as the read clock delay.
2500          *
2501          * A failure has to be seen first so that when we hit a pass, we know
2502          * that it is truely the start of the window.  If we get passing values
2503          * to start off with, we don't know if we are at the start of the window.
2504          *
2505          * The code assumes that a failure will always be found.
2506          * If a failure is not found, there is no easy way to get the middle
2507          * of the passing window.  I guess we can pretty much pick any value
2508          * but some values will be better than others.  Since the lowest speed
2509          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2510          * from experimentation it is safe to say you will always have a failure.
2511          *-----------------------------------------------------------------*/
2512         mfsdram(SDRAM_MCOPT1, ecc_temp);
2513         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2514         mfsdram(SDRAM_MCOPT1, val);
2515         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2516                 SDRAM_MCOPT1_MCHK_NON);
2517
2518         window_found = FALSE;
2519         begin_found[0] = FALSE;
2520         end_found[0] = FALSE;
2521         search_end[0] = FALSE;
2522         begin_found[1] = FALSE;
2523         end_found[1] = FALSE;
2524         search_end[1] = FALSE;
2525
2526         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2527                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2528
2529                 /* Banks enabled */
2530                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2531
2532                         /* Bank is enabled */
2533                         membase =
2534                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2535
2536                         /*------------------------------------------------------------------
2537                          * Run the short memory test.
2538                          *-----------------------------------------------------------------*/
2539                         for (i = 0; i < NUMMEMTESTS; i++) {
2540                                 for (j = 0; j < NUMMEMWORDS; j++) {
2541                                         membase[j] = test[i][j];
2542                                         ppcDcbf((u32)&(membase[j]));
2543                                 }
2544                                 sync();
2545                                 for (j = 0; j < NUMMEMWORDS; j++) {
2546                                         if (membase[j] != test[i][j]) {
2547                                                 ppcDcbf((u32)&(membase[j]));
2548                                                 break;
2549                                         }
2550                                         ppcDcbf((u32)&(membase[j]));
2551                                 }
2552                                 sync();
2553                                 if (j < NUMMEMWORDS)
2554                                         break;
2555                         }
2556
2557                         /*------------------------------------------------------------------
2558                          * See if the rffd value passed.
2559                          *-----------------------------------------------------------------*/
2560                         if (i < NUMMEMTESTS) {
2561                                 if ((end_found[dimm_num] == FALSE) &&
2562                                     (search_end[dimm_num] == TRUE)) {
2563                                         end_found[dimm_num] = TRUE;
2564                                 }
2565                                 if ((end_found[0] == TRUE) &&
2566                                     (end_found[1] == TRUE))
2567                                         break;
2568                         } else {
2569                                 if (begin_found[dimm_num] == FALSE) {
2570                                         begin_found[dimm_num] = TRUE;
2571                                         search_end[dimm_num] = TRUE;
2572                                 }
2573                         }
2574                 } else {
2575                         begin_found[dimm_num] = TRUE;
2576                         end_found[dimm_num] = TRUE;
2577                 }
2578         }
2579
2580         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2581                 window_found = TRUE;
2582
2583         /*------------------------------------------------------------------
2584          * Make sure we found the valid read passing window.  Halt if not
2585          *-----------------------------------------------------------------*/
2586         if (window_found == FALSE) {
2587                 printf("ERROR: Cannot determine a common read delay for the "
2588                        "DIMM(s) installed.\n");
2589                 hang();
2590         }
2591
2592         /*------------------------------------------------------------------
2593          * Restore the ECC variable to what it originally was
2594          *-----------------------------------------------------------------*/
2595         mtsdram(SDRAM_MCOPT1,
2596                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2597                 | ecc_temp);
2598 }
2599 #endif
2600
2601 #if defined(DEBUG)
2602 static void ppc440sp_sdram_register_dump(void)
2603 {
2604         unsigned int sdram_reg;
2605         unsigned int sdram_data;
2606         unsigned int dcr_data;
2607
2608         printf("\n  Register Dump:\n");
2609         sdram_reg = SDRAM_MCSTAT;
2610         mfsdram(sdram_reg, sdram_data);
2611         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2612         sdram_reg = SDRAM_MCOPT1;
2613         mfsdram(sdram_reg, sdram_data);
2614         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2615         sdram_reg = SDRAM_MCOPT2;
2616         mfsdram(sdram_reg, sdram_data);
2617         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2618         sdram_reg = SDRAM_MODT0;
2619         mfsdram(sdram_reg, sdram_data);
2620         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2621         sdram_reg = SDRAM_MODT1;
2622         mfsdram(sdram_reg, sdram_data);
2623         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2624         sdram_reg = SDRAM_MODT2;
2625         mfsdram(sdram_reg, sdram_data);
2626         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2627         sdram_reg = SDRAM_MODT3;
2628         mfsdram(sdram_reg, sdram_data);
2629         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2630         sdram_reg = SDRAM_CODT;
2631         mfsdram(sdram_reg, sdram_data);
2632         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2633         sdram_reg = SDRAM_VVPR;
2634         mfsdram(sdram_reg, sdram_data);
2635         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2636         sdram_reg = SDRAM_OPARS;
2637         mfsdram(sdram_reg, sdram_data);
2638         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2639         /*
2640          * OPAR2 is only used as a trigger register.
2641          * No data is contained in this register, and reading or writing
2642          * to is can cause bad things to happen (hangs).  Just skip it
2643          * and report NA
2644          * sdram_reg = SDRAM_OPAR2;
2645          * mfsdram(sdram_reg, sdram_data);
2646          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2647          */
2648         printf("        SDRAM_OPART     = N/A       ");
2649         sdram_reg = SDRAM_RTR;
2650         mfsdram(sdram_reg, sdram_data);
2651         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2652         sdram_reg = SDRAM_MB0CF;
2653         mfsdram(sdram_reg, sdram_data);
2654         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2655         sdram_reg = SDRAM_MB1CF;
2656         mfsdram(sdram_reg, sdram_data);
2657         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2658         sdram_reg = SDRAM_MB2CF;
2659         mfsdram(sdram_reg, sdram_data);
2660         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2661         sdram_reg = SDRAM_MB3CF;
2662         mfsdram(sdram_reg, sdram_data);
2663         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2664         sdram_reg = SDRAM_INITPLR0;
2665         mfsdram(sdram_reg, sdram_data);
2666         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2667         sdram_reg = SDRAM_INITPLR1;
2668         mfsdram(sdram_reg, sdram_data);
2669         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2670         sdram_reg = SDRAM_INITPLR2;
2671         mfsdram(sdram_reg, sdram_data);
2672         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2673         sdram_reg = SDRAM_INITPLR3;
2674         mfsdram(sdram_reg, sdram_data);
2675         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2676         sdram_reg = SDRAM_INITPLR4;
2677         mfsdram(sdram_reg, sdram_data);
2678         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2679         sdram_reg = SDRAM_INITPLR5;
2680         mfsdram(sdram_reg, sdram_data);
2681         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2682         sdram_reg = SDRAM_INITPLR6;
2683         mfsdram(sdram_reg, sdram_data);
2684         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2685         sdram_reg = SDRAM_INITPLR7;
2686         mfsdram(sdram_reg, sdram_data);
2687         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
2688         sdram_reg = SDRAM_INITPLR8;
2689         mfsdram(sdram_reg, sdram_data);
2690         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
2691         sdram_reg = SDRAM_INITPLR9;
2692         mfsdram(sdram_reg, sdram_data);
2693         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
2694         sdram_reg = SDRAM_INITPLR10;
2695         mfsdram(sdram_reg, sdram_data);
2696         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
2697         sdram_reg = SDRAM_INITPLR11;
2698         mfsdram(sdram_reg, sdram_data);
2699         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2700         sdram_reg = SDRAM_INITPLR12;
2701         mfsdram(sdram_reg, sdram_data);
2702         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
2703         sdram_reg = SDRAM_INITPLR13;
2704         mfsdram(sdram_reg, sdram_data);
2705         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2706         sdram_reg = SDRAM_INITPLR14;
2707         mfsdram(sdram_reg, sdram_data);
2708         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
2709         sdram_reg = SDRAM_INITPLR15;
2710         mfsdram(sdram_reg, sdram_data);
2711         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2712         sdram_reg = SDRAM_RQDC;
2713         mfsdram(sdram_reg, sdram_data);
2714         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
2715         sdram_reg = SDRAM_RFDC;
2716         mfsdram(sdram_reg, sdram_data);
2717         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
2718         sdram_reg = SDRAM_RDCC;
2719         mfsdram(sdram_reg, sdram_data);
2720         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
2721         sdram_reg = SDRAM_DLCR;
2722         mfsdram(sdram_reg, sdram_data);
2723         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
2724         sdram_reg = SDRAM_CLKTR;
2725         mfsdram(sdram_reg, sdram_data);
2726         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
2727         sdram_reg = SDRAM_WRDTR;
2728         mfsdram(sdram_reg, sdram_data);
2729         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
2730         sdram_reg = SDRAM_SDTR1;
2731         mfsdram(sdram_reg, sdram_data);
2732         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
2733         sdram_reg = SDRAM_SDTR2;
2734         mfsdram(sdram_reg, sdram_data);
2735         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
2736         sdram_reg = SDRAM_SDTR3;
2737         mfsdram(sdram_reg, sdram_data);
2738         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
2739         sdram_reg = SDRAM_MMODE;
2740         mfsdram(sdram_reg, sdram_data);
2741         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
2742         sdram_reg = SDRAM_MEMODE;
2743         mfsdram(sdram_reg, sdram_data);
2744         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
2745         sdram_reg = SDRAM_ECCCR;
2746         mfsdram(sdram_reg, sdram_data);
2747         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
2748
2749         dcr_data = mfdcr(SDRAM_R0BAS);
2750         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
2751         dcr_data = mfdcr(SDRAM_R1BAS);
2752         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
2753         dcr_data = mfdcr(SDRAM_R2BAS);
2754         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
2755         dcr_data = mfdcr(SDRAM_R3BAS);
2756         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
2757 }
2758 #endif
2759 #endif /* CONFIG_SPD_EEPROM */