cpu/ppc4xx/44x_spd_ddr.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr.c
   3  * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
   4  * DDR controller. Those are 440GP/GX/EP/GR.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * See file CREDITS for list of people who contributed to this
  27  * project.
  28  *
  29  * This program is free software; you can redistribute it and/or
  30  * modify it under the terms of the GNU General Public License as
  31  * published by the Free Software Foundation; either version 2 of
  32  * the License, or (at your option) any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful,
  35  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  37  * GNU General Public License for more details.
  38  *
  39  * You should have received a copy of the GNU General Public License
  40  * along with this program; if not, write to the Free Software
  41  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  42  * MA 02111-1307 USA
  43  */
  44
  45 #include <common.h>
  46 #include <asm/processor.h>
  47 #include <i2c.h>
  48 #include <ppc4xx.h>
  49
  50 #if defined(CONFIG_SPD_EEPROM) &&                                       \
  51         (defined(CONFIG_440GP) || defined(CONFIG_440GX) ||              \
  52          defined(CONFIG_440EP) || defined(CONFIG_440GR))
  53
  54 /*
  55  * Set default values
  56  */
  57 #ifndef CFG_I2C_SPEED
  58 #define CFG_I2C_SPEED   50000
  59 #endif
  60
  61 #ifndef CFG_I2C_SLAVE
  62 #define CFG_I2C_SLAVE   0xFE
  63 #endif
  64
  65 #define ONE_BILLION     1000000000
  66
  67 /*-----------------------------------------------------------------------------
  68   |  Memory Controller Options 0
  69   +-----------------------------------------------------------------------------*/
  70 #define SDRAM_CFG0_DCEN         0x80000000      /* SDRAM Controller Enable      */
  71 #define SDRAM_CFG0_MCHK_MASK    0x30000000      /* Memory data errchecking mask */
  72 #define SDRAM_CFG0_MCHK_NON     0x00000000      /* No ECC generation            */
  73 #define SDRAM_CFG0_MCHK_GEN     0x20000000      /* ECC generation               */
  74 #define SDRAM_CFG0_MCHK_CHK     0x30000000      /* ECC generation and checking  */
  75 #define SDRAM_CFG0_RDEN         0x08000000      /* Registered DIMM enable       */
  76 #define SDRAM_CFG0_PMUD         0x04000000      /* Page management unit         */
  77 #define SDRAM_CFG0_DMWD_MASK    0x02000000      /* DRAM width mask              */
  78 #define SDRAM_CFG0_DMWD_32      0x00000000      /* 32 bits                      */
  79 #define SDRAM_CFG0_DMWD_64      0x02000000      /* 64 bits                      */
  80 #define SDRAM_CFG0_UIOS_MASK    0x00C00000      /* Unused IO State              */
  81 #define SDRAM_CFG0_PDP          0x00200000      /* Page deallocation policy     */
  82
  83 /*-----------------------------------------------------------------------------
  84   |  Memory Controller Options 1
  85   +-----------------------------------------------------------------------------*/
  86 #define SDRAM_CFG1_SRE          0x80000000      /* Self-Refresh Entry           */
  87 #define SDRAM_CFG1_PMEN         0x40000000      /* Power Management Enable      */
  88
  89 /*-----------------------------------------------------------------------------+
  90   |  SDRAM DEVPOT Options
  91   +-----------------------------------------------------------------------------*/
  92 #define SDRAM_DEVOPT_DLL        0x80000000
  93 #define SDRAM_DEVOPT_DS         0x40000000
  94
  95 /*-----------------------------------------------------------------------------+
  96   |  SDRAM MCSTS Options
  97   +-----------------------------------------------------------------------------*/
  98 #define SDRAM_MCSTS_MRSC        0x80000000
  99 #define SDRAM_MCSTS_SRMS        0x40000000
 100 #define SDRAM_MCSTS_CIS         0x20000000
 101
 102 /*-----------------------------------------------------------------------------
 103   |  SDRAM Refresh Timer Register
 104   +-----------------------------------------------------------------------------*/
 105 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 106 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 107 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 108
 109 /*-----------------------------------------------------------------------------+
 110   |  SDRAM UABus Base Address Reg
 111   +-----------------------------------------------------------------------------*/
 112 #define SDRAM_UABBA_UBBA_MASK   0x0000000F
 113
 114 /*-----------------------------------------------------------------------------+
 115   |  Memory Bank 0-7 configuration
 116   +-----------------------------------------------------------------------------*/
 117 #define SDRAM_BXCR_SDBA_MASK    0xff800000        /* Base address             */
 118 #define SDRAM_BXCR_SDSZ_MASK    0x000e0000        /* Size                     */
 119 #define SDRAM_BXCR_SDSZ_8       0x00020000        /*   8M                     */
 120 #define SDRAM_BXCR_SDSZ_16      0x00040000        /*  16M                     */
 121 #define SDRAM_BXCR_SDSZ_32      0x00060000        /*  32M                     */
 122 #define SDRAM_BXCR_SDSZ_64      0x00080000        /*  64M                     */
 123 #define SDRAM_BXCR_SDSZ_128     0x000a0000        /* 128M                     */
 124 #define SDRAM_BXCR_SDSZ_256     0x000c0000        /* 256M                     */
 125 #define SDRAM_BXCR_SDSZ_512     0x000e0000        /* 512M                     */
 126 #define SDRAM_BXCR_SDAM_MASK    0x0000e000        /* Addressing mode          */
 127 #define SDRAM_BXCR_SDAM_1       0x00000000        /*   Mode 1                 */
 128 #define SDRAM_BXCR_SDAM_2       0x00002000        /*   Mode 2                 */
 129 #define SDRAM_BXCR_SDAM_3       0x00004000        /*   Mode 3                 */
 130 #define SDRAM_BXCR_SDAM_4       0x00006000        /*   Mode 4                 */
 131 #define SDRAM_BXCR_SDBE         0x00000001        /* Memory Bank Enable       */
 132
 133 /*-----------------------------------------------------------------------------+
 134   |  SDRAM TR0 Options
 135   +-----------------------------------------------------------------------------*/
 136 #define SDRAM_TR0_SDWR_MASK     0x80000000
 137 #define  SDRAM_TR0_SDWR_2_CLK   0x00000000
 138 #define  SDRAM_TR0_SDWR_3_CLK   0x80000000
 139 #define SDRAM_TR0_SDWD_MASK     0x40000000
 140 #define  SDRAM_TR0_SDWD_0_CLK   0x00000000
 141 #define  SDRAM_TR0_SDWD_1_CLK   0x40000000
 142 #define SDRAM_TR0_SDCL_MASK     0x01800000
 143 #define  SDRAM_TR0_SDCL_2_0_CLK 0x00800000
 144 #define  SDRAM_TR0_SDCL_2_5_CLK 0x01000000
 145 #define  SDRAM_TR0_SDCL_3_0_CLK 0x01800000
 146 #define SDRAM_TR0_SDPA_MASK     0x000C0000
 147 #define  SDRAM_TR0_SDPA_2_CLK   0x00040000
 148 #define  SDRAM_TR0_SDPA_3_CLK   0x00080000
 149 #define  SDRAM_TR0_SDPA_4_CLK   0x000C0000
 150 #define SDRAM_TR0_SDCP_MASK     0x00030000
 151 #define  SDRAM_TR0_SDCP_2_CLK   0x00000000
 152 #define  SDRAM_TR0_SDCP_3_CLK   0x00010000
 153 #define  SDRAM_TR0_SDCP_4_CLK   0x00020000
 154 #define  SDRAM_TR0_SDCP_5_CLK   0x00030000
 155 #define SDRAM_TR0_SDLD_MASK     0x0000C000
 156 #define  SDRAM_TR0_SDLD_1_CLK   0x00000000
 157 #define  SDRAM_TR0_SDLD_2_CLK   0x00004000
 158 #define SDRAM_TR0_SDRA_MASK     0x0000001C
 159 #define  SDRAM_TR0_SDRA_6_CLK   0x00000000
 160 #define  SDRAM_TR0_SDRA_7_CLK   0x00000004
 161 #define  SDRAM_TR0_SDRA_8_CLK   0x00000008
 162 #define  SDRAM_TR0_SDRA_9_CLK   0x0000000C
 163 #define  SDRAM_TR0_SDRA_10_CLK  0x00000010
 164 #define  SDRAM_TR0_SDRA_11_CLK  0x00000014
 165 #define  SDRAM_TR0_SDRA_12_CLK  0x00000018
 166 #define  SDRAM_TR0_SDRA_13_CLK  0x0000001C
 167 #define SDRAM_TR0_SDRD_MASK     0x00000003
 168 #define  SDRAM_TR0_SDRD_2_CLK   0x00000001
 169 #define  SDRAM_TR0_SDRD_3_CLK   0x00000002
 170 #define  SDRAM_TR0_SDRD_4_CLK   0x00000003
 171
 172 /*-----------------------------------------------------------------------------+
 173   |  SDRAM TR1 Options
 174   +-----------------------------------------------------------------------------*/
 175 #define SDRAM_TR1_RDSS_MASK     0xC0000000
 176 #define  SDRAM_TR1_RDSS_TR0     0x00000000
 177 #define  SDRAM_TR1_RDSS_TR1     0x40000000
 178 #define  SDRAM_TR1_RDSS_TR2     0x80000000
 179 #define  SDRAM_TR1_RDSS_TR3     0xC0000000
 180 #define SDRAM_TR1_RDSL_MASK     0x00C00000
 181 #define  SDRAM_TR1_RDSL_STAGE1  0x00000000
 182 #define  SDRAM_TR1_RDSL_STAGE2  0x00400000
 183 #define  SDRAM_TR1_RDSL_STAGE3  0x00800000
 184 #define SDRAM_TR1_RDCD_MASK     0x00000800
 185 #define  SDRAM_TR1_RDCD_RCD_0_0 0x00000000
 186 #define  SDRAM_TR1_RDCD_RCD_1_2 0x00000800
 187 #define SDRAM_TR1_RDCT_MASK     0x000001FF
 188 #define  SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 189 #define  SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 190 #define  SDRAM_TR1_RDCT_MIN     0x00000000
 191 #define  SDRAM_TR1_RDCT_MAX     0x000001FF
 192
 193 /*-----------------------------------------------------------------------------+
 194   |  SDRAM WDDCTR Options
 195   +-----------------------------------------------------------------------------*/
 196 #define SDRAM_WDDCTR_WRCP_MASK  0xC0000000
 197 #define  SDRAM_WDDCTR_WRCP_0DEG   0x00000000
 198 #define  SDRAM_WDDCTR_WRCP_90DEG  0x40000000
 199 #define  SDRAM_WDDCTR_WRCP_180DEG 0x80000000
 200 #define SDRAM_WDDCTR_DCD_MASK   0x000001FF
 201
 202 /*-----------------------------------------------------------------------------+
 203   |  SDRAM CLKTR Options
 204   +-----------------------------------------------------------------------------*/
 205 #define SDRAM_CLKTR_CLKP_MASK   0xC0000000
 206 #define  SDRAM_CLKTR_CLKP_0DEG    0x00000000
 207 #define  SDRAM_CLKTR_CLKP_90DEG   0x40000000
 208 #define  SDRAM_CLKTR_CLKP_180DEG  0x80000000
 209 #define SDRAM_CLKTR_DCDT_MASK   0x000001FF
 210
 211 /*-----------------------------------------------------------------------------+
 212   |  SDRAM DLYCAL Options
 213   +-----------------------------------------------------------------------------*/
 214 #define SDRAM_DLYCAL_DLCV_MASK  0x000003FC
 215 #define  SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 216 #define  SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 217
 218 /*-----------------------------------------------------------------------------+
 219   |  General Definition
 220   +-----------------------------------------------------------------------------*/
 221 #define DEFAULT_SPD_ADDR1       0x53
 222 #define DEFAULT_SPD_ADDR2       0x52
 223 #define MAXBANKS                4               /* at most 4 dimm banks */
 224 #define MAX_SPD_BYTES           256
 225 #define NUMHALFCYCLES           4
 226 #define NUMMEMTESTS             8
 227 #define NUMMEMWORDS             8
 228 #define MAXBXCR                 4
 229 #define TRUE                    1
 230 #define FALSE                   0
 231
 232 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 233         {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 234          0xFFFFFFFF, 0xFFFFFFFF},
 235         {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 236          0x00000000, 0x00000000},
 237         {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 238          0x55555555, 0x55555555},
 239         {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 240          0xAAAAAAAA, 0xAAAAAAAA},
 241         {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 242          0x5A5A5A5A, 0x5A5A5A5A},
 243         {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 244          0xA5A5A5A5, 0xA5A5A5A5},
 245         {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 246          0x55AA55AA, 0x55AA55AA},
 247         {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 248          0xAA55AA55, 0xAA55AA55}
 249 };
 250
 251 /* bank_parms is used to sort the bank sizes by descending order */
 252 struct bank_param {
 253         unsigned long cr;
 254         unsigned long bank_size_bytes;
 255 };
 256
 257 typedef struct bank_param BANKPARMS;
 258
 259 #ifdef CFG_SIMULATE_SPD_EEPROM
 260 extern unsigned char cfg_simulate_spd_eeprom[128];
 261 #endif
 262
 263 unsigned char spd_read(uchar chip, uint addr);
 264
 265 void get_spd_info(unsigned long* dimm_populated,
 266                   unsigned char* iic0_dimm_addr,
 267                   unsigned long  num_dimm_banks);
 268
 269 void check_mem_type
 270 (unsigned long* dimm_populated,
 271  unsigned char* iic0_dimm_addr,
 272  unsigned long  num_dimm_banks);
 273
 274 void check_volt_type
 275 (unsigned long* dimm_populated,
 276  unsigned char* iic0_dimm_addr,
 277  unsigned long  num_dimm_banks);
 278
 279 void program_cfg0(unsigned long* dimm_populated,
 280                   unsigned char* iic0_dimm_addr,
 281                   unsigned long  num_dimm_banks);
 282
 283 void program_cfg1(unsigned long* dimm_populated,
 284                   unsigned char* iic0_dimm_addr,
 285                   unsigned long  num_dimm_banks);
 286
 287 void program_rtr (unsigned long* dimm_populated,
 288                   unsigned char* iic0_dimm_addr,
 289                   unsigned long  num_dimm_banks);
 290
 291 void program_tr0 (unsigned long* dimm_populated,
 292                   unsigned char* iic0_dimm_addr,
 293                   unsigned long  num_dimm_banks);
 294
 295 void program_tr1 (void);
 296
 297 void program_ecc (unsigned long  num_bytes);
 298
 299 unsigned
 300 long  program_bxcr(unsigned long* dimm_populated,
 301                    unsigned char* iic0_dimm_addr,
 302                    unsigned long  num_dimm_banks);
 303
 304 /*
 305  * This function is reading data from the DIMM module EEPROM over the SPD bus
 306  * and uses that to program the sdram controller.
 307  *
 308  * This works on boards that has the same schematics that the AMCC walnut has.
 309  *
 310  * BUG: Don't handle ECC memory
 311  * BUG: A few values in the TR register is currently hardcoded
 312  */
 313
 314 long int spd_sdram(void) {
 315         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 316         unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 317         unsigned long total_size;
 318         unsigned long cfg0;
 319         unsigned long mcsts;
 320         unsigned long num_dimm_banks;               /* on board dimm banks */
 321
 322         num_dimm_banks = sizeof(iic0_dimm_addr);
 323
 324         /*
 325          * Make sure I2C controller is initialized
 326          * before continuing.
 327          */
 328         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 329
 330         /*
 331          * Read the SPD information using I2C interface. Check to see if the
 332          * DIMM slots are populated.
 333          */
 334         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 335
 336         /*
 337          * Check the memory type for the dimms plugged.
 338          */
 339         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 340
 341         /*
 342          * Check the voltage type for the dimms plugged.
 343          */
 344         check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 345
 346 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 347         /*
 348          * Soft-reset SDRAM controller.
 349          */
 350         mtsdr(sdr_srst, SDR0_SRST_DMC);
 351         mtsdr(sdr_srst, 0x00000000);
 352 #endif
 353
 354         /*
 355          * program 440GP SDRAM controller options (SDRAM0_CFG0)
 356          */
 357         program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 358
 359         /*
 360          * program 440GP SDRAM controller options (SDRAM0_CFG1)
 361          */
 362         program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 363
 364         /*
 365          * program SDRAM refresh register (SDRAM0_RTR)
 366          */
 367         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 368
 369         /*
 370          * program SDRAM Timing Register 0 (SDRAM0_TR0)
 371          */
 372         program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 373
 374         /*
 375          * program the BxCR registers to find out total sdram installed
 376          */
 377         total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 378                                   num_dimm_banks);
 379
 380         /*
 381          * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 382          */
 383         mtsdram(mem_clktr, 0x40000000);
 384
 385         /*
 386          * delay to ensure 200 usec has elapsed
 387          */
 388         udelay(400);
 389
 390         /*
 391          * enable the memory controller
 392          */
 393         mfsdram(mem_cfg0, cfg0);
 394         mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 395
 396         /*
 397          * wait for SDRAM_CFG0_DC_EN to complete
 398          */
 399         while (1) {
 400                 mfsdram(mem_mcsts, mcsts);
 401                 if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
 402                         break;
 403                 }
 404         }
 405
 406         /*
 407          * program SDRAM Timing Register 1, adding some delays
 408          */
 409         program_tr1();
 410
 411         /*
 412          * if ECC is enabled, initialize parity bits
 413          */
 414
 415         return total_size;
 416 }
 417
 418 unsigned char spd_read(uchar chip, uint addr)
 419 {
 420         unsigned char data[2];
 421
 422 #ifdef CFG_SIMULATE_SPD_EEPROM
 423         if (chip == CFG_SIMULATE_SPD_EEPROM) {
 424                 /*
 425                  * Onboard spd eeprom requested -> simulate values
 426                  */
 427                 return cfg_simulate_spd_eeprom[addr];
 428         }
 429 #endif /* CFG_SIMULATE_SPD_EEPROM */
 430
 431         if (i2c_probe(chip) == 0) {
 432                 if (i2c_read(chip, addr, 1, data, 1) == 0) {
 433                         return data[0];
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 void get_spd_info(unsigned long*   dimm_populated,
 441                   unsigned char*   iic0_dimm_addr,
 442                   unsigned long    num_dimm_banks)
 443 {
 444         unsigned long dimm_num;
 445         unsigned long dimm_found;
 446         unsigned char num_of_bytes;
 447         unsigned char total_size;
 448
 449         dimm_found = FALSE;
 450         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 451                 num_of_bytes = 0;
 452                 total_size = 0;
 453
 454                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 455                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 456
 457                 if ((num_of_bytes != 0) && (total_size != 0)) {
 458                         dimm_populated[dimm_num] = TRUE;
 459                         dimm_found = TRUE;
 460 #if 0
 461                         printf("DIMM slot %lu: populated\n", dimm_num);
 462 #endif
 463                 } else {
 464                         dimm_populated[dimm_num] = FALSE;
 465 #if 0
 466                         printf("DIMM slot %lu: Not populated\n", dimm_num);
 467 #endif
 468                 }
 469         }
 470
 471         if (dimm_found == FALSE) {
 472                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 473                 hang();
 474         }
 475 }
 476
 477 void check_mem_type(unsigned long*   dimm_populated,
 478                     unsigned char*   iic0_dimm_addr,
 479                     unsigned long    num_dimm_banks)
 480 {
 481         unsigned long dimm_num;
 482         unsigned char dimm_type;
 483
 484         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 485                 if (dimm_populated[dimm_num] == TRUE) {
 486                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 487                         switch (dimm_type) {
 488                         case 7:
 489 #if 0
 490                                 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 491 #endif
 492                                 break;
 493                         default:
 494                                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 495                                        dimm_num);
 496                                 printf("Only DDR SDRAM DIMMs are supported.\n");
 497                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 498                                 hang();
 499                                 break;
 500                         }
 501                 }
 502         }
 503 }
 504
 505
 506 void check_volt_type(unsigned long*   dimm_populated,
 507                      unsigned char*   iic0_dimm_addr,
 508                      unsigned long    num_dimm_banks)
 509 {
 510         unsigned long dimm_num;
 511         unsigned long voltage_type;
 512
 513         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 514                 if (dimm_populated[dimm_num] == TRUE) {
 515                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 516                         if (voltage_type != 0x04) {
 517                                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 518                                        dimm_num);
 519                                 hang();
 520                         } else {
 521 #if 0
 522                                 printf("DIMM %lu voltage level supported.\n", dimm_num);
 523 #endif
 524                         }
 525                         break;
 526                 }
 527         }
 528 }
 529
 530 void program_cfg0(unsigned long* dimm_populated,
 531                   unsigned char* iic0_dimm_addr,
 532                   unsigned long  num_dimm_banks)
 533 {
 534         unsigned long dimm_num;
 535         unsigned long cfg0;
 536         unsigned long ecc_enabled;
 537         unsigned char ecc;
 538         unsigned char attributes;
 539         unsigned long data_width;
 540         unsigned long dimm_32bit;
 541         unsigned long dimm_64bit;
 542
 543         /*
 544          * get Memory Controller Options 0 data
 545          */
 546         mfsdram(mem_cfg0, cfg0);
 547
 548         /*
 549          * clear bits
 550          */
 551         cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 552                   SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 553                   SDRAM_CFG0_DMWD_MASK |
 554                   SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 555
 556
 557         /*
 558          * FIXME: assume the DDR SDRAMs in both banks are the same
 559          */
 560         ecc_enabled = TRUE;
 561         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 562                 if (dimm_populated[dimm_num] == TRUE) {
 563                         ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 564                         if (ecc != 0x02) {
 565                                 ecc_enabled = FALSE;
 566                         }
 567
 568                         /*
 569                          * program Registered DIMM Enable
 570                          */
 571                         attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 572                         if ((attributes & 0x02) != 0x00) {
 573                                 cfg0 |= SDRAM_CFG0_RDEN;
 574                         }
 575
 576                         /*
 577                          * program DDR SDRAM Data Width
 578                          */
 579                         data_width =
 580                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 581                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 582                         if (data_width == 64 || data_width == 72) {
 583                                 dimm_64bit = TRUE;
 584                                 cfg0 |= SDRAM_CFG0_DMWD_64;
 585                         } else if (data_width == 32 || data_width == 40) {
 586                                 dimm_32bit = TRUE;
 587                                 cfg0 |= SDRAM_CFG0_DMWD_32;
 588                         } else {
 589                                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 590                                        data_width);
 591                                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 592                                 hang();
 593                         }
 594                         break;
 595                 }
 596         }
 597
 598         /*
 599          * program Memory Data Error Checking
 600          */
 601         if (ecc_enabled == TRUE) {
 602                 cfg0 |= SDRAM_CFG0_MCHK_GEN;
 603         } else {
 604                 cfg0 |= SDRAM_CFG0_MCHK_NON;
 605         }
 606
 607         /*
 608          * program Page Management Unit (0 == enabled)
 609          */
 610         cfg0 &= ~SDRAM_CFG0_PMUD;
 611
 612         /*
 613          * program Memory Controller Options 0
 614          * Note: DCEN must be enabled after all DDR SDRAM controller
 615          * configuration registers get initialized.
 616          */
 617         mtsdram(mem_cfg0, cfg0);
 618 }
 619
 620 void program_cfg1(unsigned long* dimm_populated,
 621                   unsigned char* iic0_dimm_addr,
 622                   unsigned long  num_dimm_banks)
 623 {
 624         unsigned long cfg1;
 625         mfsdram(mem_cfg1, cfg1);
 626
 627         /*
 628          * Self-refresh exit, disable PM
 629          */
 630         cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 631
 632         /*
 633          * program Memory Controller Options 1
 634          */
 635         mtsdram(mem_cfg1, cfg1);
 636 }
 637
 638 void program_rtr (unsigned long* dimm_populated,
 639                   unsigned char* iic0_dimm_addr,
 640                   unsigned long  num_dimm_banks)
 641 {
 642         unsigned long dimm_num;
 643         unsigned long bus_period_x_10;
 644         unsigned long refresh_rate = 0;
 645         unsigned char refresh_rate_type;
 646         unsigned long refresh_interval;
 647         unsigned long sdram_rtr;
 648         PPC440_SYS_INFO sys_info;
 649
 650         /*
 651          * get the board info
 652          */
 653         get_sys_info(&sys_info);
 654         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 655
 656
 657         for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
 658                 if (dimm_populated[dimm_num] == TRUE) {
 659                         refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 660                         switch (refresh_rate_type) {
 661                         case 0x00:
 662                                 refresh_rate = 15625;
 663                                 break;
 664                         case 0x01:
 665                                 refresh_rate = 15625/4;
 666                                 break;
 667                         case 0x02:
 668                                 refresh_rate = 15625/2;
 669                                 break;
 670                         case 0x03:
 671                                 refresh_rate = 15626*2;
 672                                 break;
 673                         case 0x04:
 674                                 refresh_rate = 15625*4;
 675                                 break;
 676                         case 0x05:
 677                                 refresh_rate = 15625*8;
 678                                 break;
 679                         default:
 680                                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
 681                                        dimm_num);
 682                                 printf("Replace the DIMM module with a supported DIMM.\n");
 683                                 break;
 684                         }
 685
 686                         break;
 687                 }
 688         }
 689
 690         refresh_interval = refresh_rate * 10 / bus_period_x_10;
 691         sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
 692
 693         /*
 694          * program Refresh Timer Register (SDRAM0_RTR)
 695          */
 696         mtsdram(mem_rtr, sdram_rtr);
 697 }
 698
 699 void program_tr0 (unsigned long* dimm_populated,
 700                   unsigned char* iic0_dimm_addr,
 701                   unsigned long  num_dimm_banks)
 702 {
 703         unsigned long dimm_num;
 704         unsigned long tr0;
 705         unsigned char wcsbc;
 706         unsigned char t_rp_ns;
 707         unsigned char t_rcd_ns;
 708         unsigned char t_ras_ns;
 709         unsigned long t_rp_clk;
 710         unsigned long t_ras_rcd_clk;
 711         unsigned long t_rcd_clk;
 712         unsigned long t_rfc_clk;
 713         unsigned long plb_check;
 714         unsigned char cas_bit;
 715         unsigned long cas_index;
 716         unsigned char cas_2_0_available;
 717         unsigned char cas_2_5_available;
 718         unsigned char cas_3_0_available;
 719         unsigned long cycle_time_ns_x_10[3];
 720         unsigned long tcyc_3_0_ns_x_10;
 721         unsigned long tcyc_2_5_ns_x_10;
 722         unsigned long tcyc_2_0_ns_x_10;
 723         unsigned long tcyc_reg;
 724         unsigned long bus_period_x_10;
 725         PPC440_SYS_INFO sys_info;
 726         unsigned long residue;
 727
 728         /*
 729          * get the board info
 730          */
 731         get_sys_info(&sys_info);
 732         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 733
 734         /*
 735          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 736          */
 737         mfsdram(mem_tr0, tr0);
 738         tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
 739                  SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
 740                  SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
 741                  SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
 742
 743         /*
 744          * initialization
 745          */
 746         wcsbc = 0;
 747         t_rp_ns = 0;
 748         t_rcd_ns = 0;
 749         t_ras_ns = 0;
 750         cas_2_0_available = TRUE;
 751         cas_2_5_available = TRUE;
 752         cas_3_0_available = TRUE;
 753         tcyc_2_0_ns_x_10 = 0;
 754         tcyc_2_5_ns_x_10 = 0;
 755         tcyc_3_0_ns_x_10 = 0;
 756
 757         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 758                 if (dimm_populated[dimm_num] == TRUE) {
 759                         wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 760                         t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 761                         t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
 762                         t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
 763                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 764
 765                         for (cas_index = 0; cas_index < 3; cas_index++) {
 766                                 switch (cas_index) {
 767                                 case 0:
 768                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 769                                         break;
 770                                 case 1:
 771                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
 772                                         break;
 773                                 default:
 774                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
 775                                         break;
 776                                 }
 777
 778                                 if ((tcyc_reg & 0x0F) >= 10) {
 779                                         printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
 780                                                dimm_num);
 781                                         hang();
 782                                 }
 783
 784                                 cycle_time_ns_x_10[cas_index] =
 785                                         (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
 786                         }
 787
 788                         cas_index = 0;
 789
 790                         if ((cas_bit & 0x80) != 0) {
 791                                 cas_index += 3;
 792                         } else if ((cas_bit & 0x40) != 0) {
 793                                 cas_index += 2;
 794                         } else if ((cas_bit & 0x20) != 0) {
 795                                 cas_index += 1;
 796                         }
 797
 798                         if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
 799                                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 800                                 cas_index++;
 801                         } else {
 802                                 if (cas_index != 0) {
 803                                         cas_index++;
 804                                 }
 805                                 cas_3_0_available = FALSE;
 806                         }
 807
 808                         if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
 809                                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
 810                                 cas_index++;
 811                         } else {
 812                                 if (cas_index != 0) {
 813                                         cas_index++;
 814                                 }
 815                                 cas_2_5_available = FALSE;
 816                         }
 817
 818                         if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
 819                                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 820                                 cas_index++;
 821                         } else {
 822                                 if (cas_index != 0) {
 823                                         cas_index++;
 824                                 }
 825                                 cas_2_0_available = FALSE;
 826                         }
 827
 828                         break;
 829                 }
 830         }
 831
 832         /*
 833          * Program SD_WR and SD_WCSBC fields
 834          */
 835         tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
 836         switch (wcsbc) {
 837         case 0:
 838                 tr0 |= SDRAM_TR0_SDWD_0_CLK;
 839                 break;
 840         default:
 841                 tr0 |= SDRAM_TR0_SDWD_1_CLK;
 842                 break;
 843         }
 844
 845         /*
 846          * Program SD_CASL field
 847          */
 848         if ((cas_2_0_available == TRUE) &&
 849             (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 850                 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
 851         } else if ((cas_2_5_available == TRUE) &&
 852                  (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 853                 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
 854         } else if ((cas_3_0_available == TRUE) &&
 855                  (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 856                 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 857         } else {
 858                 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
 859                 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
 860                 printf("Make sure the PLB speed is within the supported range.\n");
 861                 hang();
 862         }
 863
 864         /*
 865          * Calculate Trp in clock cycles and round up if necessary
 866          * Program SD_PTA field
 867          */
 868         t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
 869         plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
 870         if (sys_info.freqPLB != plb_check) {
 871                 t_rp_clk++;
 872         }
 873         switch ((unsigned long)t_rp_clk) {
 874         case 0:
 875         case 1:
 876         case 2:
 877                 tr0 |= SDRAM_TR0_SDPA_2_CLK;
 878                 break;
 879         case 3:
 880                 tr0 |= SDRAM_TR0_SDPA_3_CLK;
 881                 break;
 882         default:
 883                 tr0 |= SDRAM_TR0_SDPA_4_CLK;
 884                 break;
 885         }
 886
 887         /*
 888          * Program SD_CTP field
 889          */
 890         t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
 891         plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
 892         if (sys_info.freqPLB != plb_check) {
 893                 t_ras_rcd_clk++;
 894         }
 895         switch (t_ras_rcd_clk) {
 896         case 0:
 897         case 1:
 898         case 2:
 899                 tr0 |= SDRAM_TR0_SDCP_2_CLK;
 900                 break;
 901         case 3:
 902                 tr0 |= SDRAM_TR0_SDCP_3_CLK;
 903                 break;
 904         case 4:
 905                 tr0 |= SDRAM_TR0_SDCP_4_CLK;
 906                 break;
 907         default:
 908                 tr0 |= SDRAM_TR0_SDCP_5_CLK;
 909                 break;
 910         }
 911
 912         /*
 913          * Program SD_LDF field
 914          */
 915         tr0 |= SDRAM_TR0_SDLD_2_CLK;
 916
 917         /*
 918          * Program SD_RFTA field
 919          * FIXME tRFC hardcoded as 75 nanoseconds
 920          */
 921         t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
 922         residue = sys_info.freqPLB % (ONE_BILLION / 75);
 923         if (residue >= (ONE_BILLION / 150)) {
 924                 t_rfc_clk++;
 925         }
 926         switch (t_rfc_clk) {
 927         case 0:
 928         case 1:
 929         case 2:
 930         case 3:
 931         case 4:
 932         case 5:
 933         case 6:
 934                 tr0 |= SDRAM_TR0_SDRA_6_CLK;
 935                 break;
 936         case 7:
 937                 tr0 |= SDRAM_TR0_SDRA_7_CLK;
 938                 break;
 939         case 8:
 940                 tr0 |= SDRAM_TR0_SDRA_8_CLK;
 941                 break;
 942         case 9:
 943                 tr0 |= SDRAM_TR0_SDRA_9_CLK;
 944                 break;
 945         case 10:
 946                 tr0 |= SDRAM_TR0_SDRA_10_CLK;
 947                 break;
 948         case 11:
 949                 tr0 |= SDRAM_TR0_SDRA_11_CLK;
 950                 break;
 951         case 12:
 952                 tr0 |= SDRAM_TR0_SDRA_12_CLK;
 953                 break;
 954         default:
 955                 tr0 |= SDRAM_TR0_SDRA_13_CLK;
 956                 break;
 957         }
 958
 959         /*
 960          * Program SD_RCD field
 961          */
 962         t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
 963         plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
 964         if (sys_info.freqPLB != plb_check) {
 965                 t_rcd_clk++;
 966         }
 967         switch (t_rcd_clk) {
 968         case 0:
 969         case 1:
 970         case 2:
 971                 tr0 |= SDRAM_TR0_SDRD_2_CLK;
 972                 break;
 973         case 3:
 974                 tr0 |= SDRAM_TR0_SDRD_3_CLK;
 975                 break;
 976         default:
 977                 tr0 |= SDRAM_TR0_SDRD_4_CLK;
 978                 break;
 979         }
 980
 981 #if 0
 982         printf("tr0: %x\n", tr0);
 983 #endif
 984         mtsdram(mem_tr0, tr0);
 985 }
 986
 987 void program_tr1 (void)
 988 {
 989         unsigned long tr0;
 990         unsigned long tr1;
 991         unsigned long cfg0;
 992         unsigned long ecc_temp;
 993         unsigned long dlycal;
 994         unsigned long dly_val;
 995         unsigned long i, j, k;
 996         unsigned long bxcr_num;
 997         unsigned long max_pass_length;
 998         unsigned long current_pass_length;
 999         unsigned long current_fail_length;
1000         unsigned long current_start;
1001         unsigned long rdclt;
1002         unsigned long rdclt_offset;
1003         long max_start;
1004         long max_end;
1005         long rdclt_average;
1006         unsigned char window_found;
1007         unsigned char fail_found;
1008         unsigned char pass_found;
1009         unsigned long * membase;
1010         PPC440_SYS_INFO sys_info;
1011
1012         /*
1013          * get the board info
1014          */
1015         get_sys_info(&sys_info);
1016
1017         /*
1018          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1019          */
1020         mfsdram(mem_tr1, tr1);
1021         tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1022                  SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1023
1024         mfsdram(mem_tr0, tr0);
1025         if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1026             (sys_info.freqPLB > 100000000)) {
1027                 tr1 |= SDRAM_TR1_RDSS_TR2;
1028                 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1029                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1030         } else {
1031                 tr1 |= SDRAM_TR1_RDSS_TR1;
1032                 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1033                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1034         }
1035
1036         /*
1037          * save CFG0 ECC setting to a temporary variable and turn ECC off
1038          */
1039         mfsdram(mem_cfg0, cfg0);
1040         ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1041         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1042
1043         /*
1044          * get the delay line calibration register value
1045          */
1046         mfsdram(mem_dlycal, dlycal);
1047         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1048
1049         max_pass_length = 0;
1050         max_start = 0;
1051         max_end = 0;
1052         current_pass_length = 0;
1053         current_fail_length = 0;
1054         current_start = 0;
1055         rdclt_offset = 0;
1056         window_found = FALSE;
1057         fail_found = FALSE;
1058         pass_found = FALSE;
1059 #ifdef DEBUG
1060         printf("Starting memory test ");
1061 #endif
1062         for (k = 0; k < NUMHALFCYCLES; k++) {
1063                 for (rdclt = 0; rdclt < dly_val; rdclt++)  {
1064                         /*
1065                          * Set the timing reg for the test.
1066                          */
1067                         mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1068
1069                         for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1070                                 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1071                                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1072                                         /* Bank is enabled */
1073                                         membase = (unsigned long*)
1074                                                 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1075
1076                                         /*
1077                                          * Run the short memory test
1078                                          */
1079                                         for (i = 0; i < NUMMEMTESTS; i++) {
1080                                                 for (j = 0; j < NUMMEMWORDS; j++) {
1081                                                         membase[j] = test[i][j];
1082                                                         ppcDcbf((unsigned long)&(membase[j]));
1083                                                 }
1084
1085                                                 for (j = 0; j < NUMMEMWORDS; j++) {
1086                                                         if (membase[j] != test[i][j]) {
1087                                                                 ppcDcbf((unsigned long)&(membase[j]));
1088                                                                 break;
1089                                                         }
1090                                                         ppcDcbf((unsigned long)&(membase[j]));
1091                                                 }
1092
1093                                                 if (j < NUMMEMWORDS) {
1094                                                         break;
1095                                                 }
1096                                         }
1097
1098                                         /*
1099                                          * see if the rdclt value passed
1100                                          */
1101                                         if (i < NUMMEMTESTS) {
1102                                                 break;
1103                                         }
1104                                 }
1105                         }
1106
1107                         if (bxcr_num == MAXBXCR) {
1108                                 if (fail_found == TRUE) {
1109                                         pass_found = TRUE;
1110                                         if (current_pass_length == 0) {
1111                                                 current_start = rdclt_offset + rdclt;
1112                                         }
1113
1114                                         current_fail_length = 0;
1115                                         current_pass_length++;
1116
1117                                         if (current_pass_length > max_pass_length) {
1118                                                 max_pass_length = current_pass_length;
1119                                                 max_start = current_start;
1120                                                 max_end = rdclt_offset + rdclt;
1121                                         }
1122                                 }
1123                         } else {
1124                                 current_pass_length = 0;
1125                                 current_fail_length++;
1126
1127                                 if (current_fail_length >= (dly_val>>2)) {
1128                                         if (fail_found == FALSE) {
1129                                                 fail_found = TRUE;
1130                                         } else if (pass_found == TRUE) {
1131                                                 window_found = TRUE;
1132                                                 break;
1133                                         }
1134                                 }
1135                         }
1136                 }
1137 #ifdef DEBUG
1138                 printf(".");
1139 #endif
1140                 if (window_found == TRUE) {
1141                         break;
1142                 }
1143
1144                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1145                 rdclt_offset += dly_val;
1146         }
1147 #ifdef DEBUG
1148         printf("\n");
1149 #endif
1150
1151         /*
1152          * make sure we find the window
1153          */
1154         if (window_found == FALSE) {
1155                 printf("ERROR: Cannot determine a common read delay.\n");
1156                 hang();
1157         }
1158
1159         /*
1160          * restore the orignal ECC setting
1161          */
1162         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1163
1164         /*
1165          * set the SDRAM TR1 RDCD value
1166          */
1167         tr1 &= ~SDRAM_TR1_RDCD_MASK;
1168         if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1169                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1170         } else {
1171                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1172         }
1173
1174         /*
1175          * set the SDRAM TR1 RDCLT value
1176          */
1177         tr1 &= ~SDRAM_TR1_RDCT_MASK;
1178         while (max_end >= (dly_val << 1)) {
1179                 max_end -= (dly_val << 1);
1180                 max_start -= (dly_val << 1);
1181         }
1182
1183         rdclt_average = ((max_start + max_end) >> 1);
1184         if (rdclt_average >= 0x60)
1185                 while (1)
1186                         ;
1187
1188         if (rdclt_average < 0) {
1189                 rdclt_average = 0;
1190         }
1191
1192         if (rdclt_average >= dly_val) {
1193                 rdclt_average -= dly_val;
1194                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1195         }
1196         tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1197
1198 #if 0
1199         printf("tr1: %x\n", tr1);
1200 #endif
1201         /*
1202          * program SDRAM Timing Register 1 TR1
1203          */
1204         mtsdram(mem_tr1, tr1);
1205 }
1206
1207 unsigned long program_bxcr(unsigned long* dimm_populated,
1208                            unsigned char* iic0_dimm_addr,
1209                            unsigned long  num_dimm_banks)
1210 {
1211         unsigned long dimm_num;
1212         unsigned long bank_base_addr;
1213         unsigned long cr;
1214         unsigned long i;
1215         unsigned long j;
1216         unsigned long temp;
1217         unsigned char num_row_addr;
1218         unsigned char num_col_addr;
1219         unsigned char num_banks;
1220         unsigned char bank_size_id;
1221         unsigned long ctrl_bank_num[MAXBANKS];
1222         unsigned long bx_cr_num;
1223         unsigned long largest_size_index;
1224         unsigned long largest_size;
1225         unsigned long current_size_index;
1226         BANKPARMS bank_parms[MAXBXCR];
1227         unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1228         unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1229
1230         /*
1231          * Set the BxCR regs.  First, wipe out the bank config registers.
1232          */
1233         for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1234                 mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
1235                 mtdcr(memcfgd, 0x00000000);
1236                 bank_parms[bx_cr_num].bank_size_bytes = 0;
1237         }
1238
1239 #ifdef CONFIG_BAMBOO
1240         /*
1241          * This next section is hardware dependent and must be programmed
1242          * to match the hardware.  For bammboo, the following holds...
1243          * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
1244          * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1245          * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1246          * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1247          * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1248          */
1249         ctrl_bank_num[0] = 0;
1250         ctrl_bank_num[1] = 1;
1251         ctrl_bank_num[2] = 3;
1252 #else
1253         ctrl_bank_num[0] = 0;
1254         ctrl_bank_num[1] = 1;
1255         ctrl_bank_num[2] = 2;
1256         ctrl_bank_num[3] = 3;
1257 #endif
1258
1259         /*
1260          * reset the bank_base address
1261          */
1262         bank_base_addr = CFG_SDRAM_BASE;
1263
1264         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1265                 if (dimm_populated[dimm_num] == TRUE) {
1266                         num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1267                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1268                         num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1269                         bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1270
1271                         /*
1272                          * Set the SDRAM0_BxCR regs
1273                          */
1274                         cr = 0;
1275                         switch (bank_size_id) {
1276                         case 0x02:
1277                                 cr |= SDRAM_BXCR_SDSZ_8;
1278                                 break;
1279                         case 0x04:
1280                                 cr |= SDRAM_BXCR_SDSZ_16;
1281                                 break;
1282                         case 0x08:
1283                                 cr |= SDRAM_BXCR_SDSZ_32;
1284                                 break;
1285                         case 0x10:
1286                                 cr |= SDRAM_BXCR_SDSZ_64;
1287                                 break;
1288                         case 0x20:
1289                                 cr |= SDRAM_BXCR_SDSZ_128;
1290                                 break;
1291                         case 0x40:
1292                                 cr |= SDRAM_BXCR_SDSZ_256;
1293                                 break;
1294                         case 0x80:
1295                                 cr |= SDRAM_BXCR_SDSZ_512;
1296                                 break;
1297                         default:
1298                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1299                                        dimm_num);
1300                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1301                                        bank_size_id);
1302                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1303                                 hang();
1304                         }
1305
1306                         switch (num_col_addr) {
1307                         case 0x08:
1308                                 cr |= SDRAM_BXCR_SDAM_1;
1309                                 break;
1310                         case 0x09:
1311                                 cr |= SDRAM_BXCR_SDAM_2;
1312                                 break;
1313                         case 0x0A:
1314                                 cr |= SDRAM_BXCR_SDAM_3;
1315                                 break;
1316                         case 0x0B:
1317                                 cr |= SDRAM_BXCR_SDAM_4;
1318                                 break;
1319                         default:
1320                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1321                                        dimm_num);
1322                                 printf("ERROR: Unsupported value for number of "
1323                                        "column addresses: %d.\n", num_col_addr);
1324                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1325                                 hang();
1326                         }
1327
1328                         /*
1329                          * enable the bank
1330                          */
1331                         cr |= SDRAM_BXCR_SDBE;
1332
1333                         for (i = 0; i < num_banks; i++) {
1334                                 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1335                                         (4 * 1024 * 1024) * bank_size_id;
1336                                 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1337                         }
1338                 }
1339         }
1340
1341         /* Initialize sort tables */
1342         for (i = 0; i < MAXBXCR; i++) {
1343                 sorted_bank_num[i] = i;
1344                 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1345         }
1346
1347         for (i = 0; i < MAXBXCR-1; i++) {
1348                 largest_size = sorted_bank_size[i];
1349                 largest_size_index = 255;
1350
1351                 /* Find the largest remaining value */
1352                 for (j = i + 1; j < MAXBXCR; j++) {
1353                         if (sorted_bank_size[j] > largest_size) {
1354                                 /* Save largest remaining value and its index */
1355                                 largest_size = sorted_bank_size[j];
1356                                 largest_size_index = j;
1357                         }
1358                 }
1359
1360                 if (largest_size_index != 255) {
1361                         /* Swap the current and largest values */
1362                         current_size_index = sorted_bank_num[largest_size_index];
1363                         sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1364                         sorted_bank_size[i] = largest_size;
1365                         sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1366                         sorted_bank_num[i] = current_size_index;
1367                 }
1368         }
1369
1370         /* Set the SDRAM0_BxCR regs thanks to sort tables */
1371         for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1372                 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1373                         mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
1374                         temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1375                                                   SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1376                         temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1377                                 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1378                         mtdcr(memcfgd, temp);
1379                         bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1380                 }
1381         }
1382
1383         return(bank_base_addr);
1384 }
1385
1386 void program_ecc (unsigned long  num_bytes)
1387 {
1388         unsigned long bank_base_addr;
1389         unsigned long current_address;
1390         unsigned long end_address;
1391         unsigned long address_increment;
1392         unsigned long cfg0;
1393
1394         /*
1395          * get Memory Controller Options 0 data
1396          */
1397         mfsdram(mem_cfg0, cfg0);
1398
1399         /*
1400          * reset the bank_base address
1401          */
1402         bank_base_addr = CFG_SDRAM_BASE;
1403
1404         if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1405                 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1406                         SDRAM_CFG0_MCHK_GEN);
1407
1408                 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1409                         address_increment = 4;
1410                 } else {
1411                         address_increment = 8;
1412                 }
1413
1414                 current_address = (unsigned long)(bank_base_addr);
1415                 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1416
1417                 while (current_address < end_address) {
1418                         *((unsigned long*)current_address) = 0x00000000;
1419                         current_address += address_increment;
1420                 }
1421
1422                 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1423                         SDRAM_CFG0_MCHK_CHK);
1424         }
1425 }
1426 #endif /* CONFIG_SPD_EEPROM */