3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
30 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
33 #define PROFF_SMC PROFF_SMC1
34 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
36 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
39 #define PROFF_SMC PROFF_SMC2
40 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
42 #elif defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
45 #define PROFF_SCC PROFF_SCC1
46 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
48 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
51 #define PROFF_SCC PROFF_SCC2
52 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
54 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
57 #define PROFF_SCC PROFF_SCC3
58 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
60 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
63 #define PROFF_SCC PROFF_SCC4
64 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
66 #else /* CONFIG_8xx_CONS_? */
67 #error "console not correctly defined"
70 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
73 * Minimal serial functions needed to use one of the SMC ports
74 * as serial console interface.
77 int serial_init (void)
79 volatile immap_t *im = (immap_t *)CFG_IMMR;
81 volatile smc_uart_t *up;
82 volatile cbd_t *tbdf, *rbdf;
83 volatile cpm8xx_t *cp = &(im->im_cpm);
84 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
85 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
89 /* initialize pointers to SMC */
91 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
92 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
94 /* Disable transmitter/receiver.
96 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
100 im->im_siu_conf.sc_sdcr = 1;
102 /* clear error conditions */
104 im->im_sdma.sdma_sdsr = CFG_SDSR;
106 im->im_sdma.sdma_sdsr = 0x83;
109 /* clear SDMA interrupt mask */
111 im->im_sdma.sdma_sdmr = CFG_SDMR;
113 im->im_sdma.sdma_sdmr = 0x00;
116 #if defined(CONFIG_8xx_CONS_SMC1)
117 /* Use Port B for SMC1 instead of other functions.
119 cp->cp_pbpar |= 0x000000c0;
120 cp->cp_pbdir &= ~0x000000c0;
121 cp->cp_pbodr &= ~0x000000c0;
122 #else /* CONFIG_8xx_CONS_SMC2 */
123 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
124 /* Use Port A for SMC2 instead of other functions.
126 ip->iop_papar |= 0x00c0;
127 ip->iop_padir &= ~0x00c0;
128 ip->iop_paodr &= ~0x00c0;
129 # else /* must be a 860 then */
130 /* Use Port B for SMC2 instead of other functions.
132 cp->cp_pbpar |= 0x00000c00;
133 cp->cp_pbdir &= ~0x00000c00;
134 cp->cp_pbodr &= ~0x00000c00;
138 #if defined(CONFIG_FADS)
140 #if defined(CONFIG_8xx_CONS_SMC1)
141 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
143 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
145 #endif /* CONFIG_FADS */
147 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
148 /* Enable Monitor Port Transceiver */
149 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
150 #endif /* CONFIG_RPXLITE */
152 /* Set the physical address of the host memory buffers in
153 * the buffer descriptors.
156 #ifdef CFG_ALLOC_DPRAM
157 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
159 dpaddr = CPM_SERIAL_BASE ;
162 /* Allocate space for two buffer descriptors in the DP ram.
163 * For now, this address seems OK, but it may have to
164 * change with newer versions of the firmware.
165 * damm: allocating space after the two buffers for rx/tx data
168 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
169 rbdf->cbd_bufaddr = (uint) (rbdf+2);
172 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
175 /* Set up the uart parameters in the parameter ram.
177 up->smc_rbase = dpaddr;
178 up->smc_tbase = dpaddr+sizeof(cbd_t);
179 up->smc_rfcr = SMC_EB;
180 up->smc_tfcr = SMC_EB;
182 #if defined(CONFIG_MBX)
184 #endif /* CONFIG_MBX */
186 /* Set UART mode, 8 bit, no parity, one stop.
187 * Enable receive and transmit.
189 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
191 /* Mask all interrupts and remove anything pending.
196 /* Set up the baud rate generator.
200 /* Make the first buffer the only buffer.
202 tbdf->cbd_sc |= BD_SC_WRAP;
203 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
205 /* Single character receive.
210 /* Initialize Tx/Rx parameters.
213 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
216 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
218 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
221 /* Enable transmitter/receiver.
223 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
231 DECLARE_GLOBAL_DATA_PTR;
233 volatile immap_t *im = (immap_t *)CFG_IMMR;
234 volatile cpm8xx_t *cp = &(im->im_cpm);
236 /* Set up the baud rate generator.
237 * See 8xx_io/commproc.c for details.
242 cp->cp_simode = 0x00000000;
245 (((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
249 serial_putc(const char c)
251 volatile cbd_t *tbdf;
253 volatile smc_uart_t *up;
254 volatile immap_t *im = (immap_t *)CFG_IMMR;
255 volatile cpm8xx_t *cpmp = &(im->im_cpm);
260 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
262 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
264 /* Wait for last character to go.
267 buf = (char *)tbdf->cbd_bufaddr;
270 while (tbdf->cbd_sc & BD_SC_READY)
275 tbdf->cbd_datlen = 1;
276 tbdf->cbd_sc |= BD_SC_READY;
279 while (tbdf->cbd_sc & BD_SC_READY)
287 volatile cbd_t *rbdf;
288 volatile unsigned char *buf;
289 volatile smc_uart_t *up;
290 volatile immap_t *im = (immap_t *)CFG_IMMR;
291 volatile cpm8xx_t *cpmp = &(im->im_cpm);
294 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
296 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
298 /* Wait for character to show up.
300 buf = (unsigned char *)rbdf->cbd_bufaddr;
301 while (rbdf->cbd_sc & BD_SC_EMPTY)
304 rbdf->cbd_sc |= BD_SC_EMPTY;
312 volatile cbd_t *rbdf;
313 volatile smc_uart_t *up;
314 volatile immap_t *im = (immap_t *)CFG_IMMR;
315 volatile cpm8xx_t *cpmp = &(im->im_cpm);
317 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
319 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
321 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
324 #else /* ! CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
326 int serial_init (void)
328 volatile immap_t *im = (immap_t *)CFG_IMMR;
330 volatile scc_uart_t *up;
331 volatile cbd_t *tbdf, *rbdf;
332 volatile cpm8xx_t *cp = &(im->im_cpm);
334 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
335 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
338 /* initialize pointers to SCC */
340 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
341 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
343 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
344 { /* Disable Ethernet, enable Serial */
348 c &= ~0x40; /* enable COM3 */
349 c |= 0x80; /* disable Ethernet */
353 cp->cp_pbpar |= 0x2000;
354 cp->cp_pbdat |= 0x2000;
355 cp->cp_pbdir |= 0x2000;
357 #endif /* CONFIG_LWMON */
359 /* Disable transmitter/receiver.
361 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
363 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
365 * The MPC850 has SCC3 on Port B
367 cp->cp_pbpar |= 0x06;
368 cp->cp_pbdir &= ~0x06;
369 cp->cp_pbodr &= ~0x06;
371 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
373 * Standard configuration for SCC's is on Part A
375 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
376 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
377 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
380 * The IP860 has SCC3 and SCC4 on Port D
382 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
385 /* Allocate space for two buffer descriptors in the DP ram.
388 #ifdef CFG_ALLOC_DPRAM
389 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
391 dpaddr = CPM_SERIAL_BASE ;
396 im->im_siu_conf.sc_sdcr = 0x0001;
398 /* Set the physical address of the host memory buffers in
399 * the buffer descriptors.
402 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
403 rbdf->cbd_bufaddr = (uint) (rbdf+2);
406 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
409 /* Set up the baud rate generator.
413 /* Set up the uart parameters in the parameter ram.
415 up->scc_genscc.scc_rbase = dpaddr;
416 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
418 /* Initialize Tx/Rx parameters.
420 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
422 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
424 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
427 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
428 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
430 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
431 up->scc_maxidl = 0; /* disable max idle */
432 up->scc_brkcr = 1; /* send one break character on stop TX */
440 up->scc_char1 = 0x8000;
441 up->scc_char2 = 0x8000;
442 up->scc_char3 = 0x8000;
443 up->scc_char4 = 0x8000;
444 up->scc_char5 = 0x8000;
445 up->scc_char6 = 0x8000;
446 up->scc_char7 = 0x8000;
447 up->scc_char8 = 0x8000;
448 up->scc_rccm = 0xc0ff;
450 /* Set low latency / small fifo.
452 sp->scc_gsmrh = SCC_GSMRH_RFW;
454 /* Set SCC(x) clock mode to 16x
455 * See 8xx_io/commproc.c for details.
460 /* Set UART mode, clock divider 16 on Tx and Rx
463 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
465 sp->scc_psmr |= SCU_PSMR_CL;
467 /* Mask all interrupts and remove anything pending.
470 sp->scc_scce = 0xffff;
471 sp->scc_dsr = 0x7e7e;
472 sp->scc_psmr = 0x3000;
474 /* Make the first buffer the only buffer.
476 tbdf->cbd_sc |= BD_SC_WRAP;
477 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
479 /* Enable transmitter/receiver.
481 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
489 DECLARE_GLOBAL_DATA_PTR;
491 volatile immap_t *im = (immap_t *)CFG_IMMR;
492 volatile cpm8xx_t *cp = &(im->im_cpm);
494 /* Set up the baud rate generator.
495 * See 8xx_io/commproc.c for details.
500 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
501 /* no |= needed, since BRG1 is 000 */
504 (((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
508 serial_putc(const char c)
510 volatile cbd_t *tbdf;
512 volatile scc_uart_t *up;
513 volatile immap_t *im = (immap_t *)CFG_IMMR;
514 volatile cpm8xx_t *cpmp = &(im->im_cpm);
519 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
521 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
523 /* Wait for last character to go.
526 buf = (char *)tbdf->cbd_bufaddr;
529 while (tbdf->cbd_sc & BD_SC_READY)
534 tbdf->cbd_datlen = 1;
535 tbdf->cbd_sc |= BD_SC_READY;
538 while (tbdf->cbd_sc & BD_SC_READY)
546 volatile cbd_t *rbdf;
547 volatile unsigned char *buf;
548 volatile scc_uart_t *up;
549 volatile immap_t *im = (immap_t *)CFG_IMMR;
550 volatile cpm8xx_t *cpmp = &(im->im_cpm);
553 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
555 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
557 /* Wait for character to show up.
559 buf = (unsigned char *)rbdf->cbd_bufaddr;
560 while (rbdf->cbd_sc & BD_SC_EMPTY)
563 rbdf->cbd_sc |= BD_SC_EMPTY;
571 volatile cbd_t *rbdf;
572 volatile scc_uart_t *up;
573 volatile immap_t *im = (immap_t *)CFG_IMMR;
574 volatile cpm8xx_t *cpmp = &(im->im_cpm);
576 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
578 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
580 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
583 #endif /* CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2 */
587 serial_puts (const char *s)
595 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
598 kgdb_serial_init(void)
600 #if defined(CONFIG_8xx_CONS_SMC1)
601 serial_printf("[on SMC1] ");
602 #elif defined(CONFIG_8xx_CONS_SMC2)
603 serial_printf("[on SMC2] ");
604 #elif defined(CONFIG_8xx_CONS_SCC1)
605 serial_printf("[on SCC1] ");
606 #elif defined(CONFIG_8xx_CONS_SCC2)
607 serial_printf("[on SCC2] ");
608 #elif defined(CONFIG_8xx_CONS_SCC3)
609 serial_printf("[on SCC3] ");
610 #elif defined(CONFIG_8xx_CONS_SCC4)
611 serial_printf("[on SCC4] ");
622 putDebugStr (const char *str)
630 return serial_getc();
634 kgdb_interruptible (int yes)
638 #endif /* CFG_CMD_KGDB */
640 #endif /* CONFIG_8xx_CONS_NONE */