MIPS: add compile time definition of L2 cache size
[oweals/u-boot.git] / configs / zynq_picozed_defconfig
1 CONFIG_ARM=y
2 CONFIG_SPL_SYS_DCACHE_OFF=y
3 CONFIG_ARCH_ZYNQ=y
4 CONFIG_SYS_TEXT_BASE=0x4000000
5 CONFIG_SPL_STACK_R_ADDR=0x200000
6 CONFIG_SPL=y
7 CONFIG_DISTRO_DEFAULTS=y
8 CONFIG_SYS_CUSTOM_LDSCRIPT=y
9 CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
10 CONFIG_USE_PREBOOT=y
11 CONFIG_SPL_STACK_R=y
12 CONFIG_SPL_OS_BOOT=y
13 CONFIG_CMD_THOR_DOWNLOAD=y
14 CONFIG_CMD_DFU=y
15 # CONFIG_CMD_FLASH is not set
16 CONFIG_CMD_FPGA_LOADBP=y
17 CONFIG_CMD_FPGA_LOADFS=y
18 CONFIG_CMD_FPGA_LOADMK=y
19 CONFIG_CMD_FPGA_LOADP=y
20 CONFIG_CMD_GPIO=y
21 CONFIG_CMD_MMC=y
22 CONFIG_CMD_USB=y
23 # CONFIG_CMD_SETEXPR is not set
24 CONFIG_CMD_TFTPPUT=y
25 CONFIG_CMD_CACHE=y
26 CONFIG_CMD_EXT4_WRITE=y
27 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
28 CONFIG_NET_RANDOM_ETHADDR=y
29 CONFIG_SPL_DM_SEQ_ALIAS=y
30 CONFIG_DFU_MMC=y
31 CONFIG_DFU_RAM=y
32 CONFIG_FPGA_XILINX=y
33 CONFIG_FPGA_ZYNQPL=y
34 CONFIG_DM_GPIO=y
35 CONFIG_MMC_SDHCI=y
36 CONFIG_MMC_SDHCI_ZYNQ=y
37 CONFIG_PHY_MARVELL=y
38 CONFIG_PHY_REALTEK=y
39 CONFIG_PHY_XILINX=y
40 CONFIG_MII=y
41 CONFIG_ZYNQ_GEM=y
42 CONFIG_ZYNQ_SERIAL=y
43 CONFIG_USB=y
44 CONFIG_USB_EHCI_HCD=y
45 CONFIG_USB_ULPI_VIEWPORT=y
46 CONFIG_USB_ULPI=y
47 CONFIG_USB_GADGET=y
48 CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
49 CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
50 CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
51 CONFIG_CI_UDC=y
52 CONFIG_USB_GADGET_DOWNLOAD=y
53 CONFIG_USB_FUNCTION_THOR=y