Merge branch 'master' of git://git.denx.de/u-boot-tegra
[oweals/u-boot.git] / configs / mpc8308_p1m_defconfig
1 CONFIG_PPC=y
2 CONFIG_SYS_TEXT_BASE=0xFC000000
3 CONFIG_SYS_CLK_FREQ=33333333
4 CONFIG_MPC83xx=y
5 CONFIG_TARGET_MPC8308_P1M=y
6 CONFIG_SYSTEM_PLL_VCO_DIV_2=y
7 CONFIG_SYSTEM_PLL_FACTOR_4_1=y
8 CONFIG_CORE_PLL_RATIO_3_1=y
9 CONFIG_BOOT_MEMORY_SPACE_LOW=y
10 CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
11 CONFIG_BAT0=y
12 CONFIG_BAT0_NAME="DDR"
13 CONFIG_BAT0_BASE=0x00000000
14 CONFIG_BAT0_LENGTH_128_MBYTES=y
15 CONFIG_BAT0_ACCESS_RW=y
16 CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
17 CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
18 CONFIG_BAT0_USER_MODE_VALID=y
19 CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
20 CONFIG_BAT1=y
21 CONFIG_BAT1_NAME="IMMRBAR"
22 CONFIG_BAT1_BASE=0xE0000000
23 CONFIG_BAT1_LENGTH_8_MBYTES=y
24 CONFIG_BAT1_ACCESS_RW=y
25 CONFIG_BAT1_ICACHE_INHIBITED=y
26 CONFIG_BAT1_ICACHE_GUARDED=y
27 CONFIG_BAT1_DCACHE_INHIBITED=y
28 CONFIG_BAT1_DCACHE_GUARDED=y
29 CONFIG_BAT1_USER_MODE_VALID=y
30 CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
31 CONFIG_BAT2=y
32 CONFIG_BAT2_NAME="FLASH"
33 CONFIG_BAT2_BASE=0xFC000000
34 CONFIG_BAT2_LENGTH_8_MBYTES=y
35 CONFIG_BAT2_ACCESS_RW=y
36 CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
37 CONFIG_BAT2_DCACHE_INHIBITED=y
38 CONFIG_BAT2_DCACHE_GUARDED=y
39 CONFIG_BAT2_USER_MODE_VALID=y
40 CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
41 CONFIG_BAT3=y
42 CONFIG_BAT3_NAME="STACKINDCACHE"
43 CONFIG_BAT3_BASE=0xE6000000
44 CONFIG_BAT3_ACCESS_RW=y
45 CONFIG_BAT3_USER_MODE_VALID=y
46 CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
47 CONFIG_LBLAW0=y
48 CONFIG_LBLAW0_BASE=0xFC000000
49 CONFIG_LBLAW0_NAME="FLASH"
50 CONFIG_LBLAW0_LENGTH_64_MBYTES=y
51 CONFIG_LBLAW1=y
52 CONFIG_LBLAW1_BASE=0xFBFF0000
53 CONFIG_LBLAW1_NAME="SJA1000"
54 CONFIG_LBLAW1_LENGTH_32_KBYTES=y
55 CONFIG_LBLAW2=y
56 CONFIG_LBLAW2_BASE=0xFBFF8000
57 CONFIG_LBLAW2_NAME="CPLD"
58 CONFIG_LBLAW2_LENGTH_32_KBYTES=y
59 CONFIG_ELBC_BR0_OR0=y
60 CONFIG_BR0_OR0_NAME="FLASH"
61 CONFIG_BR0_OR0_BASE=0xFC000000
62 CONFIG_BR0_PORTSIZE_16BIT=y
63 CONFIG_OR0_AM_64_MBYTES=y
64 CONFIG_OR0_XAM_SET=y
65 CONFIG_OR0_SCY_4=y
66 CONFIG_OR0_CSNT_EARLIER=y
67 CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
68 CONFIG_OR0_XACS_EXTENDED=y
69 CONFIG_OR0_TRLX_RELAXED=y
70 CONFIG_OR0_EHTR_8_CYCLE=y
71 CONFIG_ELBC_BR1_OR1=y
72 CONFIG_BR1_OR1_NAME="SJA1000"
73 CONFIG_BR1_OR1_BASE=0xFBFF0000
74 CONFIG_OR1_SCY_5=y
75 CONFIG_OR1_EHTR_1_CYCLE=y
76 CONFIG_ELBC_BR2_OR2=y
77 CONFIG_BR2_OR2_NAME="CPLD"
78 CONFIG_BR2_OR2_BASE=0xFBFF8000
79 CONFIG_OR2_SCY_4=y
80 CONFIG_OR2_EHTR_1_CYCLE=y
81 CONFIG_HID0_FINAL_EMCP=y
82 CONFIG_HID0_FINAL_DPM=y
83 CONFIG_HID0_FINAL_ICE=y
84 CONFIG_HID2_HBE=y
85 CONFIG_SICR_ESDHC_A_GPIO=y
86 CONFIG_SICR_ESDHC_B_GPIO=y
87 CONFIG_SICR_ESDHC_C_GTM=y
88 CONFIG_SICR_GPIO_A_TSEC2=y
89 CONFIG_SICR_GPIO_B_TSEC2=y
90 CONFIG_SICR_IEEE1588_A_GPIO=y
91 CONFIG_SICR_GTM_GPIO=y
92 CONFIG_SICR_GPIOSEL_IEEE1588=y
93 CONFIG_ACR_PIPE_DEP_4=y
94 CONFIG_ACR_RPTCNT_4=y
95 CONFIG_SPCR_TSECEP_3=y
96 CONFIG_LCRR_DBYP_PLL_BYPASSED=y
97 CONFIG_LCRR_CLKDIV_2=y
98 CONFIG_OF_BOARD_SETUP=y
99 CONFIG_OF_STDOUT_VIA_ALIAS=y
100 CONFIG_BOOTDELAY=5
101 CONFIG_HUSH_PARSER=y
102 # CONFIG_AUTO_COMPLETE is not set
103 CONFIG_CMD_IMLS=y
104 CONFIG_CMD_I2C=y
105 CONFIG_CMD_PCI=y
106 # CONFIG_CMD_SETEXPR is not set
107 CONFIG_CMD_DHCP=y
108 CONFIG_CMD_MII=y
109 CONFIG_CMD_PING=y
110 # CONFIG_MMC is not set
111 CONFIG_MTD_NOR_FLASH=y
112 CONFIG_FLASH_CFI_DRIVER=y
113 CONFIG_SYS_FLASH_PROTECTION=y
114 CONFIG_SYS_FLASH_CFI=y
115 CONFIG_PHY_MARVELL=y
116 CONFIG_MII=y
117 CONFIG_TSEC_ENET=y
118 CONFIG_SYS_NS16550=y
119 CONFIG_OF_LIBFDT=y