common/bouncebuf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Generic bounce buffer implementation
   4  *
   5  * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <bouncebuf.h>
  13 #include <asm/cache.h>
  14
  15 static int addr_aligned(struct bounce_buffer *state)
  16 {
  17         const ulong align_mask = ARCH_DMA_MINALIGN - 1;
  18
  19         /* Check if start is aligned */
  20         if ((ulong)state->user_buffer & align_mask) {
  21                 debug("Unaligned buffer address %p\n", state->user_buffer);
  22                 return 0;
  23         }
  24
  25         /* Check if length is aligned */
  26         if (state->len != state->len_aligned) {
  27                 debug("Unaligned buffer length %zu\n", state->len);
  28                 return 0;
  29         }
  30
  31         /* Aligned */
  32         return 1;
  33 }
  34
  35 int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data,
  36                                  size_t len, unsigned int flags,
  37                                  size_t alignment,
  38                                  int (*addr_is_aligned)(struct bounce_buffer *state))
  39 {
  40         state->user_buffer = data;
  41         state->bounce_buffer = data;
  42         state->len = len;
  43         state->len_aligned = roundup(len, alignment);
  44         state->flags = flags;
  45
  46         if (!addr_is_aligned(state)) {
  47                 state->bounce_buffer = memalign(alignment,
  48                                                 state->len_aligned);
  49                 if (!state->bounce_buffer)
  50                         return -ENOMEM;
  51
  52                 if (state->flags & GEN_BB_READ)
  53                         memcpy(state->bounce_buffer, state->user_buffer,
  54                                 state->len);
  55         }
  56
  57         /*
  58          * Flush data to RAM so DMA reads can pick it up,
  59          * and any CPU writebacks don't race with DMA writes
  60          */
  61         flush_dcache_range((unsigned long)state->bounce_buffer,
  62                                 (unsigned long)(state->bounce_buffer) +
  63                                         state->len_aligned);
  64
  65         return 0;
  66 }
  67
  68 int bounce_buffer_start(struct bounce_buffer *state, void *data,
  69                         size_t len, unsigned int flags)
  70 {
  71         return bounce_buffer_start_extalign(state, data, len, flags,
  72                                             ARCH_DMA_MINALIGN,
  73                                             addr_aligned);
  74 }
  75
  76 int bounce_buffer_stop(struct bounce_buffer *state)
  77 {
  78         if (state->flags & GEN_BB_WRITE) {
  79                 /* Invalidate cache so that CPU can see any newly DMA'd data */
  80                 invalidate_dcache_range((unsigned long)state->bounce_buffer,
  81                                         (unsigned long)(state->bounce_buffer) +
  82                                                 state->len_aligned);
  83         }
  84
  85         if (state->bounce_buffer == state->user_buffer)
  86                 return 0;
  87
  88         if (state->flags & GEN_BB_WRITE)
  89                 memcpy(state->user_buffer, state->bounce_buffer, state->len);
  90
  91         free(state->bounce_buffer);
  92
  93         return 0;
  94 }