board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <wdt.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/psu_init_gpl.h>
  18 #include <asm/io.h>
  19 #include <dm/device.h>
  20 #include <dm/uclass.h>
  21 #include <usb.h>
  22 #include <dwc3-uboot.h>
  23 #include <zynqmppl.h>
  24 #include <g_dnl.h>
  25
  26 #include "pm_cfg_obj.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  31     !defined(CONFIG_SPL_BUILD)
  32 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  33
  34 static const struct {
  35         u32 id;
  36         u32 ver;
  37         char *name;
  38         bool evexists;
  39 } zynqmp_devices[] = {
  40         {
  41                 .id = 0x10,
  42                 .name = "3eg",
  43         },
  44         {
  45                 .id = 0x10,
  46                 .ver = 0x2c,
  47                 .name = "3cg",
  48         },
  49         {
  50                 .id = 0x11,
  51                 .name = "2eg",
  52         },
  53         {
  54                 .id = 0x11,
  55                 .ver = 0x2c,
  56                 .name = "2cg",
  57         },
  58         {
  59                 .id = 0x20,
  60                 .name = "5ev",
  61                 .evexists = 1,
  62         },
  63         {
  64                 .id = 0x20,
  65                 .ver = 0x100,
  66                 .name = "5eg",
  67                 .evexists = 1,
  68         },
  69         {
  70                 .id = 0x20,
  71                 .ver = 0x12c,
  72                 .name = "5cg",
  73                 .evexists = 1,
  74         },
  75         {
  76                 .id = 0x21,
  77                 .name = "4ev",
  78                 .evexists = 1,
  79         },
  80         {
  81                 .id = 0x21,
  82                 .ver = 0x100,
  83                 .name = "4eg",
  84                 .evexists = 1,
  85         },
  86         {
  87                 .id = 0x21,
  88                 .ver = 0x12c,
  89                 .name = "4cg",
  90                 .evexists = 1,
  91         },
  92         {
  93                 .id = 0x30,
  94                 .name = "7ev",
  95                 .evexists = 1,
  96         },
  97         {
  98                 .id = 0x30,
  99                 .ver = 0x100,
 100                 .name = "7eg",
 101                 .evexists = 1,
 102         },
 103         {
 104                 .id = 0x30,
 105                 .ver = 0x12c,
 106                 .name = "7cg",
 107                 .evexists = 1,
 108         },
 109         {
 110                 .id = 0x38,
 111                 .name = "9eg",
 112         },
 113         {
 114                 .id = 0x38,
 115                 .ver = 0x2c,
 116                 .name = "9cg",
 117         },
 118         {
 119                 .id = 0x39,
 120                 .name = "6eg",
 121         },
 122         {
 123                 .id = 0x39,
 124                 .ver = 0x2c,
 125                 .name = "6cg",
 126         },
 127         {
 128                 .id = 0x40,
 129                 .name = "11eg",
 130         },
 131         { /* For testing purpose only */
 132                 .id = 0x50,
 133                 .ver = 0x2c,
 134                 .name = "15cg",
 135         },
 136         {
 137                 .id = 0x50,
 138                 .name = "15eg",
 139         },
 140         {
 141                 .id = 0x58,
 142                 .name = "19eg",
 143         },
 144         {
 145                 .id = 0x59,
 146                 .name = "17eg",
 147         },
 148         {
 149                 .id = 0x61,
 150                 .name = "21dr",
 151         },
 152         {
 153                 .id = 0x63,
 154                 .name = "23dr",
 155         },
 156         {
 157                 .id = 0x65,
 158                 .name = "25dr",
 159         },
 160         {
 161                 .id = 0x64,
 162                 .name = "27dr",
 163         },
 164         {
 165                 .id = 0x60,
 166                 .name = "28dr",
 167         },
 168         {
 169                 .id = 0x62,
 170                 .name = "29dr",
 171         },
 172         {
 173                 .id = 0x66,
 174                 .name = "39dr",
 175         },
 176 };
 177 #endif
 178
 179 int chip_id(unsigned char id)
 180 {
 181         struct pt_regs regs;
 182         int val = -EINVAL;
 183
 184         if (current_el() != 3) {
 185                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 186                 regs.regs[1] = 0;
 187                 regs.regs[2] = 0;
 188                 regs.regs[3] = 0;
 189
 190                 smc_call(&regs);
 191
 192                 /*
 193                  * SMC returns:
 194                  * regs[0][31:0]  = status of the operation
 195                  * regs[0][63:32] = CSU.IDCODE register
 196                  * regs[1][31:0]  = CSU.version register
 197                  * regs[1][63:32] = CSU.IDCODE2 register
 198                  */
 199                 switch (id) {
 200                 case IDCODE:
 201                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 202                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 203                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 204                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 205                         val = regs.regs[0];
 206                         break;
 207                 case VERSION:
 208                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 209                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 210                         val = regs.regs[1];
 211                         break;
 212                 case IDCODE2:
 213                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 214                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 215                         val = regs.regs[1];
 216                         break;
 217                 default:
 218                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 219                 }
 220         } else {
 221                 switch (id) {
 222                 case IDCODE:
 223                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 224                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 225                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 226                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 227                         break;
 228                 case VERSION:
 229                         val = readl(ZYNQMP_CSU_VER_ADDR);
 230                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 231                         break;
 232                 default:
 233                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 234                 }
 235         }
 236
 237         return val;
 238 }
 239
 240 #define ZYNQMP_VERSION_SIZE             9
 241 #define ZYNQMP_PL_STATUS_BIT            9
 242 #define ZYNQMP_IPDIS_VCU_BIT            8
 243 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 244 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 245 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 246                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 247 #define MAX_VARIANTS_EV                 3
 248
 249 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 250         !defined(CONFIG_SPL_BUILD)
 251 static char *zynqmp_get_silicon_idcode_name(void)
 252 {
 253         u32 i, id, ver, j;
 254         char *buf;
 255         static char name[ZYNQMP_VERSION_SIZE];
 256
 257         id = chip_id(IDCODE);
 258         ver = chip_id(IDCODE2);
 259
 260         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 261                 if (zynqmp_devices[i].id == id) {
 262                         if (zynqmp_devices[i].evexists &&
 263                             !(ver & ZYNQMP_PL_STATUS_MASK))
 264                                 break;
 265                         if (zynqmp_devices[i].ver == (ver &
 266                             ZYNQMP_CSU_VERSION_MASK))
 267                                 break;
 268                 }
 269         }
 270
 271         if (i >= ARRAY_SIZE(zynqmp_devices))
 272                 return "unknown";
 273
 274         strncat(name, "zu", 2);
 275         if (!zynqmp_devices[i].evexists ||
 276             (ver & ZYNQMP_PL_STATUS_MASK)) {
 277                 strncat(name, zynqmp_devices[i].name,
 278                         ZYNQMP_VERSION_SIZE - 3);
 279                 return name;
 280         }
 281
 282         /*
 283          * Here we are means, PL not powered up and ev variant
 284          * exists. So, we need to ignore VCU disable bit(8) in
 285          * version and findout if its CG or EG/EV variant.
 286          */
 287         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 288                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 289                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 290                         strncat(name, zynqmp_devices[i].name,
 291                                 ZYNQMP_VERSION_SIZE - 3);
 292                         break;
 293                 }
 294         }
 295
 296         if (j >= MAX_VARIANTS_EV)
 297                 return "unknown";
 298
 299         if (strstr(name, "eg") || strstr(name, "ev")) {
 300                 buf = strstr(name, "e");
 301                 *buf = '\0';
 302         }
 303
 304         return name;
 305 }
 306 #endif
 307
 308 int board_early_init_f(void)
 309 {
 310         int ret = 0;
 311 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 312         u32 pm_api_version;
 313
 314         pm_api_version = zynqmp_pmufw_version();
 315         printf("PMUFW:\tv%d.%d\n",
 316                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 317                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 318
 319         if (pm_api_version < ZYNQMP_PM_VERSION)
 320                 panic("PMUFW version error. Expected: v%d.%d\n",
 321                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 322 #endif
 323
 324 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 325         ret = psu_init();
 326 #endif
 327
 328         return ret;
 329 }
 330
 331 int board_init(void)
 332 {
 333 #if defined(CONFIG_SPL_BUILD)
 334         /* Check *at build time* if the filename is an non-empty string */
 335         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 336                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 337                                                 zynqmp_pm_cfg_obj_size);
 338 #endif
 339
 340         printf("EL Level:\tEL%d\n", current_el());
 341
 342 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 343     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 344     defined(CONFIG_SPL_BUILD))
 345         if (current_el() != 3) {
 346                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 347                 printf("Chip ID:\t%s\n", zynqmppl.name);
 348                 fpga_init();
 349                 fpga_add(fpga_xilinx, &zynqmppl);
 350         }
 351 #endif
 352
 353         return 0;
 354 }
 355
 356 int board_early_init_r(void)
 357 {
 358         u32 val;
 359
 360         if (current_el() != 3)
 361                 return 0;
 362
 363         val = readl(&crlapb_base->timestamp_ref_ctrl);
 364         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 365
 366         if (!val) {
 367                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 368                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 369                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 370
 371                 /* Program freq register in System counter */
 372                 writel(zynqmp_get_system_timer_freq(),
 373                        &iou_scntr_secure->base_frequency_id_register);
 374                 /* And enable system counter */
 375                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 376                        &iou_scntr_secure->counter_control_register);
 377         }
 378         return 0;
 379 }
 380
 381 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 382                          char * const argv[])
 383 {
 384         int ret = 0;
 385
 386         if (current_el() > 1) {
 387                 smp_kick_all_cpus();
 388                 dcache_disable();
 389                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 390                                     ES_TO_AARCH64);
 391         } else {
 392                 printf("FAIL: current EL is not above EL1\n");
 393                 ret = EINVAL;
 394         }
 395         return ret;
 396 }
 397
 398 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 399 int dram_init_banksize(void)
 400 {
 401         int ret;
 402
 403         ret = fdtdec_setup_memory_banksize();
 404         if (ret)
 405                 return ret;
 406
 407         mem_map_fill();
 408
 409         return 0;
 410 }
 411
 412 int dram_init(void)
 413 {
 414         if (fdtdec_setup_mem_size_base() != 0)
 415                 return -EINVAL;
 416
 417         return 0;
 418 }
 419 #else
 420 int dram_init_banksize(void)
 421 {
 422 #if defined(CONFIG_NR_DRAM_BANKS)
 423         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 424         gd->bd->bi_dram[0].size = get_effective_memsize();
 425 #endif
 426
 427         mem_map_fill();
 428
 429         return 0;
 430 }
 431
 432 int dram_init(void)
 433 {
 434         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 435                                     CONFIG_SYS_SDRAM_SIZE);
 436
 437         return 0;
 438 }
 439 #endif
 440
 441 void reset_cpu(ulong addr)
 442 {
 443 }
 444
 445 #if defined(CONFIG_BOARD_LATE_INIT)
 446 static const struct {
 447         u32 bit;
 448         const char *name;
 449 } reset_reasons[] = {
 450         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 451         { RESET_REASON_SOFT, "SOFT" },
 452         { RESET_REASON_SRST, "SRST" },
 453         { RESET_REASON_PSONLY, "PS-ONLY" },
 454         { RESET_REASON_PMU, "PMU" },
 455         { RESET_REASON_INTERNAL, "INTERNAL" },
 456         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 457         {}
 458 };
 459
 460 static int reset_reason(void)
 461 {
 462         u32 reg;
 463         int i, ret;
 464         const char *reason = NULL;
 465
 466         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 467         if (ret)
 468                 return -EINVAL;
 469
 470         puts("Reset reason:\t");
 471
 472         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 473                 if (reg & reset_reasons[i].bit) {
 474                         reason = reset_reasons[i].name;
 475                         printf("%s ", reset_reasons[i].name);
 476                         break;
 477                 }
 478         }
 479
 480         puts("\n");
 481
 482         env_set("reset_reason", reason);
 483
 484         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 485         if (ret)
 486                 return -EINVAL;
 487
 488         return ret;
 489 }
 490
 491 static int set_fdtfile(void)
 492 {
 493         char *compatible, *fdtfile;
 494         const char *suffix = ".dtb";
 495         const char *vendor = "xilinx/";
 496
 497         if (env_get("fdtfile"))
 498                 return 0;
 499
 500         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 501         if (compatible) {
 502                 debug("Compatible: %s\n", compatible);
 503
 504                 /* Discard vendor prefix */
 505                 strsep(&compatible, ",");
 506
 507                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 508                                  strlen(suffix) + 1);
 509                 if (!fdtfile)
 510                         return -ENOMEM;
 511
 512                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 513
 514                 env_set("fdtfile", fdtfile);
 515                 free(fdtfile);
 516         }
 517
 518         return 0;
 519 }
 520
 521 int board_late_init(void)
 522 {
 523         u32 reg = 0;
 524         u8 bootmode;
 525         struct udevice *dev;
 526         int bootseq = -1;
 527         int bootseq_len = 0;
 528         int env_targets_len = 0;
 529         const char *mode;
 530         char *new_targets;
 531         char *env_targets;
 532         int ret;
 533
 534 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 535         usb_ether_init();
 536 #endif
 537
 538         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 539                 debug("Saved variables - Skipping\n");
 540                 return 0;
 541         }
 542
 543         ret = set_fdtfile();
 544         if (ret)
 545                 return ret;
 546
 547         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 548         if (ret)
 549                 return -EINVAL;
 550
 551         if (reg >> BOOT_MODE_ALT_SHIFT)
 552                 reg >>= BOOT_MODE_ALT_SHIFT;
 553
 554         bootmode = reg & BOOT_MODES_MASK;
 555
 556         puts("Bootmode: ");
 557         switch (bootmode) {
 558         case USB_MODE:
 559                 puts("USB_MODE\n");
 560                 mode = "usb";
 561                 env_set("modeboot", "usb_dfu_spl");
 562                 break;
 563         case JTAG_MODE:
 564                 puts("JTAG_MODE\n");
 565                 mode = "pxe dhcp";
 566                 env_set("modeboot", "jtagboot");
 567                 break;
 568         case QSPI_MODE_24BIT:
 569         case QSPI_MODE_32BIT:
 570                 mode = "qspi0";
 571                 puts("QSPI_MODE\n");
 572                 env_set("modeboot", "qspiboot");
 573                 break;
 574         case EMMC_MODE:
 575                 puts("EMMC_MODE\n");
 576                 mode = "mmc0";
 577                 env_set("modeboot", "emmcboot");
 578                 break;
 579         case SD_MODE:
 580                 puts("SD_MODE\n");
 581                 if (uclass_get_device_by_name(UCLASS_MMC,
 582                                               "mmc@ff160000", &dev) &&
 583                     uclass_get_device_by_name(UCLASS_MMC,
 584                                               "sdhci@ff160000", &dev)) {
 585                         puts("Boot from SD0 but without SD0 enabled!\n");
 586                         return -1;
 587                 }
 588                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 589
 590                 mode = "mmc";
 591                 bootseq = dev->seq;
 592                 env_set("modeboot", "sdboot");
 593                 break;
 594         case SD1_LSHFT_MODE:
 595                 puts("LVL_SHFT_");
 596                 /* fall through */
 597         case SD_MODE1:
 598                 puts("SD_MODE1\n");
 599                 if (uclass_get_device_by_name(UCLASS_MMC,
 600                                               "mmc@ff170000", &dev) &&
 601                     uclass_get_device_by_name(UCLASS_MMC,
 602                                               "sdhci@ff170000", &dev)) {
 603                         puts("Boot from SD1 but without SD1 enabled!\n");
 604                         return -1;
 605                 }
 606                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 607
 608                 mode = "mmc";
 609                 bootseq = dev->seq;
 610                 env_set("modeboot", "sdboot");
 611                 break;
 612         case NAND_MODE:
 613                 puts("NAND_MODE\n");
 614                 mode = "nand0";
 615                 env_set("modeboot", "nandboot");
 616                 break;
 617         default:
 618                 mode = "";
 619                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 620                 break;
 621         }
 622
 623         if (bootseq >= 0) {
 624                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 625                 debug("Bootseq len: %x\n", bootseq_len);
 626         }
 627
 628         /*
 629          * One terminating char + one byte for space between mode
 630          * and default boot_targets
 631          */
 632         env_targets = env_get("boot_targets");
 633         if (env_targets)
 634                 env_targets_len = strlen(env_targets);
 635
 636         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 637                              bootseq_len);
 638         if (!new_targets)
 639                 return -ENOMEM;
 640
 641         if (bootseq >= 0)
 642                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 643                         env_targets ? env_targets : "");
 644         else
 645                 sprintf(new_targets, "%s %s", mode,
 646                         env_targets ? env_targets : "");
 647
 648         env_set("boot_targets", new_targets);
 649
 650         reset_reason();
 651
 652         return 0;
 653 }
 654 #endif
 655
 656 int checkboard(void)
 657 {
 658         puts("Board: Xilinx ZynqMP\n");
 659         return 0;
 660 }