board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <sata.h>
  16 #include <ahci.h>
  17 #include <scsi.h>
  18 #include <malloc.h>
  19 #include <wdt.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/psu_init_gpl.h>
  24 #include <asm/cache.h>
  25 #include <asm/io.h>
  26 #include <asm/ptrace.h>
  27 #include <dm/device.h>
  28 #include <dm/uclass.h>
  29 #include <usb.h>
  30 #include <dwc3-uboot.h>
  31 #include <zynqmppl.h>
  32 #include <zynqmp_firmware.h>
  33 #include <g_dnl.h>
  34 #include "../common/board.h"
  35
  36 #include "pm_cfg_obj.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  41     !defined(CONFIG_SPL_BUILD)
  42 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  43
  44 static const struct {
  45         u32 id;
  46         u32 ver;
  47         char *name;
  48         bool evexists;
  49 } zynqmp_devices[] = {
  50         {
  51                 .id = 0x10,
  52                 .name = "3eg",
  53         },
  54         {
  55                 .id = 0x10,
  56                 .ver = 0x2c,
  57                 .name = "3cg",
  58         },
  59         {
  60                 .id = 0x11,
  61                 .name = "2eg",
  62         },
  63         {
  64                 .id = 0x11,
  65                 .ver = 0x2c,
  66                 .name = "2cg",
  67         },
  68         {
  69                 .id = 0x20,
  70                 .name = "5ev",
  71                 .evexists = 1,
  72         },
  73         {
  74                 .id = 0x20,
  75                 .ver = 0x100,
  76                 .name = "5eg",
  77                 .evexists = 1,
  78         },
  79         {
  80                 .id = 0x20,
  81                 .ver = 0x12c,
  82                 .name = "5cg",
  83                 .evexists = 1,
  84         },
  85         {
  86                 .id = 0x21,
  87                 .name = "4ev",
  88                 .evexists = 1,
  89         },
  90         {
  91                 .id = 0x21,
  92                 .ver = 0x100,
  93                 .name = "4eg",
  94                 .evexists = 1,
  95         },
  96         {
  97                 .id = 0x21,
  98                 .ver = 0x12c,
  99                 .name = "4cg",
 100                 .evexists = 1,
 101         },
 102         {
 103                 .id = 0x30,
 104                 .name = "7ev",
 105                 .evexists = 1,
 106         },
 107         {
 108                 .id = 0x30,
 109                 .ver = 0x100,
 110                 .name = "7eg",
 111                 .evexists = 1,
 112         },
 113         {
 114                 .id = 0x30,
 115                 .ver = 0x12c,
 116                 .name = "7cg",
 117                 .evexists = 1,
 118         },
 119         {
 120                 .id = 0x38,
 121                 .name = "9eg",
 122         },
 123         {
 124                 .id = 0x38,
 125                 .ver = 0x2c,
 126                 .name = "9cg",
 127         },
 128         {
 129                 .id = 0x39,
 130                 .name = "6eg",
 131         },
 132         {
 133                 .id = 0x39,
 134                 .ver = 0x2c,
 135                 .name = "6cg",
 136         },
 137         {
 138                 .id = 0x40,
 139                 .name = "11eg",
 140         },
 141         { /* For testing purpose only */
 142                 .id = 0x50,
 143                 .ver = 0x2c,
 144                 .name = "15cg",
 145         },
 146         {
 147                 .id = 0x50,
 148                 .name = "15eg",
 149         },
 150         {
 151                 .id = 0x58,
 152                 .name = "19eg",
 153         },
 154         {
 155                 .id = 0x59,
 156                 .name = "17eg",
 157         },
 158         {
 159                 .id = 0x61,
 160                 .name = "21dr",
 161         },
 162         {
 163                 .id = 0x63,
 164                 .name = "23dr",
 165         },
 166         {
 167                 .id = 0x65,
 168                 .name = "25dr",
 169         },
 170         {
 171                 .id = 0x64,
 172                 .name = "27dr",
 173         },
 174         {
 175                 .id = 0x60,
 176                 .name = "28dr",
 177         },
 178         {
 179                 .id = 0x62,
 180                 .name = "29dr",
 181         },
 182         {
 183                 .id = 0x66,
 184                 .name = "39dr",
 185         },
 186         {
 187                 .id = 0x7b,
 188                 .name = "48dr",
 189         },
 190         {
 191                 .id = 0x7e,
 192                 .name = "49dr",
 193         },
 194 };
 195 #endif
 196
 197 int chip_id(unsigned char id)
 198 {
 199         struct pt_regs regs;
 200         int val = -EINVAL;
 201
 202         if (current_el() != 3) {
 203                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 204                 regs.regs[1] = 0;
 205                 regs.regs[2] = 0;
 206                 regs.regs[3] = 0;
 207
 208                 smc_call(&regs);
 209
 210                 /*
 211                  * SMC returns:
 212                  * regs[0][31:0]  = status of the operation
 213                  * regs[0][63:32] = CSU.IDCODE register
 214                  * regs[1][31:0]  = CSU.version register
 215                  * regs[1][63:32] = CSU.IDCODE2 register
 216                  */
 217                 switch (id) {
 218                 case IDCODE:
 219                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 220                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 221                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 222                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 223                         val = regs.regs[0];
 224                         break;
 225                 case VERSION:
 226                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 227                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 228                         val = regs.regs[1];
 229                         break;
 230                 case IDCODE2:
 231                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 232                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 233                         val = regs.regs[1];
 234                         break;
 235                 default:
 236                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 237                 }
 238         } else {
 239                 switch (id) {
 240                 case IDCODE:
 241                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 242                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 243                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 244                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 245                         break;
 246                 case VERSION:
 247                         val = readl(ZYNQMP_CSU_VER_ADDR);
 248                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 249                         break;
 250                 default:
 251                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 252                 }
 253         }
 254
 255         return val;
 256 }
 257
 258 #define ZYNQMP_VERSION_SIZE             9
 259 #define ZYNQMP_PL_STATUS_BIT            9
 260 #define ZYNQMP_IPDIS_VCU_BIT            8
 261 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 262 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 263 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 264                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 265 #define MAX_VARIANTS_EV                 3
 266
 267 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 268         !defined(CONFIG_SPL_BUILD)
 269 static char *zynqmp_get_silicon_idcode_name(void)
 270 {
 271         u32 i, id, ver, j;
 272         char *buf;
 273         static char name[ZYNQMP_VERSION_SIZE];
 274
 275         id = chip_id(IDCODE);
 276         ver = chip_id(IDCODE2);
 277
 278         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 279                 if (zynqmp_devices[i].id == id) {
 280                         if (zynqmp_devices[i].evexists &&
 281                             !(ver & ZYNQMP_PL_STATUS_MASK))
 282                                 break;
 283                         if (zynqmp_devices[i].ver == (ver &
 284                             ZYNQMP_CSU_VERSION_MASK))
 285                                 break;
 286                 }
 287         }
 288
 289         if (i >= ARRAY_SIZE(zynqmp_devices))
 290                 return "unknown";
 291
 292         strncat(name, "zu", 2);
 293         if (!zynqmp_devices[i].evexists ||
 294             (ver & ZYNQMP_PL_STATUS_MASK)) {
 295                 strncat(name, zynqmp_devices[i].name,
 296                         ZYNQMP_VERSION_SIZE - 3);
 297                 return name;
 298         }
 299
 300         /*
 301          * Here we are means, PL not powered up and ev variant
 302          * exists. So, we need to ignore VCU disable bit(8) in
 303          * version and findout if its CG or EG/EV variant.
 304          */
 305         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 306                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 307                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 308                         strncat(name, zynqmp_devices[i].name,
 309                                 ZYNQMP_VERSION_SIZE - 3);
 310                         break;
 311                 }
 312         }
 313
 314         if (j >= MAX_VARIANTS_EV)
 315                 return "unknown";
 316
 317         if (strstr(name, "eg") || strstr(name, "ev")) {
 318                 buf = strstr(name, "e");
 319                 *buf = '\0';
 320         }
 321
 322         return name;
 323 }
 324 #endif
 325
 326 int board_early_init_f(void)
 327 {
 328 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 329         int ret;
 330
 331         ret = psu_init();
 332         if (ret)
 333                 return ret;
 334
 335         /* Delay is required for clocks to be propagated */
 336         udelay(1000000);
 337 #endif
 338
 339 #ifdef CONFIG_DEBUG_UART
 340         /* Uart debug for sure */
 341         debug_uart_init();
 342         puts("Debug uart enabled\n"); /* or printch() */
 343 #endif
 344
 345         return 0;
 346 }
 347
 348 static int multi_boot(void)
 349 {
 350         u32 multiboot;
 351
 352         multiboot = readl(&csu_base->multi_boot);
 353
 354         printf("Multiboot:\t%x\n", multiboot);
 355
 356         return 0;
 357 }
 358
 359 int board_init(void)
 360 {
 361 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 362         struct udevice *dev;
 363
 364         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 365         if (!dev)
 366                 panic("PMU Firmware device not found - Enable it");
 367 #endif
 368
 369 #if defined(CONFIG_SPL_BUILD)
 370         /* Check *at build time* if the filename is an non-empty string */
 371         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 372                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 373                                                 zynqmp_pm_cfg_obj_size);
 374 #endif
 375
 376         printf("EL Level:\tEL%d\n", current_el());
 377
 378 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 379     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 380     defined(CONFIG_SPL_BUILD))
 381         if (current_el() != 3) {
 382                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 383                 printf("Chip ID:\t%s\n", zynqmppl.name);
 384                 fpga_init();
 385                 fpga_add(fpga_xilinx, &zynqmppl);
 386         }
 387 #endif
 388
 389         if (current_el() == 3)
 390                 multi_boot();
 391
 392         return 0;
 393 }
 394
 395 int board_early_init_r(void)
 396 {
 397         u32 val;
 398
 399         if (current_el() != 3)
 400                 return 0;
 401
 402         val = readl(&crlapb_base->timestamp_ref_ctrl);
 403         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 404
 405         if (!val) {
 406                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 407                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 408                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 409
 410                 /* Program freq register in System counter */
 411                 writel(zynqmp_get_system_timer_freq(),
 412                        &iou_scntr_secure->base_frequency_id_register);
 413                 /* And enable system counter */
 414                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 415                        &iou_scntr_secure->counter_control_register);
 416         }
 417         return 0;
 418 }
 419
 420 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 421                          char *const argv[])
 422 {
 423         int ret = 0;
 424
 425         if (current_el() > 1) {
 426                 smp_kick_all_cpus();
 427                 dcache_disable();
 428                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 429                                     ES_TO_AARCH64);
 430         } else {
 431                 printf("FAIL: current EL is not above EL1\n");
 432                 ret = EINVAL;
 433         }
 434         return ret;
 435 }
 436
 437 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 438 int dram_init_banksize(void)
 439 {
 440         int ret;
 441
 442         ret = fdtdec_setup_memory_banksize();
 443         if (ret)
 444                 return ret;
 445
 446         mem_map_fill();
 447
 448         return 0;
 449 }
 450
 451 int dram_init(void)
 452 {
 453         if (fdtdec_setup_mem_size_base() != 0)
 454                 return -EINVAL;
 455
 456         return 0;
 457 }
 458 #else
 459 int dram_init_banksize(void)
 460 {
 461 #if defined(CONFIG_NR_DRAM_BANKS)
 462         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 463         gd->bd->bi_dram[0].size = get_effective_memsize();
 464 #endif
 465
 466         mem_map_fill();
 467
 468         return 0;
 469 }
 470
 471 int dram_init(void)
 472 {
 473         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 474                                     CONFIG_SYS_SDRAM_SIZE);
 475
 476         return 0;
 477 }
 478 #endif
 479
 480 void reset_cpu(ulong addr)
 481 {
 482 }
 483
 484 #if defined(CONFIG_BOARD_LATE_INIT)
 485 static const struct {
 486         u32 bit;
 487         const char *name;
 488 } reset_reasons[] = {
 489         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 490         { RESET_REASON_SOFT, "SOFT" },
 491         { RESET_REASON_SRST, "SRST" },
 492         { RESET_REASON_PSONLY, "PS-ONLY" },
 493         { RESET_REASON_PMU, "PMU" },
 494         { RESET_REASON_INTERNAL, "INTERNAL" },
 495         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 496         {}
 497 };
 498
 499 static int reset_reason(void)
 500 {
 501         u32 reg;
 502         int i, ret;
 503         const char *reason = NULL;
 504
 505         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 506         if (ret)
 507                 return -EINVAL;
 508
 509         puts("Reset reason:\t");
 510
 511         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 512                 if (reg & reset_reasons[i].bit) {
 513                         reason = reset_reasons[i].name;
 514                         printf("%s ", reset_reasons[i].name);
 515                         break;
 516                 }
 517         }
 518
 519         puts("\n");
 520
 521         env_set("reset_reason", reason);
 522
 523         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 524         if (ret)
 525                 return -EINVAL;
 526
 527         return ret;
 528 }
 529
 530 static int set_fdtfile(void)
 531 {
 532         char *compatible, *fdtfile;
 533         const char *suffix = ".dtb";
 534         const char *vendor = "xilinx/";
 535
 536         if (env_get("fdtfile"))
 537                 return 0;
 538
 539         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 540         if (compatible) {
 541                 debug("Compatible: %s\n", compatible);
 542
 543                 /* Discard vendor prefix */
 544                 strsep(&compatible, ",");
 545
 546                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 547                                  strlen(suffix) + 1);
 548                 if (!fdtfile)
 549                         return -ENOMEM;
 550
 551                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 552
 553                 env_set("fdtfile", fdtfile);
 554                 free(fdtfile);
 555         }
 556
 557         return 0;
 558 }
 559
 560 static u8 zynqmp_get_bootmode(void)
 561 {
 562         u8 bootmode;
 563         u32 reg = 0;
 564         int ret;
 565
 566         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 567         if (ret)
 568                 return -EINVAL;
 569
 570         if (reg >> BOOT_MODE_ALT_SHIFT)
 571                 reg >>= BOOT_MODE_ALT_SHIFT;
 572
 573         bootmode = reg & BOOT_MODES_MASK;
 574
 575         return bootmode;
 576 }
 577
 578 int board_late_init(void)
 579 {
 580         u8 bootmode;
 581         struct udevice *dev;
 582         int bootseq = -1;
 583         int bootseq_len = 0;
 584         int env_targets_len = 0;
 585         const char *mode;
 586         char *new_targets;
 587         char *env_targets;
 588         int ret;
 589
 590 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 591         usb_ether_init();
 592 #endif
 593
 594         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 595                 debug("Saved variables - Skipping\n");
 596                 return 0;
 597         }
 598
 599         ret = set_fdtfile();
 600         if (ret)
 601                 return ret;
 602
 603         bootmode = zynqmp_get_bootmode();
 604
 605         puts("Bootmode: ");
 606         switch (bootmode) {
 607         case USB_MODE:
 608                 puts("USB_MODE\n");
 609                 mode = "usb";
 610                 env_set("modeboot", "usb_dfu_spl");
 611                 break;
 612         case JTAG_MODE:
 613                 puts("JTAG_MODE\n");
 614                 mode = "jtag pxe dhcp";
 615                 env_set("modeboot", "jtagboot");
 616                 break;
 617         case QSPI_MODE_24BIT:
 618         case QSPI_MODE_32BIT:
 619                 mode = "qspi0";
 620                 puts("QSPI_MODE\n");
 621                 env_set("modeboot", "qspiboot");
 622                 break;
 623         case EMMC_MODE:
 624                 puts("EMMC_MODE\n");
 625                 if (uclass_get_device_by_name(UCLASS_MMC,
 626                                               "mmc@ff160000", &dev) &&
 627                     uclass_get_device_by_name(UCLASS_MMC,
 628                                               "sdhci@ff160000", &dev)) {
 629                         puts("Boot from EMMC but without SD0 enabled!\n");
 630                         return -1;
 631                 }
 632                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 633
 634                 mode = "mmc";
 635                 bootseq = dev->seq;
 636                 break;
 637         case SD_MODE:
 638                 puts("SD_MODE\n");
 639                 if (uclass_get_device_by_name(UCLASS_MMC,
 640                                               "mmc@ff160000", &dev) &&
 641                     uclass_get_device_by_name(UCLASS_MMC,
 642                                               "sdhci@ff160000", &dev)) {
 643                         puts("Boot from SD0 but without SD0 enabled!\n");
 644                         return -1;
 645                 }
 646                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 647
 648                 mode = "mmc";
 649                 bootseq = dev->seq;
 650                 env_set("modeboot", "sdboot");
 651                 break;
 652         case SD1_LSHFT_MODE:
 653                 puts("LVL_SHFT_");
 654                 /* fall through */
 655         case SD_MODE1:
 656                 puts("SD_MODE1\n");
 657                 if (uclass_get_device_by_name(UCLASS_MMC,
 658                                               "mmc@ff170000", &dev) &&
 659                     uclass_get_device_by_name(UCLASS_MMC,
 660                                               "sdhci@ff170000", &dev)) {
 661                         puts("Boot from SD1 but without SD1 enabled!\n");
 662                         return -1;
 663                 }
 664                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 665
 666                 mode = "mmc";
 667                 bootseq = dev->seq;
 668                 env_set("modeboot", "sdboot");
 669                 break;
 670         case NAND_MODE:
 671                 puts("NAND_MODE\n");
 672                 mode = "nand0";
 673                 env_set("modeboot", "nandboot");
 674                 break;
 675         default:
 676                 mode = "";
 677                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 678                 break;
 679         }
 680
 681         if (bootseq >= 0) {
 682                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 683                 debug("Bootseq len: %x\n", bootseq_len);
 684         }
 685
 686         /*
 687          * One terminating char + one byte for space between mode
 688          * and default boot_targets
 689          */
 690         env_targets = env_get("boot_targets");
 691         if (env_targets)
 692                 env_targets_len = strlen(env_targets);
 693
 694         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 695                              bootseq_len);
 696         if (!new_targets)
 697                 return -ENOMEM;
 698
 699         if (bootseq >= 0)
 700                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 701                         env_targets ? env_targets : "");
 702         else
 703                 sprintf(new_targets, "%s %s", mode,
 704                         env_targets ? env_targets : "");
 705
 706         env_set("boot_targets", new_targets);
 707
 708         reset_reason();
 709
 710         return board_late_init_xilinx();
 711 }
 712 #endif
 713
 714 int checkboard(void)
 715 {
 716         puts("Board: Xilinx ZynqMP\n");
 717         return 0;
 718 }