board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <net.h>
  14 #include <sata.h>
  15 #include <ahci.h>
  16 #include <scsi.h>
  17 #include <malloc.h>
  18 #include <wdt.h>
  19 #include <asm/arch/clk.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/psu_init_gpl.h>
  23 #include <asm/cache.h>
  24 #include <asm/io.h>
  25 #include <dm/device.h>
  26 #include <dm/uclass.h>
  27 #include <usb.h>
  28 #include <dwc3-uboot.h>
  29 #include <zynqmppl.h>
  30 #include <zynqmp_firmware.h>
  31 #include <g_dnl.h>
  32 #include "../common/board.h"
  33
  34 #include "pm_cfg_obj.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  39     !defined(CONFIG_SPL_BUILD)
  40 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  41
  42 static const struct {
  43         u32 id;
  44         u32 ver;
  45         char *name;
  46         bool evexists;
  47 } zynqmp_devices[] = {
  48         {
  49                 .id = 0x10,
  50                 .name = "3eg",
  51         },
  52         {
  53                 .id = 0x10,
  54                 .ver = 0x2c,
  55                 .name = "3cg",
  56         },
  57         {
  58                 .id = 0x11,
  59                 .name = "2eg",
  60         },
  61         {
  62                 .id = 0x11,
  63                 .ver = 0x2c,
  64                 .name = "2cg",
  65         },
  66         {
  67                 .id = 0x20,
  68                 .name = "5ev",
  69                 .evexists = 1,
  70         },
  71         {
  72                 .id = 0x20,
  73                 .ver = 0x100,
  74                 .name = "5eg",
  75                 .evexists = 1,
  76         },
  77         {
  78                 .id = 0x20,
  79                 .ver = 0x12c,
  80                 .name = "5cg",
  81                 .evexists = 1,
  82         },
  83         {
  84                 .id = 0x21,
  85                 .name = "4ev",
  86                 .evexists = 1,
  87         },
  88         {
  89                 .id = 0x21,
  90                 .ver = 0x100,
  91                 .name = "4eg",
  92                 .evexists = 1,
  93         },
  94         {
  95                 .id = 0x21,
  96                 .ver = 0x12c,
  97                 .name = "4cg",
  98                 .evexists = 1,
  99         },
 100         {
 101                 .id = 0x30,
 102                 .name = "7ev",
 103                 .evexists = 1,
 104         },
 105         {
 106                 .id = 0x30,
 107                 .ver = 0x100,
 108                 .name = "7eg",
 109                 .evexists = 1,
 110         },
 111         {
 112                 .id = 0x30,
 113                 .ver = 0x12c,
 114                 .name = "7cg",
 115                 .evexists = 1,
 116         },
 117         {
 118                 .id = 0x38,
 119                 .name = "9eg",
 120         },
 121         {
 122                 .id = 0x38,
 123                 .ver = 0x2c,
 124                 .name = "9cg",
 125         },
 126         {
 127                 .id = 0x39,
 128                 .name = "6eg",
 129         },
 130         {
 131                 .id = 0x39,
 132                 .ver = 0x2c,
 133                 .name = "6cg",
 134         },
 135         {
 136                 .id = 0x40,
 137                 .name = "11eg",
 138         },
 139         { /* For testing purpose only */
 140                 .id = 0x50,
 141                 .ver = 0x2c,
 142                 .name = "15cg",
 143         },
 144         {
 145                 .id = 0x50,
 146                 .name = "15eg",
 147         },
 148         {
 149                 .id = 0x58,
 150                 .name = "19eg",
 151         },
 152         {
 153                 .id = 0x59,
 154                 .name = "17eg",
 155         },
 156         {
 157                 .id = 0x61,
 158                 .name = "21dr",
 159         },
 160         {
 161                 .id = 0x63,
 162                 .name = "23dr",
 163         },
 164         {
 165                 .id = 0x65,
 166                 .name = "25dr",
 167         },
 168         {
 169                 .id = 0x64,
 170                 .name = "27dr",
 171         },
 172         {
 173                 .id = 0x60,
 174                 .name = "28dr",
 175         },
 176         {
 177                 .id = 0x62,
 178                 .name = "29dr",
 179         },
 180         {
 181                 .id = 0x66,
 182                 .name = "39dr",
 183         },
 184         {
 185                 .id = 0x7b,
 186                 .name = "48dr",
 187         },
 188         {
 189                 .id = 0x7e,
 190                 .name = "49dr",
 191         },
 192 };
 193 #endif
 194
 195 int chip_id(unsigned char id)
 196 {
 197         struct pt_regs regs;
 198         int val = -EINVAL;
 199
 200         if (current_el() != 3) {
 201                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 202                 regs.regs[1] = 0;
 203                 regs.regs[2] = 0;
 204                 regs.regs[3] = 0;
 205
 206                 smc_call(&regs);
 207
 208                 /*
 209                  * SMC returns:
 210                  * regs[0][31:0]  = status of the operation
 211                  * regs[0][63:32] = CSU.IDCODE register
 212                  * regs[1][31:0]  = CSU.version register
 213                  * regs[1][63:32] = CSU.IDCODE2 register
 214                  */
 215                 switch (id) {
 216                 case IDCODE:
 217                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 218                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 219                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 220                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 221                         val = regs.regs[0];
 222                         break;
 223                 case VERSION:
 224                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 225                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 226                         val = regs.regs[1];
 227                         break;
 228                 case IDCODE2:
 229                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 230                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 231                         val = regs.regs[1];
 232                         break;
 233                 default:
 234                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 235                 }
 236         } else {
 237                 switch (id) {
 238                 case IDCODE:
 239                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 240                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 241                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 242                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 243                         break;
 244                 case VERSION:
 245                         val = readl(ZYNQMP_CSU_VER_ADDR);
 246                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 247                         break;
 248                 default:
 249                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 250                 }
 251         }
 252
 253         return val;
 254 }
 255
 256 #define ZYNQMP_VERSION_SIZE             9
 257 #define ZYNQMP_PL_STATUS_BIT            9
 258 #define ZYNQMP_IPDIS_VCU_BIT            8
 259 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 260 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 261 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 262                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 263 #define MAX_VARIANTS_EV                 3
 264
 265 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 266         !defined(CONFIG_SPL_BUILD)
 267 static char *zynqmp_get_silicon_idcode_name(void)
 268 {
 269         u32 i, id, ver, j;
 270         char *buf;
 271         static char name[ZYNQMP_VERSION_SIZE];
 272
 273         id = chip_id(IDCODE);
 274         ver = chip_id(IDCODE2);
 275
 276         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 277                 if (zynqmp_devices[i].id == id) {
 278                         if (zynqmp_devices[i].evexists &&
 279                             !(ver & ZYNQMP_PL_STATUS_MASK))
 280                                 break;
 281                         if (zynqmp_devices[i].ver == (ver &
 282                             ZYNQMP_CSU_VERSION_MASK))
 283                                 break;
 284                 }
 285         }
 286
 287         if (i >= ARRAY_SIZE(zynqmp_devices))
 288                 return "unknown";
 289
 290         strncat(name, "zu", 2);
 291         if (!zynqmp_devices[i].evexists ||
 292             (ver & ZYNQMP_PL_STATUS_MASK)) {
 293                 strncat(name, zynqmp_devices[i].name,
 294                         ZYNQMP_VERSION_SIZE - 3);
 295                 return name;
 296         }
 297
 298         /*
 299          * Here we are means, PL not powered up and ev variant
 300          * exists. So, we need to ignore VCU disable bit(8) in
 301          * version and findout if its CG or EG/EV variant.
 302          */
 303         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 304                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 305                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 306                         strncat(name, zynqmp_devices[i].name,
 307                                 ZYNQMP_VERSION_SIZE - 3);
 308                         break;
 309                 }
 310         }
 311
 312         if (j >= MAX_VARIANTS_EV)
 313                 return "unknown";
 314
 315         if (strstr(name, "eg") || strstr(name, "ev")) {
 316                 buf = strstr(name, "e");
 317                 *buf = '\0';
 318         }
 319
 320         return name;
 321 }
 322 #endif
 323
 324 int board_early_init_f(void)
 325 {
 326 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 327         int ret;
 328
 329         ret = psu_init();
 330         if (ret)
 331                 return ret;
 332
 333         /* Delay is required for clocks to be propagated */
 334         udelay(1000000);
 335 #endif
 336
 337 #ifdef CONFIG_DEBUG_UART
 338         /* Uart debug for sure */
 339         debug_uart_init();
 340         puts("Debug uart enabled\n"); /* or printch() */
 341 #endif
 342
 343         return 0;
 344 }
 345
 346 static int multi_boot(void)
 347 {
 348         u32 multiboot;
 349
 350         multiboot = readl(&csu_base->multi_boot);
 351
 352         printf("Multiboot:\t%x\n", multiboot);
 353
 354         return 0;
 355 }
 356
 357 int board_init(void)
 358 {
 359 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 360         struct udevice *dev;
 361
 362         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 363         if (!dev)
 364                 panic("PMU Firmware device not found - Enable it");
 365 #endif
 366
 367 #if defined(CONFIG_SPL_BUILD)
 368         /* Check *at build time* if the filename is an non-empty string */
 369         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 370                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 371                                                 zynqmp_pm_cfg_obj_size);
 372 #endif
 373
 374         printf("EL Level:\tEL%d\n", current_el());
 375
 376 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 377     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 378     defined(CONFIG_SPL_BUILD))
 379         if (current_el() != 3) {
 380                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 381                 printf("Chip ID:\t%s\n", zynqmppl.name);
 382                 fpga_init();
 383                 fpga_add(fpga_xilinx, &zynqmppl);
 384         }
 385 #endif
 386
 387         if (current_el() == 3)
 388                 multi_boot();
 389
 390         return 0;
 391 }
 392
 393 int board_early_init_r(void)
 394 {
 395         u32 val;
 396
 397         if (current_el() != 3)
 398                 return 0;
 399
 400         val = readl(&crlapb_base->timestamp_ref_ctrl);
 401         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 402
 403         if (!val) {
 404                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 405                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 406                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 407
 408                 /* Program freq register in System counter */
 409                 writel(zynqmp_get_system_timer_freq(),
 410                        &iou_scntr_secure->base_frequency_id_register);
 411                 /* And enable system counter */
 412                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 413                        &iou_scntr_secure->counter_control_register);
 414         }
 415         return 0;
 416 }
 417
 418 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 419                          char *const argv[])
 420 {
 421         int ret = 0;
 422
 423         if (current_el() > 1) {
 424                 smp_kick_all_cpus();
 425                 dcache_disable();
 426                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 427                                     ES_TO_AARCH64);
 428         } else {
 429                 printf("FAIL: current EL is not above EL1\n");
 430                 ret = EINVAL;
 431         }
 432         return ret;
 433 }
 434
 435 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 436 int dram_init_banksize(void)
 437 {
 438         int ret;
 439
 440         ret = fdtdec_setup_memory_banksize();
 441         if (ret)
 442                 return ret;
 443
 444         mem_map_fill();
 445
 446         return 0;
 447 }
 448
 449 int dram_init(void)
 450 {
 451         if (fdtdec_setup_mem_size_base() != 0)
 452                 return -EINVAL;
 453
 454         return 0;
 455 }
 456 #else
 457 int dram_init_banksize(void)
 458 {
 459 #if defined(CONFIG_NR_DRAM_BANKS)
 460         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 461         gd->bd->bi_dram[0].size = get_effective_memsize();
 462 #endif
 463
 464         mem_map_fill();
 465
 466         return 0;
 467 }
 468
 469 int dram_init(void)
 470 {
 471         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 472                                     CONFIG_SYS_SDRAM_SIZE);
 473
 474         return 0;
 475 }
 476 #endif
 477
 478 void reset_cpu(ulong addr)
 479 {
 480 }
 481
 482 #if defined(CONFIG_BOARD_LATE_INIT)
 483 static const struct {
 484         u32 bit;
 485         const char *name;
 486 } reset_reasons[] = {
 487         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 488         { RESET_REASON_SOFT, "SOFT" },
 489         { RESET_REASON_SRST, "SRST" },
 490         { RESET_REASON_PSONLY, "PS-ONLY" },
 491         { RESET_REASON_PMU, "PMU" },
 492         { RESET_REASON_INTERNAL, "INTERNAL" },
 493         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 494         {}
 495 };
 496
 497 static int reset_reason(void)
 498 {
 499         u32 reg;
 500         int i, ret;
 501         const char *reason = NULL;
 502
 503         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 504         if (ret)
 505                 return -EINVAL;
 506
 507         puts("Reset reason:\t");
 508
 509         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 510                 if (reg & reset_reasons[i].bit) {
 511                         reason = reset_reasons[i].name;
 512                         printf("%s ", reset_reasons[i].name);
 513                         break;
 514                 }
 515         }
 516
 517         puts("\n");
 518
 519         env_set("reset_reason", reason);
 520
 521         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 522         if (ret)
 523                 return -EINVAL;
 524
 525         return ret;
 526 }
 527
 528 static int set_fdtfile(void)
 529 {
 530         char *compatible, *fdtfile;
 531         const char *suffix = ".dtb";
 532         const char *vendor = "xilinx/";
 533
 534         if (env_get("fdtfile"))
 535                 return 0;
 536
 537         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 538         if (compatible) {
 539                 debug("Compatible: %s\n", compatible);
 540
 541                 /* Discard vendor prefix */
 542                 strsep(&compatible, ",");
 543
 544                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 545                                  strlen(suffix) + 1);
 546                 if (!fdtfile)
 547                         return -ENOMEM;
 548
 549                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 550
 551                 env_set("fdtfile", fdtfile);
 552                 free(fdtfile);
 553         }
 554
 555         return 0;
 556 }
 557
 558 static u8 zynqmp_get_bootmode(void)
 559 {
 560         u8 bootmode;
 561         u32 reg = 0;
 562         int ret;
 563
 564         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 565         if (ret)
 566                 return -EINVAL;
 567
 568         if (reg >> BOOT_MODE_ALT_SHIFT)
 569                 reg >>= BOOT_MODE_ALT_SHIFT;
 570
 571         bootmode = reg & BOOT_MODES_MASK;
 572
 573         return bootmode;
 574 }
 575
 576 int board_late_init(void)
 577 {
 578         u8 bootmode;
 579         struct udevice *dev;
 580         int bootseq = -1;
 581         int bootseq_len = 0;
 582         int env_targets_len = 0;
 583         const char *mode;
 584         char *new_targets;
 585         char *env_targets;
 586         int ret;
 587
 588 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 589         usb_ether_init();
 590 #endif
 591
 592         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 593                 debug("Saved variables - Skipping\n");
 594                 return 0;
 595         }
 596
 597         ret = set_fdtfile();
 598         if (ret)
 599                 return ret;
 600
 601         bootmode = zynqmp_get_bootmode();
 602
 603         puts("Bootmode: ");
 604         switch (bootmode) {
 605         case USB_MODE:
 606                 puts("USB_MODE\n");
 607                 mode = "usb";
 608                 env_set("modeboot", "usb_dfu_spl");
 609                 break;
 610         case JTAG_MODE:
 611                 puts("JTAG_MODE\n");
 612                 mode = "jtag pxe dhcp";
 613                 env_set("modeboot", "jtagboot");
 614                 break;
 615         case QSPI_MODE_24BIT:
 616         case QSPI_MODE_32BIT:
 617                 mode = "qspi0";
 618                 puts("QSPI_MODE\n");
 619                 env_set("modeboot", "qspiboot");
 620                 break;
 621         case EMMC_MODE:
 622                 puts("EMMC_MODE\n");
 623                 if (uclass_get_device_by_name(UCLASS_MMC,
 624                                               "mmc@ff160000", &dev) &&
 625                     uclass_get_device_by_name(UCLASS_MMC,
 626                                               "sdhci@ff160000", &dev)) {
 627                         puts("Boot from EMMC but without SD0 enabled!\n");
 628                         return -1;
 629                 }
 630                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 631
 632                 mode = "mmc";
 633                 bootseq = dev->seq;
 634                 break;
 635         case SD_MODE:
 636                 puts("SD_MODE\n");
 637                 if (uclass_get_device_by_name(UCLASS_MMC,
 638                                               "mmc@ff160000", &dev) &&
 639                     uclass_get_device_by_name(UCLASS_MMC,
 640                                               "sdhci@ff160000", &dev)) {
 641                         puts("Boot from SD0 but without SD0 enabled!\n");
 642                         return -1;
 643                 }
 644                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 645
 646                 mode = "mmc";
 647                 bootseq = dev->seq;
 648                 env_set("modeboot", "sdboot");
 649                 break;
 650         case SD1_LSHFT_MODE:
 651                 puts("LVL_SHFT_");
 652                 /* fall through */
 653         case SD_MODE1:
 654                 puts("SD_MODE1\n");
 655                 if (uclass_get_device_by_name(UCLASS_MMC,
 656                                               "mmc@ff170000", &dev) &&
 657                     uclass_get_device_by_name(UCLASS_MMC,
 658                                               "sdhci@ff170000", &dev)) {
 659                         puts("Boot from SD1 but without SD1 enabled!\n");
 660                         return -1;
 661                 }
 662                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 663
 664                 mode = "mmc";
 665                 bootseq = dev->seq;
 666                 env_set("modeboot", "sdboot");
 667                 break;
 668         case NAND_MODE:
 669                 puts("NAND_MODE\n");
 670                 mode = "nand0";
 671                 env_set("modeboot", "nandboot");
 672                 break;
 673         default:
 674                 mode = "";
 675                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 676                 break;
 677         }
 678
 679         if (bootseq >= 0) {
 680                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 681                 debug("Bootseq len: %x\n", bootseq_len);
 682         }
 683
 684         /*
 685          * One terminating char + one byte for space between mode
 686          * and default boot_targets
 687          */
 688         env_targets = env_get("boot_targets");
 689         if (env_targets)
 690                 env_targets_len = strlen(env_targets);
 691
 692         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 693                              bootseq_len);
 694         if (!new_targets)
 695                 return -ENOMEM;
 696
 697         if (bootseq >= 0)
 698                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 699                         env_targets ? env_targets : "");
 700         else
 701                 sprintf(new_targets, "%s %s", mode,
 702                         env_targets ? env_targets : "");
 703
 704         env_set("boot_targets", new_targets);
 705
 706         reset_reason();
 707
 708         return board_late_init_xilinx();
 709 }
 710 #endif
 711
 712 int checkboard(void)
 713 {
 714         puts("Board: Xilinx ZynqMP\n");
 715         return 0;
 716 }