board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <debug_uart.h>
  10 #include <env.h>
  11 #include <init.h>
  12 #include <sata.h>
  13 #include <ahci.h>
  14 #include <scsi.h>
  15 #include <malloc.h>
  16 #include <wdt.h>
  17 #include <asm/arch/clk.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/psu_init_gpl.h>
  21 #include <asm/io.h>
  22 #include <dm/device.h>
  23 #include <dm/uclass.h>
  24 #include <usb.h>
  25 #include <dwc3-uboot.h>
  26 #include <zynqmppl.h>
  27 #include <zynqmp_firmware.h>
  28 #include <g_dnl.h>
  29 #include <linux/sizes.h>
  30
  31 #include "pm_cfg_obj.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  36     !defined(CONFIG_SPL_BUILD)
  37 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  38
  39 static const struct {
  40         u32 id;
  41         u32 ver;
  42         char *name;
  43         bool evexists;
  44 } zynqmp_devices[] = {
  45         {
  46                 .id = 0x10,
  47                 .name = "3eg",
  48         },
  49         {
  50                 .id = 0x10,
  51                 .ver = 0x2c,
  52                 .name = "3cg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .name = "2eg",
  57         },
  58         {
  59                 .id = 0x11,
  60                 .ver = 0x2c,
  61                 .name = "2cg",
  62         },
  63         {
  64                 .id = 0x20,
  65                 .name = "5ev",
  66                 .evexists = 1,
  67         },
  68         {
  69                 .id = 0x20,
  70                 .ver = 0x100,
  71                 .name = "5eg",
  72                 .evexists = 1,
  73         },
  74         {
  75                 .id = 0x20,
  76                 .ver = 0x12c,
  77                 .name = "5cg",
  78                 .evexists = 1,
  79         },
  80         {
  81                 .id = 0x21,
  82                 .name = "4ev",
  83                 .evexists = 1,
  84         },
  85         {
  86                 .id = 0x21,
  87                 .ver = 0x100,
  88                 .name = "4eg",
  89                 .evexists = 1,
  90         },
  91         {
  92                 .id = 0x21,
  93                 .ver = 0x12c,
  94                 .name = "4cg",
  95                 .evexists = 1,
  96         },
  97         {
  98                 .id = 0x30,
  99                 .name = "7ev",
 100                 .evexists = 1,
 101         },
 102         {
 103                 .id = 0x30,
 104                 .ver = 0x100,
 105                 .name = "7eg",
 106                 .evexists = 1,
 107         },
 108         {
 109                 .id = 0x30,
 110                 .ver = 0x12c,
 111                 .name = "7cg",
 112                 .evexists = 1,
 113         },
 114         {
 115                 .id = 0x38,
 116                 .name = "9eg",
 117         },
 118         {
 119                 .id = 0x38,
 120                 .ver = 0x2c,
 121                 .name = "9cg",
 122         },
 123         {
 124                 .id = 0x39,
 125                 .name = "6eg",
 126         },
 127         {
 128                 .id = 0x39,
 129                 .ver = 0x2c,
 130                 .name = "6cg",
 131         },
 132         {
 133                 .id = 0x40,
 134                 .name = "11eg",
 135         },
 136         { /* For testing purpose only */
 137                 .id = 0x50,
 138                 .ver = 0x2c,
 139                 .name = "15cg",
 140         },
 141         {
 142                 .id = 0x50,
 143                 .name = "15eg",
 144         },
 145         {
 146                 .id = 0x58,
 147                 .name = "19eg",
 148         },
 149         {
 150                 .id = 0x59,
 151                 .name = "17eg",
 152         },
 153         {
 154                 .id = 0x61,
 155                 .name = "21dr",
 156         },
 157         {
 158                 .id = 0x63,
 159                 .name = "23dr",
 160         },
 161         {
 162                 .id = 0x65,
 163                 .name = "25dr",
 164         },
 165         {
 166                 .id = 0x64,
 167                 .name = "27dr",
 168         },
 169         {
 170                 .id = 0x60,
 171                 .name = "28dr",
 172         },
 173         {
 174                 .id = 0x62,
 175                 .name = "29dr",
 176         },
 177         {
 178                 .id = 0x66,
 179                 .name = "39dr",
 180         },
 181         {
 182                 .id = 0x7b,
 183                 .name = "48dr",
 184         },
 185         {
 186                 .id = 0x7e,
 187                 .name = "49dr",
 188         },
 189 };
 190 #endif
 191
 192 int chip_id(unsigned char id)
 193 {
 194         struct pt_regs regs;
 195         int val = -EINVAL;
 196
 197         if (current_el() != 3) {
 198                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 199                 regs.regs[1] = 0;
 200                 regs.regs[2] = 0;
 201                 regs.regs[3] = 0;
 202
 203                 smc_call(&regs);
 204
 205                 /*
 206                  * SMC returns:
 207                  * regs[0][31:0]  = status of the operation
 208                  * regs[0][63:32] = CSU.IDCODE register
 209                  * regs[1][31:0]  = CSU.version register
 210                  * regs[1][63:32] = CSU.IDCODE2 register
 211                  */
 212                 switch (id) {
 213                 case IDCODE:
 214                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 215                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 216                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 217                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 218                         val = regs.regs[0];
 219                         break;
 220                 case VERSION:
 221                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 222                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 223                         val = regs.regs[1];
 224                         break;
 225                 case IDCODE2:
 226                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 227                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 228                         val = regs.regs[1];
 229                         break;
 230                 default:
 231                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 232                 }
 233         } else {
 234                 switch (id) {
 235                 case IDCODE:
 236                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 237                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 238                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 239                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 240                         break;
 241                 case VERSION:
 242                         val = readl(ZYNQMP_CSU_VER_ADDR);
 243                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 244                         break;
 245                 default:
 246                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 247                 }
 248         }
 249
 250         return val;
 251 }
 252
 253 #define ZYNQMP_VERSION_SIZE             9
 254 #define ZYNQMP_PL_STATUS_BIT            9
 255 #define ZYNQMP_IPDIS_VCU_BIT            8
 256 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 257 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 258 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 259                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 260 #define MAX_VARIANTS_EV                 3
 261
 262 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 263         !defined(CONFIG_SPL_BUILD)
 264 static char *zynqmp_get_silicon_idcode_name(void)
 265 {
 266         u32 i, id, ver, j;
 267         char *buf;
 268         static char name[ZYNQMP_VERSION_SIZE];
 269
 270         id = chip_id(IDCODE);
 271         ver = chip_id(IDCODE2);
 272
 273         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 274                 if (zynqmp_devices[i].id == id) {
 275                         if (zynqmp_devices[i].evexists &&
 276                             !(ver & ZYNQMP_PL_STATUS_MASK))
 277                                 break;
 278                         if (zynqmp_devices[i].ver == (ver &
 279                             ZYNQMP_CSU_VERSION_MASK))
 280                                 break;
 281                 }
 282         }
 283
 284         if (i >= ARRAY_SIZE(zynqmp_devices))
 285                 return "unknown";
 286
 287         strncat(name, "zu", 2);
 288         if (!zynqmp_devices[i].evexists ||
 289             (ver & ZYNQMP_PL_STATUS_MASK)) {
 290                 strncat(name, zynqmp_devices[i].name,
 291                         ZYNQMP_VERSION_SIZE - 3);
 292                 return name;
 293         }
 294
 295         /*
 296          * Here we are means, PL not powered up and ev variant
 297          * exists. So, we need to ignore VCU disable bit(8) in
 298          * version and findout if its CG or EG/EV variant.
 299          */
 300         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 301                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 302                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 303                         strncat(name, zynqmp_devices[i].name,
 304                                 ZYNQMP_VERSION_SIZE - 3);
 305                         break;
 306                 }
 307         }
 308
 309         if (j >= MAX_VARIANTS_EV)
 310                 return "unknown";
 311
 312         if (strstr(name, "eg") || strstr(name, "ev")) {
 313                 buf = strstr(name, "e");
 314                 *buf = '\0';
 315         }
 316
 317         return name;
 318 }
 319 #endif
 320
 321 int board_early_init_f(void)
 322 {
 323 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 324         int ret;
 325
 326         ret = psu_init();
 327         if (ret)
 328                 return ret;
 329
 330         /* Delay is required for clocks to be propagated */
 331         udelay(1000000);
 332 #endif
 333
 334 #ifdef CONFIG_DEBUG_UART
 335         /* Uart debug for sure */
 336         debug_uart_init();
 337         puts("Debug uart enabled\n"); /* or printch() */
 338 #endif
 339
 340         return 0;
 341 }
 342
 343 static int multi_boot(void)
 344 {
 345         u32 multiboot;
 346
 347         multiboot = readl(&csu_base->multi_boot);
 348
 349         printf("Multiboot:\t%x\n", multiboot);
 350
 351         return 0;
 352 }
 353
 354 int board_init(void)
 355 {
 356 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 357         struct udevice *dev;
 358
 359         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 360         if (!dev)
 361                 panic("PMU Firmware device not found - Enable it");
 362 #endif
 363
 364 #if defined(CONFIG_SPL_BUILD)
 365         /* Check *at build time* if the filename is an non-empty string */
 366         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 367                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 368                                                 zynqmp_pm_cfg_obj_size);
 369 #endif
 370
 371         printf("EL Level:\tEL%d\n", current_el());
 372
 373 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 374     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 375     defined(CONFIG_SPL_BUILD))
 376         if (current_el() != 3) {
 377                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 378                 printf("Chip ID:\t%s\n", zynqmppl.name);
 379                 fpga_init();
 380                 fpga_add(fpga_xilinx, &zynqmppl);
 381         }
 382 #endif
 383
 384         if (current_el() == 3)
 385                 multi_boot();
 386
 387         return 0;
 388 }
 389
 390 int board_early_init_r(void)
 391 {
 392         u32 val;
 393
 394         if (current_el() != 3)
 395                 return 0;
 396
 397         val = readl(&crlapb_base->timestamp_ref_ctrl);
 398         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 399
 400         if (!val) {
 401                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 402                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 403                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 404
 405                 /* Program freq register in System counter */
 406                 writel(zynqmp_get_system_timer_freq(),
 407                        &iou_scntr_secure->base_frequency_id_register);
 408                 /* And enable system counter */
 409                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 410                        &iou_scntr_secure->counter_control_register);
 411         }
 412         return 0;
 413 }
 414
 415 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 416                          char * const argv[])
 417 {
 418         int ret = 0;
 419
 420         if (current_el() > 1) {
 421                 smp_kick_all_cpus();
 422                 dcache_disable();
 423                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 424                                     ES_TO_AARCH64);
 425         } else {
 426                 printf("FAIL: current EL is not above EL1\n");
 427                 ret = EINVAL;
 428         }
 429         return ret;
 430 }
 431
 432 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 433 int dram_init_banksize(void)
 434 {
 435         int ret;
 436
 437         ret = fdtdec_setup_memory_banksize();
 438         if (ret)
 439                 return ret;
 440
 441         mem_map_fill();
 442
 443         return 0;
 444 }
 445
 446 int dram_init(void)
 447 {
 448         if (fdtdec_setup_mem_size_base() != 0)
 449                 return -EINVAL;
 450
 451         return 0;
 452 }
 453 #else
 454 int dram_init_banksize(void)
 455 {
 456 #if defined(CONFIG_NR_DRAM_BANKS)
 457         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 458         gd->bd->bi_dram[0].size = get_effective_memsize();
 459 #endif
 460
 461         mem_map_fill();
 462
 463         return 0;
 464 }
 465
 466 int dram_init(void)
 467 {
 468         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 469                                     CONFIG_SYS_SDRAM_SIZE);
 470
 471         return 0;
 472 }
 473 #endif
 474
 475 void reset_cpu(ulong addr)
 476 {
 477 }
 478
 479 #if defined(CONFIG_BOARD_LATE_INIT)
 480 static const struct {
 481         u32 bit;
 482         const char *name;
 483 } reset_reasons[] = {
 484         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 485         { RESET_REASON_SOFT, "SOFT" },
 486         { RESET_REASON_SRST, "SRST" },
 487         { RESET_REASON_PSONLY, "PS-ONLY" },
 488         { RESET_REASON_PMU, "PMU" },
 489         { RESET_REASON_INTERNAL, "INTERNAL" },
 490         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 491         {}
 492 };
 493
 494 static int reset_reason(void)
 495 {
 496         u32 reg;
 497         int i, ret;
 498         const char *reason = NULL;
 499
 500         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 501         if (ret)
 502                 return -EINVAL;
 503
 504         puts("Reset reason:\t");
 505
 506         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 507                 if (reg & reset_reasons[i].bit) {
 508                         reason = reset_reasons[i].name;
 509                         printf("%s ", reset_reasons[i].name);
 510                         break;
 511                 }
 512         }
 513
 514         puts("\n");
 515
 516         env_set("reset_reason", reason);
 517
 518         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 519         if (ret)
 520                 return -EINVAL;
 521
 522         return ret;
 523 }
 524
 525 static int set_fdtfile(void)
 526 {
 527         char *compatible, *fdtfile;
 528         const char *suffix = ".dtb";
 529         const char *vendor = "xilinx/";
 530
 531         if (env_get("fdtfile"))
 532                 return 0;
 533
 534         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 535         if (compatible) {
 536                 debug("Compatible: %s\n", compatible);
 537
 538                 /* Discard vendor prefix */
 539                 strsep(&compatible, ",");
 540
 541                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 542                                  strlen(suffix) + 1);
 543                 if (!fdtfile)
 544                         return -ENOMEM;
 545
 546                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 547
 548                 env_set("fdtfile", fdtfile);
 549                 free(fdtfile);
 550         }
 551
 552         return 0;
 553 }
 554
 555 int board_late_init(void)
 556 {
 557         u32 reg = 0;
 558         u8 bootmode;
 559         struct udevice *dev;
 560         int bootseq = -1;
 561         int bootseq_len = 0;
 562         int env_targets_len = 0;
 563         const char *mode;
 564         char *new_targets;
 565         char *env_targets;
 566         int ret;
 567         ulong initrd_hi;
 568
 569 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 570         usb_ether_init();
 571 #endif
 572
 573         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 574                 debug("Saved variables - Skipping\n");
 575                 return 0;
 576         }
 577
 578         ret = set_fdtfile();
 579         if (ret)
 580                 return ret;
 581
 582         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 583         if (ret)
 584                 return -EINVAL;
 585
 586         if (reg >> BOOT_MODE_ALT_SHIFT)
 587                 reg >>= BOOT_MODE_ALT_SHIFT;
 588
 589         bootmode = reg & BOOT_MODES_MASK;
 590
 591         puts("Bootmode: ");
 592         switch (bootmode) {
 593         case USB_MODE:
 594                 puts("USB_MODE\n");
 595                 mode = "usb";
 596                 env_set("modeboot", "usb_dfu_spl");
 597                 break;
 598         case JTAG_MODE:
 599                 puts("JTAG_MODE\n");
 600                 mode = "jtag pxe dhcp";
 601                 env_set("modeboot", "jtagboot");
 602                 break;
 603         case QSPI_MODE_24BIT:
 604         case QSPI_MODE_32BIT:
 605                 mode = "qspi0";
 606                 puts("QSPI_MODE\n");
 607                 env_set("modeboot", "qspiboot");
 608                 break;
 609         case EMMC_MODE:
 610                 puts("EMMC_MODE\n");
 611                 if (uclass_get_device_by_name(UCLASS_MMC,
 612                                               "mmc@ff160000", &dev) &&
 613                     uclass_get_device_by_name(UCLASS_MMC,
 614                                               "sdhci@ff160000", &dev)) {
 615                         puts("Boot from EMMC but without SD0 enabled!\n");
 616                         return -1;
 617                 }
 618                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 619
 620                 mode = "mmc";
 621                 bootseq = dev->seq;
 622                 break;
 623         case SD_MODE:
 624                 puts("SD_MODE\n");
 625                 if (uclass_get_device_by_name(UCLASS_MMC,
 626                                               "mmc@ff160000", &dev) &&
 627                     uclass_get_device_by_name(UCLASS_MMC,
 628                                               "sdhci@ff160000", &dev)) {
 629                         puts("Boot from SD0 but without SD0 enabled!\n");
 630                         return -1;
 631                 }
 632                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 633
 634                 mode = "mmc";
 635                 bootseq = dev->seq;
 636                 env_set("modeboot", "sdboot");
 637                 break;
 638         case SD1_LSHFT_MODE:
 639                 puts("LVL_SHFT_");
 640                 /* fall through */
 641         case SD_MODE1:
 642                 puts("SD_MODE1\n");
 643                 if (uclass_get_device_by_name(UCLASS_MMC,
 644                                               "mmc@ff170000", &dev) &&
 645                     uclass_get_device_by_name(UCLASS_MMC,
 646                                               "sdhci@ff170000", &dev)) {
 647                         puts("Boot from SD1 but without SD1 enabled!\n");
 648                         return -1;
 649                 }
 650                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 651
 652                 mode = "mmc";
 653                 bootseq = dev->seq;
 654                 env_set("modeboot", "sdboot");
 655                 break;
 656         case NAND_MODE:
 657                 puts("NAND_MODE\n");
 658                 mode = "nand0";
 659                 env_set("modeboot", "nandboot");
 660                 break;
 661         default:
 662                 mode = "";
 663                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 664                 break;
 665         }
 666
 667         if (bootseq >= 0) {
 668                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 669                 debug("Bootseq len: %x\n", bootseq_len);
 670         }
 671
 672         /*
 673          * One terminating char + one byte for space between mode
 674          * and default boot_targets
 675          */
 676         env_targets = env_get("boot_targets");
 677         if (env_targets)
 678                 env_targets_len = strlen(env_targets);
 679
 680         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 681                              bootseq_len);
 682         if (!new_targets)
 683                 return -ENOMEM;
 684
 685         if (bootseq >= 0)
 686                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 687                         env_targets ? env_targets : "");
 688         else
 689                 sprintf(new_targets, "%s %s", mode,
 690                         env_targets ? env_targets : "");
 691
 692         env_set("boot_targets", new_targets);
 693
 694         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 695         initrd_hi = round_down(initrd_hi, SZ_16M);
 696         env_set_addr("initrd_high", (void *)initrd_hi);
 697
 698         env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
 699
 700         reset_reason();
 701
 702         return 0;
 703 }
 704 #endif
 705
 706 int checkboard(void)
 707 {
 708         puts("Board: Xilinx ZynqMP\n");
 709         return 0;
 710 }