board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <sata.h>
  16 #include <ahci.h>
  17 #include <scsi.h>
  18 #include <malloc.h>
  19 #include <wdt.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/psu_init_gpl.h>
  24 #include <asm/cache.h>
  25 #include <asm/io.h>
  26 #include <asm/ptrace.h>
  27 #include <dm/device.h>
  28 #include <dm/uclass.h>
  29 #include <usb.h>
  30 #include <dwc3-uboot.h>
  31 #include <zynqmppl.h>
  32 #include <zynqmp_firmware.h>
  33 #include <g_dnl.h>
  34 #include <linux/delay.h>
  35 #include <linux/sizes.h>
  36 #include "../common/board.h"
  37
  38 #include "pm_cfg_obj.h"
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  43     !defined(CONFIG_SPL_BUILD)
  44 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  45
  46 static const struct {
  47         u32 id;
  48         u32 ver;
  49         char *name;
  50         bool evexists;
  51 } zynqmp_devices[] = {
  52         {
  53                 .id = 0x10,
  54                 .name = "3eg",
  55         },
  56         {
  57                 .id = 0x10,
  58                 .ver = 0x2c,
  59                 .name = "3cg",
  60         },
  61         {
  62                 .id = 0x11,
  63                 .name = "2eg",
  64         },
  65         {
  66                 .id = 0x11,
  67                 .ver = 0x2c,
  68                 .name = "2cg",
  69         },
  70         {
  71                 .id = 0x20,
  72                 .name = "5ev",
  73                 .evexists = 1,
  74         },
  75         {
  76                 .id = 0x20,
  77                 .ver = 0x100,
  78                 .name = "5eg",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x20,
  83                 .ver = 0x12c,
  84                 .name = "5cg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .name = "4ev",
  90                 .evexists = 1,
  91         },
  92         {
  93                 .id = 0x21,
  94                 .ver = 0x100,
  95                 .name = "4eg",
  96                 .evexists = 1,
  97         },
  98         {
  99                 .id = 0x21,
 100                 .ver = 0x12c,
 101                 .name = "4cg",
 102                 .evexists = 1,
 103         },
 104         {
 105                 .id = 0x30,
 106                 .name = "7ev",
 107                 .evexists = 1,
 108         },
 109         {
 110                 .id = 0x30,
 111                 .ver = 0x100,
 112                 .name = "7eg",
 113                 .evexists = 1,
 114         },
 115         {
 116                 .id = 0x30,
 117                 .ver = 0x12c,
 118                 .name = "7cg",
 119                 .evexists = 1,
 120         },
 121         {
 122                 .id = 0x38,
 123                 .name = "9eg",
 124         },
 125         {
 126                 .id = 0x38,
 127                 .ver = 0x2c,
 128                 .name = "9cg",
 129         },
 130         {
 131                 .id = 0x39,
 132                 .name = "6eg",
 133         },
 134         {
 135                 .id = 0x39,
 136                 .ver = 0x2c,
 137                 .name = "6cg",
 138         },
 139         {
 140                 .id = 0x40,
 141                 .name = "11eg",
 142         },
 143         { /* For testing purpose only */
 144                 .id = 0x50,
 145                 .ver = 0x2c,
 146                 .name = "15cg",
 147         },
 148         {
 149                 .id = 0x50,
 150                 .name = "15eg",
 151         },
 152         {
 153                 .id = 0x58,
 154                 .name = "19eg",
 155         },
 156         {
 157                 .id = 0x59,
 158                 .name = "17eg",
 159         },
 160         {
 161                 .id = 0x61,
 162                 .name = "21dr",
 163         },
 164         {
 165                 .id = 0x63,
 166                 .name = "23dr",
 167         },
 168         {
 169                 .id = 0x65,
 170                 .name = "25dr",
 171         },
 172         {
 173                 .id = 0x64,
 174                 .name = "27dr",
 175         },
 176         {
 177                 .id = 0x60,
 178                 .name = "28dr",
 179         },
 180         {
 181                 .id = 0x62,
 182                 .name = "29dr",
 183         },
 184         {
 185                 .id = 0x66,
 186                 .name = "39dr",
 187         },
 188         {
 189                 .id = 0x7b,
 190                 .name = "48dr",
 191         },
 192         {
 193                 .id = 0x7e,
 194                 .name = "49dr",
 195         },
 196 };
 197 #endif
 198
 199 int chip_id(unsigned char id)
 200 {
 201         struct pt_regs regs;
 202         int val = -EINVAL;
 203
 204         if (current_el() != 3) {
 205                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 206                 regs.regs[1] = 0;
 207                 regs.regs[2] = 0;
 208                 regs.regs[3] = 0;
 209
 210                 smc_call(&regs);
 211
 212                 /*
 213                  * SMC returns:
 214                  * regs[0][31:0]  = status of the operation
 215                  * regs[0][63:32] = CSU.IDCODE register
 216                  * regs[1][31:0]  = CSU.version register
 217                  * regs[1][63:32] = CSU.IDCODE2 register
 218                  */
 219                 switch (id) {
 220                 case IDCODE:
 221                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 222                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 223                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 224                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 225                         val = regs.regs[0];
 226                         break;
 227                 case VERSION:
 228                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 229                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 230                         val = regs.regs[1];
 231                         break;
 232                 case IDCODE2:
 233                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 234                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 235                         val = regs.regs[1];
 236                         break;
 237                 default:
 238                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 239                 }
 240         } else {
 241                 switch (id) {
 242                 case IDCODE:
 243                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 244                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 245                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 246                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 247                         break;
 248                 case VERSION:
 249                         val = readl(ZYNQMP_CSU_VER_ADDR);
 250                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 251                         break;
 252                 default:
 253                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 254                 }
 255         }
 256
 257         return val;
 258 }
 259
 260 #define ZYNQMP_VERSION_SIZE             9
 261 #define ZYNQMP_PL_STATUS_BIT            9
 262 #define ZYNQMP_IPDIS_VCU_BIT            8
 263 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 264 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 265 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 266                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 267 #define MAX_VARIANTS_EV                 3
 268
 269 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 270         !defined(CONFIG_SPL_BUILD)
 271 static char *zynqmp_get_silicon_idcode_name(void)
 272 {
 273         u32 i, id, ver, j;
 274         char *buf;
 275         static char name[ZYNQMP_VERSION_SIZE];
 276
 277         id = chip_id(IDCODE);
 278         ver = chip_id(IDCODE2);
 279
 280         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 281                 if (zynqmp_devices[i].id == id) {
 282                         if (zynqmp_devices[i].evexists &&
 283                             !(ver & ZYNQMP_PL_STATUS_MASK))
 284                                 break;
 285                         if (zynqmp_devices[i].ver == (ver &
 286                             ZYNQMP_CSU_VERSION_MASK))
 287                                 break;
 288                 }
 289         }
 290
 291         if (i >= ARRAY_SIZE(zynqmp_devices))
 292                 return "unknown";
 293
 294         strncat(name, "zu", 2);
 295         if (!zynqmp_devices[i].evexists ||
 296             (ver & ZYNQMP_PL_STATUS_MASK)) {
 297                 strncat(name, zynqmp_devices[i].name,
 298                         ZYNQMP_VERSION_SIZE - 3);
 299                 return name;
 300         }
 301
 302         /*
 303          * Here we are means, PL not powered up and ev variant
 304          * exists. So, we need to ignore VCU disable bit(8) in
 305          * version and findout if its CG or EG/EV variant.
 306          */
 307         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 308                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 309                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 310                         strncat(name, zynqmp_devices[i].name,
 311                                 ZYNQMP_VERSION_SIZE - 3);
 312                         break;
 313                 }
 314         }
 315
 316         if (j >= MAX_VARIANTS_EV)
 317                 return "unknown";
 318
 319         if (strstr(name, "eg") || strstr(name, "ev")) {
 320                 buf = strstr(name, "e");
 321                 *buf = '\0';
 322         }
 323
 324         return name;
 325 }
 326 #endif
 327
 328 int board_early_init_f(void)
 329 {
 330 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 331         int ret;
 332
 333         ret = psu_init();
 334         if (ret)
 335                 return ret;
 336
 337         /* Delay is required for clocks to be propagated */
 338         udelay(1000000);
 339 #endif
 340
 341 #ifdef CONFIG_DEBUG_UART
 342         /* Uart debug for sure */
 343         debug_uart_init();
 344         puts("Debug uart enabled\n"); /* or printch() */
 345 #endif
 346
 347         return 0;
 348 }
 349
 350 static int multi_boot(void)
 351 {
 352         u32 multiboot;
 353
 354         multiboot = readl(&csu_base->multi_boot);
 355
 356         printf("Multiboot:\t%x\n", multiboot);
 357
 358         return 0;
 359 }
 360
 361 int board_init(void)
 362 {
 363 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 364         struct udevice *dev;
 365
 366         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 367         if (!dev)
 368                 panic("PMU Firmware device not found - Enable it");
 369 #endif
 370
 371 #if defined(CONFIG_SPL_BUILD)
 372         /* Check *at build time* if the filename is an non-empty string */
 373         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 374                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 375                                                 zynqmp_pm_cfg_obj_size);
 376 #endif
 377
 378         printf("EL Level:\tEL%d\n", current_el());
 379
 380 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 381     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 382     defined(CONFIG_SPL_BUILD))
 383         if (current_el() != 3) {
 384                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 385                 printf("Chip ID:\t%s\n", zynqmppl.name);
 386                 fpga_init();
 387                 fpga_add(fpga_xilinx, &zynqmppl);
 388         }
 389 #endif
 390
 391         if (current_el() == 3)
 392                 multi_boot();
 393
 394         return 0;
 395 }
 396
 397 int board_early_init_r(void)
 398 {
 399         u32 val;
 400
 401         if (current_el() != 3)
 402                 return 0;
 403
 404         val = readl(&crlapb_base->timestamp_ref_ctrl);
 405         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 406
 407         if (!val) {
 408                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 409                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 410                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 411
 412                 /* Program freq register in System counter */
 413                 writel(zynqmp_get_system_timer_freq(),
 414                        &iou_scntr_secure->base_frequency_id_register);
 415                 /* And enable system counter */
 416                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 417                        &iou_scntr_secure->counter_control_register);
 418         }
 419         return 0;
 420 }
 421
 422 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 423                          char *const argv[])
 424 {
 425         int ret = 0;
 426
 427         if (current_el() > 1) {
 428                 smp_kick_all_cpus();
 429                 dcache_disable();
 430                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 431                                     ES_TO_AARCH64);
 432         } else {
 433                 printf("FAIL: current EL is not above EL1\n");
 434                 ret = EINVAL;
 435         }
 436         return ret;
 437 }
 438
 439 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 440 int dram_init_banksize(void)
 441 {
 442         int ret;
 443
 444         ret = fdtdec_setup_memory_banksize();
 445         if (ret)
 446                 return ret;
 447
 448         mem_map_fill();
 449
 450         return 0;
 451 }
 452
 453 int dram_init(void)
 454 {
 455         if (fdtdec_setup_mem_size_base() != 0)
 456                 return -EINVAL;
 457
 458         return 0;
 459 }
 460 #else
 461 int dram_init_banksize(void)
 462 {
 463 #if defined(CONFIG_NR_DRAM_BANKS)
 464         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 465         gd->bd->bi_dram[0].size = get_effective_memsize();
 466 #endif
 467
 468         mem_map_fill();
 469
 470         return 0;
 471 }
 472
 473 int dram_init(void)
 474 {
 475         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 476                                     CONFIG_SYS_SDRAM_SIZE);
 477
 478         return 0;
 479 }
 480 #endif
 481
 482 void reset_cpu(ulong addr)
 483 {
 484 }
 485
 486 #if defined(CONFIG_BOARD_LATE_INIT)
 487 static const struct {
 488         u32 bit;
 489         const char *name;
 490 } reset_reasons[] = {
 491         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 492         { RESET_REASON_SOFT, "SOFT" },
 493         { RESET_REASON_SRST, "SRST" },
 494         { RESET_REASON_PSONLY, "PS-ONLY" },
 495         { RESET_REASON_PMU, "PMU" },
 496         { RESET_REASON_INTERNAL, "INTERNAL" },
 497         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 498         {}
 499 };
 500
 501 static int reset_reason(void)
 502 {
 503         u32 reg;
 504         int i, ret;
 505         const char *reason = NULL;
 506
 507         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 508         if (ret)
 509                 return -EINVAL;
 510
 511         puts("Reset reason:\t");
 512
 513         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 514                 if (reg & reset_reasons[i].bit) {
 515                         reason = reset_reasons[i].name;
 516                         printf("%s ", reset_reasons[i].name);
 517                         break;
 518                 }
 519         }
 520
 521         puts("\n");
 522
 523         env_set("reset_reason", reason);
 524
 525         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 526         if (ret)
 527                 return -EINVAL;
 528
 529         return ret;
 530 }
 531
 532 static int set_fdtfile(void)
 533 {
 534         char *compatible, *fdtfile;
 535         const char *suffix = ".dtb";
 536         const char *vendor = "xilinx/";
 537
 538         if (env_get("fdtfile"))
 539                 return 0;
 540
 541         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 542         if (compatible) {
 543                 debug("Compatible: %s\n", compatible);
 544
 545                 /* Discard vendor prefix */
 546                 strsep(&compatible, ",");
 547
 548                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 549                                  strlen(suffix) + 1);
 550                 if (!fdtfile)
 551                         return -ENOMEM;
 552
 553                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 554
 555                 env_set("fdtfile", fdtfile);
 556                 free(fdtfile);
 557         }
 558
 559         return 0;
 560 }
 561
 562 static u8 zynqmp_get_bootmode(void)
 563 {
 564         u8 bootmode;
 565         u32 reg = 0;
 566         int ret;
 567
 568         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 569         if (ret)
 570                 return -EINVAL;
 571
 572         if (reg >> BOOT_MODE_ALT_SHIFT)
 573                 reg >>= BOOT_MODE_ALT_SHIFT;
 574
 575         bootmode = reg & BOOT_MODES_MASK;
 576
 577         return bootmode;
 578 }
 579
 580 int board_late_init(void)
 581 {
 582         u8 bootmode;
 583         struct udevice *dev;
 584         int bootseq = -1;
 585         int bootseq_len = 0;
 586         int env_targets_len = 0;
 587         const char *mode;
 588         char *new_targets;
 589         char *env_targets;
 590         int ret;
 591
 592 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 593         usb_ether_init();
 594 #endif
 595
 596         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 597                 debug("Saved variables - Skipping\n");
 598                 return 0;
 599         }
 600
 601         ret = set_fdtfile();
 602         if (ret)
 603                 return ret;
 604
 605         bootmode = zynqmp_get_bootmode();
 606
 607         puts("Bootmode: ");
 608         switch (bootmode) {
 609         case USB_MODE:
 610                 puts("USB_MODE\n");
 611                 mode = "usb";
 612                 env_set("modeboot", "usb_dfu_spl");
 613                 break;
 614         case JTAG_MODE:
 615                 puts("JTAG_MODE\n");
 616                 mode = "jtag pxe dhcp";
 617                 env_set("modeboot", "jtagboot");
 618                 break;
 619         case QSPI_MODE_24BIT:
 620         case QSPI_MODE_32BIT:
 621                 mode = "qspi0";
 622                 puts("QSPI_MODE\n");
 623                 env_set("modeboot", "qspiboot");
 624                 break;
 625         case EMMC_MODE:
 626                 puts("EMMC_MODE\n");
 627                 if (uclass_get_device_by_name(UCLASS_MMC,
 628                                               "mmc@ff160000", &dev) &&
 629                     uclass_get_device_by_name(UCLASS_MMC,
 630                                               "sdhci@ff160000", &dev)) {
 631                         puts("Boot from EMMC but without SD0 enabled!\n");
 632                         return -1;
 633                 }
 634                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 635
 636                 mode = "mmc";
 637                 bootseq = dev->seq;
 638                 break;
 639         case SD_MODE:
 640                 puts("SD_MODE\n");
 641                 if (uclass_get_device_by_name(UCLASS_MMC,
 642                                               "mmc@ff160000", &dev) &&
 643                     uclass_get_device_by_name(UCLASS_MMC,
 644                                               "sdhci@ff160000", &dev)) {
 645                         puts("Boot from SD0 but without SD0 enabled!\n");
 646                         return -1;
 647                 }
 648                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 649
 650                 mode = "mmc";
 651                 bootseq = dev->seq;
 652                 env_set("modeboot", "sdboot");
 653                 break;
 654         case SD1_LSHFT_MODE:
 655                 puts("LVL_SHFT_");
 656                 /* fall through */
 657         case SD_MODE1:
 658                 puts("SD_MODE1\n");
 659                 if (uclass_get_device_by_name(UCLASS_MMC,
 660                                               "mmc@ff170000", &dev) &&
 661                     uclass_get_device_by_name(UCLASS_MMC,
 662                                               "sdhci@ff170000", &dev)) {
 663                         puts("Boot from SD1 but without SD1 enabled!\n");
 664                         return -1;
 665                 }
 666                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 667
 668                 mode = "mmc";
 669                 bootseq = dev->seq;
 670                 env_set("modeboot", "sdboot");
 671                 break;
 672         case NAND_MODE:
 673                 puts("NAND_MODE\n");
 674                 mode = "nand0";
 675                 env_set("modeboot", "nandboot");
 676                 break;
 677         default:
 678                 mode = "";
 679                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 680                 break;
 681         }
 682
 683         if (bootseq >= 0) {
 684                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 685                 debug("Bootseq len: %x\n", bootseq_len);
 686         }
 687
 688         /*
 689          * One terminating char + one byte for space between mode
 690          * and default boot_targets
 691          */
 692         env_targets = env_get("boot_targets");
 693         if (env_targets)
 694                 env_targets_len = strlen(env_targets);
 695
 696         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 697                              bootseq_len);
 698         if (!new_targets)
 699                 return -ENOMEM;
 700
 701         if (bootseq >= 0)
 702                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 703                         env_targets ? env_targets : "");
 704         else
 705                 sprintf(new_targets, "%s %s", mode,
 706                         env_targets ? env_targets : "");
 707
 708         env_set("boot_targets", new_targets);
 709
 710         reset_reason();
 711
 712         return board_late_init_xilinx();
 713 }
 714 #endif
 715
 716 int checkboard(void)
 717 {
 718         puts("Board: Xilinx ZynqMP\n");
 719         return 0;
 720 }