board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <sata.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <malloc.h>
  12 #include <wdt.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <usb.h>
  21 #include <dwc3-uboot.h>
  22 #include <zynqmppl.h>
  23 #include <g_dnl.h>
  24
  25 #include "pm_cfg_obj.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  30     !defined(CONFIG_SPL_BUILD)
  31 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  32
  33 static const struct {
  34         u32 id;
  35         u32 ver;
  36         char *name;
  37         bool evexists;
  38 } zynqmp_devices[] = {
  39         {
  40                 .id = 0x10,
  41                 .name = "3eg",
  42         },
  43         {
  44                 .id = 0x10,
  45                 .ver = 0x2c,
  46                 .name = "3cg",
  47         },
  48         {
  49                 .id = 0x11,
  50                 .name = "2eg",
  51         },
  52         {
  53                 .id = 0x11,
  54                 .ver = 0x2c,
  55                 .name = "2cg",
  56         },
  57         {
  58                 .id = 0x20,
  59                 .name = "5ev",
  60                 .evexists = 1,
  61         },
  62         {
  63                 .id = 0x20,
  64                 .ver = 0x100,
  65                 .name = "5eg",
  66                 .evexists = 1,
  67         },
  68         {
  69                 .id = 0x20,
  70                 .ver = 0x12c,
  71                 .name = "5cg",
  72                 .evexists = 1,
  73         },
  74         {
  75                 .id = 0x21,
  76                 .name = "4ev",
  77                 .evexists = 1,
  78         },
  79         {
  80                 .id = 0x21,
  81                 .ver = 0x100,
  82                 .name = "4eg",
  83                 .evexists = 1,
  84         },
  85         {
  86                 .id = 0x21,
  87                 .ver = 0x12c,
  88                 .name = "4cg",
  89                 .evexists = 1,
  90         },
  91         {
  92                 .id = 0x30,
  93                 .name = "7ev",
  94                 .evexists = 1,
  95         },
  96         {
  97                 .id = 0x30,
  98                 .ver = 0x100,
  99                 .name = "7eg",
 100                 .evexists = 1,
 101         },
 102         {
 103                 .id = 0x30,
 104                 .ver = 0x12c,
 105                 .name = "7cg",
 106                 .evexists = 1,
 107         },
 108         {
 109                 .id = 0x38,
 110                 .name = "9eg",
 111         },
 112         {
 113                 .id = 0x38,
 114                 .ver = 0x2c,
 115                 .name = "9cg",
 116         },
 117         {
 118                 .id = 0x39,
 119                 .name = "6eg",
 120         },
 121         {
 122                 .id = 0x39,
 123                 .ver = 0x2c,
 124                 .name = "6cg",
 125         },
 126         {
 127                 .id = 0x40,
 128                 .name = "11eg",
 129         },
 130         { /* For testing purpose only */
 131                 .id = 0x50,
 132                 .ver = 0x2c,
 133                 .name = "15cg",
 134         },
 135         {
 136                 .id = 0x50,
 137                 .name = "15eg",
 138         },
 139         {
 140                 .id = 0x58,
 141                 .name = "19eg",
 142         },
 143         {
 144                 .id = 0x59,
 145                 .name = "17eg",
 146         },
 147         {
 148                 .id = 0x61,
 149                 .name = "21dr",
 150         },
 151         {
 152                 .id = 0x63,
 153                 .name = "23dr",
 154         },
 155         {
 156                 .id = 0x65,
 157                 .name = "25dr",
 158         },
 159         {
 160                 .id = 0x64,
 161                 .name = "27dr",
 162         },
 163         {
 164                 .id = 0x60,
 165                 .name = "28dr",
 166         },
 167         {
 168                 .id = 0x62,
 169                 .name = "29dr",
 170         },
 171         {
 172                 .id = 0x66,
 173                 .name = "39dr",
 174         },
 175 };
 176 #endif
 177
 178 int chip_id(unsigned char id)
 179 {
 180         struct pt_regs regs;
 181         int val = -EINVAL;
 182
 183         if (current_el() != 3) {
 184                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 185                 regs.regs[1] = 0;
 186                 regs.regs[2] = 0;
 187                 regs.regs[3] = 0;
 188
 189                 smc_call(&regs);
 190
 191                 /*
 192                  * SMC returns:
 193                  * regs[0][31:0]  = status of the operation
 194                  * regs[0][63:32] = CSU.IDCODE register
 195                  * regs[1][31:0]  = CSU.version register
 196                  * regs[1][63:32] = CSU.IDCODE2 register
 197                  */
 198                 switch (id) {
 199                 case IDCODE:
 200                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 201                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 202                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 203                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 204                         val = regs.regs[0];
 205                         break;
 206                 case VERSION:
 207                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 208                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 209                         val = regs.regs[1];
 210                         break;
 211                 case IDCODE2:
 212                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 213                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 214                         val = regs.regs[1];
 215                         break;
 216                 default:
 217                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 218                 }
 219         } else {
 220                 switch (id) {
 221                 case IDCODE:
 222                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 223                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 224                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 225                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 226                         break;
 227                 case VERSION:
 228                         val = readl(ZYNQMP_CSU_VER_ADDR);
 229                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 230                         break;
 231                 default:
 232                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 233                 }
 234         }
 235
 236         return val;
 237 }
 238
 239 #define ZYNQMP_VERSION_SIZE             9
 240 #define ZYNQMP_PL_STATUS_BIT            9
 241 #define ZYNQMP_IPDIS_VCU_BIT            8
 242 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 243 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 244 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 245                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 246 #define MAX_VARIANTS_EV                 3
 247
 248 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 249         !defined(CONFIG_SPL_BUILD)
 250 static char *zynqmp_get_silicon_idcode_name(void)
 251 {
 252         u32 i, id, ver, j;
 253         char *buf;
 254         static char name[ZYNQMP_VERSION_SIZE];
 255
 256         id = chip_id(IDCODE);
 257         ver = chip_id(IDCODE2);
 258
 259         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 260                 if (zynqmp_devices[i].id == id) {
 261                         if (zynqmp_devices[i].evexists &&
 262                             !(ver & ZYNQMP_PL_STATUS_MASK))
 263                                 break;
 264                         if (zynqmp_devices[i].ver == (ver &
 265                             ZYNQMP_CSU_VERSION_MASK))
 266                                 break;
 267                 }
 268         }
 269
 270         if (i >= ARRAY_SIZE(zynqmp_devices))
 271                 return "unknown";
 272
 273         strncat(name, "zu", 2);
 274         if (!zynqmp_devices[i].evexists ||
 275             (ver & ZYNQMP_PL_STATUS_MASK)) {
 276                 strncat(name, zynqmp_devices[i].name,
 277                         ZYNQMP_VERSION_SIZE - 3);
 278                 return name;
 279         }
 280
 281         /*
 282          * Here we are means, PL not powered up and ev variant
 283          * exists. So, we need to ignore VCU disable bit(8) in
 284          * version and findout if its CG or EG/EV variant.
 285          */
 286         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 287                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 288                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 289                         strncat(name, zynqmp_devices[i].name,
 290                                 ZYNQMP_VERSION_SIZE - 3);
 291                         break;
 292                 }
 293         }
 294
 295         if (j >= MAX_VARIANTS_EV)
 296                 return "unknown";
 297
 298         if (strstr(name, "eg") || strstr(name, "ev")) {
 299                 buf = strstr(name, "e");
 300                 *buf = '\0';
 301         }
 302
 303         return name;
 304 }
 305 #endif
 306
 307 int board_early_init_f(void)
 308 {
 309         int ret = 0;
 310 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 311         u32 pm_api_version;
 312
 313         pm_api_version = zynqmp_pmufw_version();
 314         printf("PMUFW:\tv%d.%d\n",
 315                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 316                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 317
 318         if (pm_api_version < ZYNQMP_PM_VERSION)
 319                 panic("PMUFW version error. Expected: v%d.%d\n",
 320                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 321 #endif
 322
 323 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 324         ret = psu_init();
 325 #endif
 326
 327         return ret;
 328 }
 329
 330 int board_init(void)
 331 {
 332 #if defined(CONFIG_SPL_BUILD)
 333         /* Check *at build time* if the filename is an non-empty string */
 334         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 335                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 336                                                 zynqmp_pm_cfg_obj_size);
 337 #endif
 338
 339         printf("EL Level:\tEL%d\n", current_el());
 340
 341 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 342     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 343     defined(CONFIG_SPL_BUILD))
 344         if (current_el() != 3) {
 345                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 346                 printf("Chip ID:\t%s\n", zynqmppl.name);
 347                 fpga_init();
 348                 fpga_add(fpga_xilinx, &zynqmppl);
 349         }
 350 #endif
 351
 352         return 0;
 353 }
 354
 355 int board_early_init_r(void)
 356 {
 357         u32 val;
 358
 359         if (current_el() != 3)
 360                 return 0;
 361
 362         val = readl(&crlapb_base->timestamp_ref_ctrl);
 363         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 364
 365         if (!val) {
 366                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 367                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 368                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 369
 370                 /* Program freq register in System counter */
 371                 writel(zynqmp_get_system_timer_freq(),
 372                        &iou_scntr_secure->base_frequency_id_register);
 373                 /* And enable system counter */
 374                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 375                        &iou_scntr_secure->counter_control_register);
 376         }
 377         return 0;
 378 }
 379
 380 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 381                          char * const argv[])
 382 {
 383         int ret = 0;
 384
 385         if (current_el() > 1) {
 386                 smp_kick_all_cpus();
 387                 dcache_disable();
 388                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 389                                     ES_TO_AARCH64);
 390         } else {
 391                 printf("FAIL: current EL is not above EL1\n");
 392                 ret = EINVAL;
 393         }
 394         return ret;
 395 }
 396
 397 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 398 int dram_init_banksize(void)
 399 {
 400         int ret;
 401
 402         ret = fdtdec_setup_memory_banksize();
 403         if (ret)
 404                 return ret;
 405
 406         mem_map_fill();
 407
 408         return 0;
 409 }
 410
 411 int dram_init(void)
 412 {
 413         if (fdtdec_setup_mem_size_base() != 0)
 414                 return -EINVAL;
 415
 416         return 0;
 417 }
 418 #else
 419 int dram_init_banksize(void)
 420 {
 421 #if defined(CONFIG_NR_DRAM_BANKS)
 422         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 423         gd->bd->bi_dram[0].size = get_effective_memsize();
 424 #endif
 425
 426         mem_map_fill();
 427
 428         return 0;
 429 }
 430
 431 int dram_init(void)
 432 {
 433         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 434                                     CONFIG_SYS_SDRAM_SIZE);
 435
 436         return 0;
 437 }
 438 #endif
 439
 440 void reset_cpu(ulong addr)
 441 {
 442 }
 443
 444 #if defined(CONFIG_BOARD_LATE_INIT)
 445 static const struct {
 446         u32 bit;
 447         const char *name;
 448 } reset_reasons[] = {
 449         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 450         { RESET_REASON_SOFT, "SOFT" },
 451         { RESET_REASON_SRST, "SRST" },
 452         { RESET_REASON_PSONLY, "PS-ONLY" },
 453         { RESET_REASON_PMU, "PMU" },
 454         { RESET_REASON_INTERNAL, "INTERNAL" },
 455         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 456         {}
 457 };
 458
 459 static int reset_reason(void)
 460 {
 461         u32 reg;
 462         int i, ret;
 463         const char *reason = NULL;
 464
 465         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 466         if (ret)
 467                 return -EINVAL;
 468
 469         puts("Reset reason:\t");
 470
 471         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 472                 if (reg & reset_reasons[i].bit) {
 473                         reason = reset_reasons[i].name;
 474                         printf("%s ", reset_reasons[i].name);
 475                         break;
 476                 }
 477         }
 478
 479         puts("\n");
 480
 481         env_set("reset_reason", reason);
 482
 483         ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
 484         if (ret)
 485                 return -EINVAL;
 486
 487         return ret;
 488 }
 489
 490 static int set_fdtfile(void)
 491 {
 492         char *compatible, *fdtfile;
 493         const char *suffix = ".dtb";
 494         const char *vendor = "xilinx/";
 495
 496         if (env_get("fdtfile"))
 497                 return 0;
 498
 499         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 500         if (compatible) {
 501                 debug("Compatible: %s\n", compatible);
 502
 503                 /* Discard vendor prefix */
 504                 strsep(&compatible, ",");
 505
 506                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 507                                  strlen(suffix) + 1);
 508                 if (!fdtfile)
 509                         return -ENOMEM;
 510
 511                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 512
 513                 env_set("fdtfile", fdtfile);
 514                 free(fdtfile);
 515         }
 516
 517         return 0;
 518 }
 519
 520 int board_late_init(void)
 521 {
 522         u32 reg = 0;
 523         u8 bootmode;
 524         struct udevice *dev;
 525         int bootseq = -1;
 526         int bootseq_len = 0;
 527         int env_targets_len = 0;
 528         const char *mode;
 529         char *new_targets;
 530         char *env_targets;
 531         int ret;
 532
 533 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 534         usb_ether_init();
 535 #endif
 536
 537         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 538                 debug("Saved variables - Skipping\n");
 539                 return 0;
 540         }
 541
 542         ret = set_fdtfile();
 543         if (ret)
 544                 return ret;
 545
 546         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 547         if (ret)
 548                 return -EINVAL;
 549
 550         if (reg >> BOOT_MODE_ALT_SHIFT)
 551                 reg >>= BOOT_MODE_ALT_SHIFT;
 552
 553         bootmode = reg & BOOT_MODES_MASK;
 554
 555         puts("Bootmode: ");
 556         switch (bootmode) {
 557         case USB_MODE:
 558                 puts("USB_MODE\n");
 559                 mode = "usb";
 560                 env_set("modeboot", "usb_dfu_spl");
 561                 break;
 562         case JTAG_MODE:
 563                 puts("JTAG_MODE\n");
 564                 mode = "pxe dhcp";
 565                 env_set("modeboot", "jtagboot");
 566                 break;
 567         case QSPI_MODE_24BIT:
 568         case QSPI_MODE_32BIT:
 569                 mode = "qspi0";
 570                 puts("QSPI_MODE\n");
 571                 env_set("modeboot", "qspiboot");
 572                 break;
 573         case EMMC_MODE:
 574                 puts("EMMC_MODE\n");
 575                 mode = "mmc0";
 576                 env_set("modeboot", "emmcboot");
 577                 break;
 578         case SD_MODE:
 579                 puts("SD_MODE\n");
 580                 if (uclass_get_device_by_name(UCLASS_MMC,
 581                                               "mmc@ff160000", &dev) &&
 582                     uclass_get_device_by_name(UCLASS_MMC,
 583                                               "sdhci@ff160000", &dev)) {
 584                         puts("Boot from SD0 but without SD0 enabled!\n");
 585                         return -1;
 586                 }
 587                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 588
 589                 mode = "mmc";
 590                 bootseq = dev->seq;
 591                 env_set("modeboot", "sdboot");
 592                 break;
 593         case SD1_LSHFT_MODE:
 594                 puts("LVL_SHFT_");
 595                 /* fall through */
 596         case SD_MODE1:
 597                 puts("SD_MODE1\n");
 598                 if (uclass_get_device_by_name(UCLASS_MMC,
 599                                               "mmc@ff170000", &dev) &&
 600                     uclass_get_device_by_name(UCLASS_MMC,
 601                                               "sdhci@ff170000", &dev)) {
 602                         puts("Boot from SD1 but without SD1 enabled!\n");
 603                         return -1;
 604                 }
 605                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 606
 607                 mode = "mmc";
 608                 bootseq = dev->seq;
 609                 env_set("modeboot", "sdboot");
 610                 break;
 611         case NAND_MODE:
 612                 puts("NAND_MODE\n");
 613                 mode = "nand0";
 614                 env_set("modeboot", "nandboot");
 615                 break;
 616         default:
 617                 mode = "";
 618                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 619                 break;
 620         }
 621
 622         if (bootseq >= 0) {
 623                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 624                 debug("Bootseq len: %x\n", bootseq_len);
 625         }
 626
 627         /*
 628          * One terminating char + one byte for space between mode
 629          * and default boot_targets
 630          */
 631         env_targets = env_get("boot_targets");
 632         if (env_targets)
 633                 env_targets_len = strlen(env_targets);
 634
 635         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 636                              bootseq_len);
 637         if (!new_targets)
 638                 return -ENOMEM;
 639
 640         if (bootseq >= 0)
 641                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 642                         env_targets ? env_targets : "");
 643         else
 644                 sprintf(new_targets, "%s %s", mode,
 645                         env_targets ? env_targets : "");
 646
 647         env_set("boot_targets", new_targets);
 648
 649         reset_reason();
 650
 651         return 0;
 652 }
 653 #endif
 654
 655 int checkboard(void)
 656 {
 657         puts("Board: Xilinx ZynqMP\n");
 658         return 0;
 659 }