board/xilinx/versal/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <fdtdec.h>
  10 #include <init.h>
  11 #include <malloc.h>
  12 #include <time.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <dm/device.h>
  17 #include <dm/uclass.h>
  18 #include <versalpl.h>
  19 #include <linux/sizes.h>
  20 #include "../common/board.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_FPGA_VERSALPL)
  25 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  26 #endif
  27
  28 int board_init(void)
  29 {
  30         printf("EL Level:\tEL%d\n", current_el());
  31
  32 #if defined(CONFIG_FPGA_VERSALPL)
  33         fpga_init();
  34         fpga_add(fpga_xilinx, &versalpl);
  35 #endif
  36
  37         return 0;
  38 }
  39
  40 int board_early_init_r(void)
  41 {
  42         u32 val;
  43
  44         if (current_el() != 3)
  45                 return 0;
  46
  47         debug("iou_switch ctrl div0 %x\n",
  48               readl(&crlapb_base->iou_switch_ctrl));
  49
  50         writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  51                (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  52                &crlapb_base->iou_switch_ctrl);
  53
  54         /* Global timer init - Program time stamp reference clk */
  55         val = readl(&crlapb_base->timestamp_ref_ctrl);
  56         val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  57         writel(val, &crlapb_base->timestamp_ref_ctrl);
  58
  59         debug("ref ctrl 0x%x\n",
  60               readl(&crlapb_base->timestamp_ref_ctrl));
  61
  62         /* Clear reset of timestamp reg */
  63         writel(0, &crlapb_base->rst_timestamp);
  64
  65         /*
  66          * Program freq register in System counter and
  67          * enable system counter.
  68          */
  69         writel(COUNTER_FREQUENCY,
  70                &iou_scntr_secure->base_frequency_id_register);
  71
  72         debug("counter val 0x%x\n",
  73               readl(&iou_scntr_secure->base_frequency_id_register));
  74
  75         writel(IOU_SCNTRS_CONTROL_EN,
  76                &iou_scntr_secure->counter_control_register);
  77
  78         debug("scntrs control 0x%x\n",
  79               readl(&iou_scntr_secure->counter_control_register));
  80         debug("timer 0x%llx\n", get_ticks());
  81         debug("timer 0x%llx\n", get_ticks());
  82
  83         return 0;
  84 }
  85
  86 int board_late_init(void)
  87 {
  88         u32 reg = 0;
  89         u8 bootmode;
  90         struct udevice *dev;
  91         int bootseq = -1;
  92         int bootseq_len = 0;
  93         int env_targets_len = 0;
  94         const char *mode;
  95         char *new_targets;
  96         char *env_targets;
  97         ulong initrd_hi;
  98
  99         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 100                 debug("Saved variables - Skipping\n");
 101                 return 0;
 102         }
 103
 104         reg = readl(&crp_base->boot_mode_usr);
 105
 106         if (reg >> BOOT_MODE_ALT_SHIFT)
 107                 reg >>= BOOT_MODE_ALT_SHIFT;
 108
 109         bootmode = reg & BOOT_MODES_MASK;
 110
 111         puts("Bootmode: ");
 112         switch (bootmode) {
 113         case USB_MODE:
 114                 puts("USB_MODE\n");
 115                 mode = "dfu_usb";
 116                 break;
 117         case JTAG_MODE:
 118                 puts("JTAG_MODE\n");
 119                 mode = "jtag pxe dhcp";
 120                 break;
 121         case QSPI_MODE_24BIT:
 122                 puts("QSPI_MODE_24\n");
 123                 mode = "xspi0";
 124                 break;
 125         case QSPI_MODE_32BIT:
 126                 puts("QSPI_MODE_32\n");
 127                 mode = "xspi0";
 128                 break;
 129         case OSPI_MODE:
 130                 puts("OSPI_MODE\n");
 131                 mode = "xspi0";
 132                 break;
 133         case EMMC_MODE:
 134                 puts("EMMC_MODE\n");
 135                 if (uclass_get_device_by_name(UCLASS_MMC,
 136                                               "sdhci@f1050000", &dev)) {
 137                         puts("Boot from EMMC but without SD1 enabled!\n");
 138                         return -1;
 139                 }
 140                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 141                 mode = "mmc";
 142                 bootseq = dev->seq;
 143                 break;
 144         case SD_MODE:
 145                 puts("SD_MODE\n");
 146                 if (uclass_get_device_by_name(UCLASS_MMC,
 147                                               "sdhci@f1040000", &dev)) {
 148                         puts("Boot from SD0 but without SD0 enabled!\n");
 149                         return -1;
 150                 }
 151                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 152
 153                 mode = "mmc";
 154                 bootseq = dev->seq;
 155                 break;
 156         case SD1_LSHFT_MODE:
 157                 puts("LVL_SHFT_");
 158                 /* fall through */
 159         case SD_MODE1:
 160                 puts("SD_MODE1\n");
 161                 if (uclass_get_device_by_name(UCLASS_MMC,
 162                                               "sdhci@f1050000", &dev)) {
 163                         puts("Boot from SD1 but without SD1 enabled!\n");
 164                         return -1;
 165                 }
 166                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 167
 168                 mode = "mmc";
 169                 bootseq = dev->seq;
 170                 break;
 171         default:
 172                 mode = "";
 173                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 174                 break;
 175         }
 176
 177         if (bootseq >= 0) {
 178                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 179                 debug("Bootseq len: %x\n", bootseq_len);
 180         }
 181
 182         /*
 183          * One terminating char + one byte for space between mode
 184          * and default boot_targets
 185          */
 186         env_targets = env_get("boot_targets");
 187         if (env_targets)
 188                 env_targets_len = strlen(env_targets);
 189
 190         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 191                              bootseq_len);
 192         if (!new_targets)
 193                 return -ENOMEM;
 194
 195         if (bootseq >= 0)
 196                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 197                         env_targets ? env_targets : "");
 198         else
 199                 sprintf(new_targets, "%s %s", mode,
 200                         env_targets ? env_targets : "");
 201
 202         env_set("boot_targets", new_targets);
 203
 204         initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
 205         initrd_hi = round_down(initrd_hi, SZ_16M);
 206         env_set_addr("initrd_high", (void *)initrd_hi);
 207
 208         return board_late_init_xilinx();
 209 }
 210
 211 int dram_init_banksize(void)
 212 {
 213         int ret;
 214
 215         ret = fdtdec_setup_memory_banksize();
 216         if (ret)
 217                 return ret;
 218
 219         mem_map_fill();
 220
 221         return 0;
 222 }
 223
 224 int dram_init(void)
 225 {
 226         if (fdtdec_setup_mem_size_base() != 0)
 227                 return -EINVAL;
 228
 229         return 0;
 230 }
 231
 232 void reset_cpu(ulong addr)
 233 {
 234 }