board/wandboard/wandboard.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2014 O.S. Systems Software LTDA.
   5  *
   6  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   7  */
   8
   9 #include <common.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/arch/mxc_hdmi.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <asm/mach-imx/sata.h>
  26 #include <asm/io.h>
  27 #include <env.h>
  28 #include <linux/delay.h>
  29 #include <linux/sizes.h>
  30 #include <common.h>
  31 #include <miiphy.h>
  32 #include <netdev.h>
  33 #include <phy.h>
  34 #include <i2c.h>
  35 #include <power/pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  49         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  50
  51 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  52 #define ETH_PHY_AR8035_POWER    IMX_GPIO_NR(7, 13)
  53 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  54
  55 /* Speed defined in Kconfig is only applicable when not using DM_I2C.  */
  56 #ifdef CONFIG_DM_I2C
  57 #define I2C1_SPEED_NON_DM       0
  58 #define I2C2_SPEED_NON_DM       0
  59 #else
  60 #define I2C1_SPEED_NON_DM       CONFIG_SYS_MXC_I2C1_SPEED
  61 #define I2C2_SPEED_NON_DM       CONFIG_SYS_MXC_I2C2_SPEED
  62 #endif
  63
  64 static bool with_pmic;
  65
  66 int dram_init(void)
  67 {
  68         gd->ram_size = imx_ddr_size();
  69
  70         return 0;
  71 }
  72
  73 static iomux_v3_cfg_t const uart1_pads[] = {
  74         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  75         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  76 };
  77
  78 static iomux_v3_cfg_t const enet_pads[] = {
  79         /* AR8031 PHY Reset */
  80         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81 };
  82
  83 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  84         /* AR8035 POWER */
  85         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86 };
  87
  88 static iomux_v3_cfg_t const rev_detection_pad[] = {
  89         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90 };
  91
  92 static void setup_iomux_uart(void)
  93 {
  94         SETUP_IOMUX_PADS(uart1_pads);
  95 }
  96
  97 static void setup_iomux_enet(void)
  98 {
  99         SETUP_IOMUX_PADS(enet_pads);
 100
 101         if (with_pmic) {
 102                 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
 103                 /* enable AR8035 POWER */
 104                 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 105                 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 106         }
 107         /* wait until 3.3V of PHY and clock become stable */
 108         mdelay(10);
 109
 110         /* Reset AR8031 PHY */
 111         gpio_request(ETH_PHY_RESET, "PHY_RESET");
 112         gpio_direction_output(ETH_PHY_RESET, 0);
 113         mdelay(10);
 114         gpio_set_value(ETH_PHY_RESET, 1);
 115         udelay(100);
 116 }
 117
 118 static int ar8031_phy_fixup(struct phy_device *phydev)
 119 {
 120         unsigned short val;
 121         int mask;
 122
 123         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 124         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 125         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 126         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 127
 128         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 129         if (with_pmic)
 130                 mask = 0xffe7;  /* AR8035 */
 131         else
 132                 mask = 0xffe3;  /* AR8031 */
 133
 134         val &= mask;
 135         val |= 0x18;
 136         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 137
 138         /* introduce tx clock delay */
 139         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 140         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 141         val |= 0x0100;
 142         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 143
 144         return 0;
 145 }
 146
 147 int board_phy_config(struct phy_device *phydev)
 148 {
 149         ar8031_phy_fixup(phydev);
 150
 151         if (phydev->drv->config)
 152                 phydev->drv->config(phydev);
 153
 154         return 0;
 155 }
 156
 157 #if defined(CONFIG_VIDEO_IPUV3)
 158 struct i2c_pads_info mx6q_i2c2_pad_info = {
 159         .scl = {
 160                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 161                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 162                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 163                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 164                 .gp = IMX_GPIO_NR(4, 12)
 165         },
 166         .sda = {
 167                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 168                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 169                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 170                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 171                 .gp = IMX_GPIO_NR(4, 13)
 172         }
 173 };
 174
 175 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 176         .scl = {
 177                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 178                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 179                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 180                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 181                 .gp = IMX_GPIO_NR(4, 12)
 182         },
 183         .sda = {
 184                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 185                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 186                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 187                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 188                 .gp = IMX_GPIO_NR(4, 13)
 189         }
 190 };
 191
 192 struct i2c_pads_info mx6q_i2c3_pad_info = {
 193         .scl = {
 194                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
 195                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 196                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
 197                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 198                 .gp = IMX_GPIO_NR(1, 5)
 199         },
 200         .sda = {
 201                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
 202                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 203                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
 204                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 205                 .gp = IMX_GPIO_NR(7, 11)
 206         }
 207 };
 208
 209 struct i2c_pads_info mx6dl_i2c3_pad_info = {
 210         .scl = {
 211                 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
 212                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 213                 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
 214                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 215                 .gp = IMX_GPIO_NR(1, 5)
 216         },
 217         .sda = {
 218                 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
 219                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 220                 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
 221                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 222                 .gp = IMX_GPIO_NR(7, 11)
 223         }
 224 };
 225
 226 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 227         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 228         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 229         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 230         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 231         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 232         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 233         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 234         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 235         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 236         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 237         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 238         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 239         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 240         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 241         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 242         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 243         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 244         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 245         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 246         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 247         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 248         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 249         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 250         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 251         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 252 };
 253
 254 static void do_enable_hdmi(struct display_info_t const *dev)
 255 {
 256         imx_enable_hdmi_phy();
 257 }
 258
 259 static int detect_i2c(struct display_info_t const *dev)
 260 {
 261 #ifdef CONFIG_DM_I2C
 262         struct udevice *bus, *udev;
 263         int rc;
 264
 265         rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
 266         if (rc)
 267                 return rc;
 268         rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
 269         if (rc)
 270                 return 0;
 271         return 1;
 272 #else
 273         return (0 == i2c_set_bus_num(dev->bus)) &&
 274                         (0 == i2c_probe(dev->addr));
 275 #endif
 276 }
 277
 278 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 279 {
 280         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 281
 282         gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
 283         gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 284         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 285         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 286 }
 287
 288 struct display_info_t const displays[] = {{
 289         .bus    = -1,
 290         .addr   = 0,
 291         .pixfmt = IPU_PIX_FMT_RGB24,
 292         .detect = detect_hdmi,
 293         .enable = do_enable_hdmi,
 294         .mode   = {
 295                 .name           = "HDMI",
 296                 .refresh        = 60,
 297                 .xres           = 1024,
 298                 .yres           = 768,
 299                 .pixclock       = 15385,
 300                 .left_margin    = 220,
 301                 .right_margin   = 40,
 302                 .upper_margin   = 21,
 303                 .lower_margin   = 7,
 304                 .hsync_len      = 60,
 305                 .vsync_len      = 10,
 306                 .sync           = FB_SYNC_EXT,
 307                 .vmode          = FB_VMODE_NONINTERLACED
 308 } }, {
 309         .bus    = 1,
 310         .addr   = 0x10,
 311         .pixfmt = IPU_PIX_FMT_RGB666,
 312         .detect = detect_i2c,
 313         .enable = enable_fwadapt_7wvga,
 314         .mode   = {
 315                 .name           = "FWBADAPT-LCD-F07A-0102",
 316                 .refresh        = 60,
 317                 .xres           = 800,
 318                 .yres           = 480,
 319                 .pixclock       = 33260,
 320                 .left_margin    = 128,
 321                 .right_margin   = 128,
 322                 .upper_margin   = 22,
 323                 .lower_margin   = 22,
 324                 .hsync_len      = 1,
 325                 .vsync_len      = 1,
 326                 .sync           = 0,
 327                 .vmode          = FB_VMODE_NONINTERLACED
 328 } } };
 329 size_t display_count = ARRAY_SIZE(displays);
 330
 331 static void setup_display(void)
 332 {
 333         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 334         int reg;
 335
 336         enable_ipu_clock();
 337         imx_setup_hdmi();
 338
 339         reg = readl(&mxc_ccm->chsccdr);
 340         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 341                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 342         writel(reg, &mxc_ccm->chsccdr);
 343
 344         /* Disable LCD backlight */
 345         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 346         gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 347         gpio_direction_input(IMX_GPIO_NR(4, 20));
 348 }
 349 #endif /* CONFIG_VIDEO_IPUV3 */
 350
 351 int board_early_init_f(void)
 352 {
 353         setup_iomux_uart();
 354 #ifdef CONFIG_SATA
 355         setup_sata();
 356 #endif
 357
 358         return 0;
 359 }
 360
 361 #define PMIC_I2C_BUS            2
 362
 363 int power_init_board(void)
 364 {
 365         struct udevice *dev;
 366         int reg, ret;
 367
 368         ret = pmic_get("pfuze100@8", &dev);
 369         if (ret < 0) {
 370                 debug("pmic_get() ret %d\n", ret);
 371                 return 0;
 372         }
 373
 374         reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
 375         if (reg < 0) {
 376                 debug("pmic_reg_read() ret %d\n", reg);
 377                 return 0;
 378         }
 379         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 380         with_pmic = true;
 381
 382         /* Set VGEN2 to 1.5V and enable */
 383         reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
 384         reg &= ~(LDO_VOL_MASK);
 385         reg |= (LDOA_1_50V | (1 << (LDO_EN)));
 386         pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 387         return 0;
 388 }
 389
 390 /*
 391  * Do not overwrite the console
 392  * Use always serial for U-Boot console
 393  */
 394 int overwrite_console(void)
 395 {
 396         return 1;
 397 }
 398
 399 #ifdef CONFIG_CMD_BMODE
 400 static const struct boot_mode board_boot_modes[] = {
 401         /* 4 bit bus width */
 402         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 403         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 404         {NULL,   0},
 405 };
 406 #endif
 407
 408 static bool is_revc1(void)
 409 {
 410         SETUP_IOMUX_PADS(rev_detection_pad);
 411         gpio_request(REV_DETECTION, "REV_DETECT");
 412         gpio_direction_input(REV_DETECTION);
 413
 414         if (gpio_get_value(REV_DETECTION))
 415                 return true;
 416         else
 417                 return false;
 418 }
 419
 420 static bool is_revd1(void)
 421 {
 422         if (with_pmic)
 423                 return true;
 424         else
 425                 return false;
 426 }
 427
 428 int board_late_init(void)
 429 {
 430 #ifdef CONFIG_CMD_BMODE
 431         add_board_boot_modes(board_boot_modes);
 432 #endif
 433
 434 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 435         if (is_mx6dqp())
 436                 env_set("board_rev", "MX6QP");
 437         else if (is_mx6dq())
 438                 env_set("board_rev", "MX6Q");
 439         else
 440                 env_set("board_rev", "MX6DL");
 441
 442         if (is_revd1())
 443                 env_set("board_name", "D1");
 444         else if (is_revc1())
 445                 env_set("board_name", "C1");
 446         else
 447                 env_set("board_name", "B1");
 448 #endif
 449         setup_iomux_enet();
 450
 451         if (is_revd1())
 452                 puts("Board: Wandboard rev D1\n");
 453         else if (is_revc1())
 454                 puts("Board: Wandboard rev C1\n");
 455         else
 456                 puts("Board: Wandboard rev B1\n");
 457
 458         return 0;
 459 }
 460
 461 int board_init(void)
 462 {
 463         /* address of boot parameters */
 464         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 465
 466 #if defined(CONFIG_VIDEO_IPUV3)
 467         setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 468         if (is_mx6dq() || is_mx6dqp()) {
 469                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
 470                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
 471         } else {
 472                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 473                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
 474         }
 475
 476         setup_display();
 477 #endif
 478
 479         return 0;
 480 }
 481
 482 #ifdef CONFIG_SPL_LOAD_FIT
 483 int board_fit_config_name_match(const char *name)
 484 {
 485         if (is_mx6dq()) {
 486                 if (!strcmp(name, "imx6q-wandboard-revd1"))
 487                         return 0;
 488         } else if (is_mx6dqp()) {
 489                 if (!strcmp(name, "imx6qp-wandboard-revd1"))
 490                         return 0;
 491         } else if (is_mx6dl() || is_mx6solo()) {
 492                 if (!strcmp(name, "imx6dl-wandboard-revd1"))
 493                         return 0;
 494         }
 495
 496         return -EINVAL;
 497 }
 498 #endif