1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/mx6-pins.h>
18 #include <asm/arch/mxc_hdmi.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-imx/iomux-v3.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/mach-imx/boot_mode.h>
24 #include <asm/mach-imx/video.h>
25 #include <asm/mach-imx/sata.h>
28 #include <linux/sizes.h>
34 #include <power/pmic.h>
35 #include <power/pfuze100_pmic.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
48 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
51 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
52 #define REV_DETECTION IMX_GPIO_NR(2, 28)
54 /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
56 #define I2C1_SPEED_NON_DM 0
57 #define I2C2_SPEED_NON_DM 0
59 #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
60 #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
63 static bool with_pmic;
67 gd->ram_size = imx_ddr_size();
72 static iomux_v3_cfg_t const uart1_pads[] = {
73 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
74 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
77 static iomux_v3_cfg_t const enet_pads[] = {
78 /* AR8031 PHY Reset */
79 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
82 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
84 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
87 static iomux_v3_cfg_t const rev_detection_pad[] = {
88 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 static void setup_iomux_uart(void)
93 SETUP_IOMUX_PADS(uart1_pads);
96 static void setup_iomux_enet(void)
98 SETUP_IOMUX_PADS(enet_pads);
101 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
102 /* enable AR8035 POWER */
103 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
104 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
106 /* wait until 3.3V of PHY and clock become stable */
109 /* Reset AR8031 PHY */
110 gpio_request(ETH_PHY_RESET, "PHY_RESET");
111 gpio_direction_output(ETH_PHY_RESET, 0);
113 gpio_set_value(ETH_PHY_RESET, 1);
117 static int ar8031_phy_fixup(struct phy_device *phydev)
122 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
123 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
124 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
125 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
127 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
129 mask = 0xffe7; /* AR8035 */
131 mask = 0xffe3; /* AR8031 */
135 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
137 /* introduce tx clock delay */
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
139 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
141 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
146 int board_phy_config(struct phy_device *phydev)
148 ar8031_phy_fixup(phydev);
150 if (phydev->drv->config)
151 phydev->drv->config(phydev);
156 #if defined(CONFIG_VIDEO_IPUV3)
157 struct i2c_pads_info mx6q_i2c2_pad_info = {
159 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
160 | MUX_PAD_CTRL(I2C_PAD_CTRL),
161 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
162 | MUX_PAD_CTRL(I2C_PAD_CTRL),
163 .gp = IMX_GPIO_NR(4, 12)
166 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
167 | MUX_PAD_CTRL(I2C_PAD_CTRL),
168 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
169 | MUX_PAD_CTRL(I2C_PAD_CTRL),
170 .gp = IMX_GPIO_NR(4, 13)
174 struct i2c_pads_info mx6dl_i2c2_pad_info = {
176 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
177 | MUX_PAD_CTRL(I2C_PAD_CTRL),
178 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
179 | MUX_PAD_CTRL(I2C_PAD_CTRL),
180 .gp = IMX_GPIO_NR(4, 12)
183 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
184 | MUX_PAD_CTRL(I2C_PAD_CTRL),
185 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
186 | MUX_PAD_CTRL(I2C_PAD_CTRL),
187 .gp = IMX_GPIO_NR(4, 13)
191 struct i2c_pads_info mx6q_i2c3_pad_info = {
193 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
194 | MUX_PAD_CTRL(I2C_PAD_CTRL),
195 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
196 | MUX_PAD_CTRL(I2C_PAD_CTRL),
197 .gp = IMX_GPIO_NR(1, 5)
200 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
201 | MUX_PAD_CTRL(I2C_PAD_CTRL),
202 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
203 | MUX_PAD_CTRL(I2C_PAD_CTRL),
204 .gp = IMX_GPIO_NR(7, 11)
208 struct i2c_pads_info mx6dl_i2c3_pad_info = {
210 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
211 | MUX_PAD_CTRL(I2C_PAD_CTRL),
212 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
213 | MUX_PAD_CTRL(I2C_PAD_CTRL),
214 .gp = IMX_GPIO_NR(1, 5)
217 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
218 | MUX_PAD_CTRL(I2C_PAD_CTRL),
219 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
220 | MUX_PAD_CTRL(I2C_PAD_CTRL),
221 .gp = IMX_GPIO_NR(7, 11)
225 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
226 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
227 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
228 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
229 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
230 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
231 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
232 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
233 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
234 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
235 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
236 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
237 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
238 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
239 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
240 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
241 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
242 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
243 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
244 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
245 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
246 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
247 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
248 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
249 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
250 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
253 static void do_enable_hdmi(struct display_info_t const *dev)
255 imx_enable_hdmi_phy();
258 static int detect_i2c(struct display_info_t const *dev)
261 struct udevice *bus, *udev;
264 rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
267 rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
272 return (0 == i2c_set_bus_num(dev->bus)) &&
273 (0 == i2c_probe(dev->addr));
277 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
279 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
281 gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
282 gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
283 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
284 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
287 struct display_info_t const displays[] = {{
290 .pixfmt = IPU_PIX_FMT_RGB24,
291 .detect = detect_hdmi,
292 .enable = do_enable_hdmi,
306 .vmode = FB_VMODE_NONINTERLACED
310 .pixfmt = IPU_PIX_FMT_RGB666,
311 .detect = detect_i2c,
312 .enable = enable_fwadapt_7wvga,
314 .name = "FWBADAPT-LCD-F07A-0102",
326 .vmode = FB_VMODE_NONINTERLACED
328 size_t display_count = ARRAY_SIZE(displays);
330 static void setup_display(void)
332 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
338 reg = readl(&mxc_ccm->chsccdr);
339 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
340 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
341 writel(reg, &mxc_ccm->chsccdr);
343 /* Disable LCD backlight */
344 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
345 gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
346 gpio_direction_input(IMX_GPIO_NR(4, 20));
348 #endif /* CONFIG_VIDEO_IPUV3 */
350 int board_early_init_f(void)
360 #define PMIC_I2C_BUS 2
362 int power_init_board(void)
367 ret = pmic_get("pfuze100@8", &dev);
369 debug("pmic_get() ret %d\n", ret);
373 reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
375 debug("pmic_reg_read() ret %d\n", reg);
378 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
381 /* Set VGEN2 to 1.5V and enable */
382 reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
383 reg &= ~(LDO_VOL_MASK);
384 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
385 pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
390 * Do not overwrite the console
391 * Use always serial for U-Boot console
393 int overwrite_console(void)
398 #ifdef CONFIG_CMD_BMODE
399 static const struct boot_mode board_boot_modes[] = {
400 /* 4 bit bus width */
401 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
402 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
407 static bool is_revc1(void)
409 SETUP_IOMUX_PADS(rev_detection_pad);
410 gpio_request(REV_DETECTION, "REV_DETECT");
411 gpio_direction_input(REV_DETECTION);
413 if (gpio_get_value(REV_DETECTION))
419 static bool is_revd1(void)
427 int board_late_init(void)
429 #ifdef CONFIG_CMD_BMODE
430 add_board_boot_modes(board_boot_modes);
433 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
435 env_set("board_rev", "MX6QP");
437 env_set("board_rev", "MX6Q");
439 env_set("board_rev", "MX6DL");
442 env_set("board_name", "D1");
444 env_set("board_name", "C1");
446 env_set("board_name", "B1");
451 puts("Board: Wandboard rev D1\n");
453 puts("Board: Wandboard rev C1\n");
455 puts("Board: Wandboard rev B1\n");
462 /* address of boot parameters */
463 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
465 #if defined(CONFIG_VIDEO_IPUV3)
466 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
467 if (is_mx6dq() || is_mx6dqp()) {
468 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
469 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
471 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
472 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
481 #ifdef CONFIG_SPL_LOAD_FIT
482 int board_fit_config_name_match(const char *name)
485 if (!strcmp(name, "imx6q-wandboard-revd1"))
487 } else if (is_mx6dqp()) {
488 if (!strcmp(name, "imx6qp-wandboard-revd1"))
490 } else if (is_mx6dl() || is_mx6solo()) {
491 if (!strcmp(name, "imx6dl-wandboard-revd1"))