board/wandboard/wandboard.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2014 O.S. Systems Software LTDA.
   5  *
   6  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/mach-imx/sata.h>
  22 #include <asm/io.h>
  23 #include <linux/sizes.h>
  24 #include <common.h>
  25 #include <fsl_esdhc.h>
  26 #include <mmc.h>
  27 #include <miiphy.h>
  28 #include <netdev.h>
  29 #include <phy.h>
  30 #include <i2c.h>
  31 #include <power/pmic.h>
  32 #include <power/pfuze100_pmic.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  41         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  49         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  50
  51 #define USDHC1_CD_GPIO          IMX_GPIO_NR(1, 2)
  52 #define USDHC3_CD_GPIO          IMX_GPIO_NR(3, 9)
  53 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  54 #define ETH_PHY_AR8035_POWER    IMX_GPIO_NR(7, 13)
  55 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  56
  57 static bool with_pmic;
  58
  59 int dram_init(void)
  60 {
  61         gd->ram_size = imx_ddr_size();
  62
  63         return 0;
  64 }
  65
  66 static iomux_v3_cfg_t const uart1_pads[] = {
  67         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  68         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  69 };
  70
  71 static iomux_v3_cfg_t const usdhc1_pads[] = {
  72         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78         /* Carrier MicroSD Card Detect */
  79         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  80 };
  81
  82 static iomux_v3_cfg_t const usdhc3_pads[] = {
  83         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89         /* SOM MicroSD Card Detect */
  90         IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91 };
  92
  93 static iomux_v3_cfg_t const enet_pads[] = {
  94         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 100         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 101         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 102         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 103         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 104         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 105         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 106         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 107         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 108         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 109         /* AR8031 PHY Reset */
 110         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 111 };
 112
 113 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
 114         /* AR8035 POWER */
 115         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 116 };
 117
 118 static iomux_v3_cfg_t const rev_detection_pad[] = {
 119         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 120 };
 121
 122 static void setup_iomux_uart(void)
 123 {
 124         SETUP_IOMUX_PADS(uart1_pads);
 125 }
 126
 127 static void setup_iomux_enet(void)
 128 {
 129         SETUP_IOMUX_PADS(enet_pads);
 130
 131         if (with_pmic) {
 132                 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
 133                 /* enable AR8035 POWER */
 134                 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 135                 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 136         }
 137         /* wait until 3.3V of PHY and clock become stable */
 138         mdelay(10);
 139
 140         /* Reset AR8031 PHY */
 141         gpio_request(ETH_PHY_RESET, "PHY_RESET");
 142         gpio_direction_output(ETH_PHY_RESET, 0);
 143         mdelay(10);
 144         gpio_set_value(ETH_PHY_RESET, 1);
 145         udelay(100);
 146 }
 147
 148 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 149         {USDHC3_BASE_ADDR},
 150         {USDHC1_BASE_ADDR},
 151 };
 152
 153 int board_mmc_getcd(struct mmc *mmc)
 154 {
 155         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 156         int ret = 0;
 157
 158         switch (cfg->esdhc_base) {
 159         case USDHC1_BASE_ADDR:
 160                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 161                 break;
 162         case USDHC3_BASE_ADDR:
 163                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 164                 break;
 165         }
 166
 167         return ret;
 168 }
 169
 170 int board_mmc_init(bd_t *bis)
 171 {
 172         int ret;
 173         u32 index = 0;
 174
 175 #if !CONFIG_IS_ENABLED(DM_MMC)
 176         gpio_request(USDHC1_CD_GPIO, "USDHC1_CD");
 177         gpio_request(USDHC3_CD_GPIO, "USDHC3_CD");
 178 #endif
 179
 180         /*
 181          * Following map is done:
 182          * (U-Boot device node)    (Physical Port)
 183          * mmc0                    SOM MicroSD
 184          * mmc1                    Carrier board MicroSD
 185          */
 186         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 187                 switch (index) {
 188                 case 0:
 189                         SETUP_IOMUX_PADS(usdhc3_pads);
 190                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 191                         usdhc_cfg[0].max_bus_width = 4;
 192                         gpio_direction_input(USDHC3_CD_GPIO);
 193                         break;
 194                 case 1:
 195                         SETUP_IOMUX_PADS(usdhc1_pads);
 196                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 197                         usdhc_cfg[1].max_bus_width = 4;
 198                         gpio_direction_input(USDHC1_CD_GPIO);
 199                         break;
 200                 default:
 201                         printf("Warning: you configured more USDHC controllers"
 202                                "(%d) then supported by the board (%d)\n",
 203                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 204                         return -EINVAL;
 205                 }
 206
 207                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 208                 if (ret)
 209                         return ret;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int ar8031_phy_fixup(struct phy_device *phydev)
 216 {
 217         unsigned short val;
 218         int mask;
 219
 220         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 221         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 222         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 223         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 224
 225         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 226         if (with_pmic)
 227                 mask = 0xffe7;  /* AR8035 */
 228         else
 229                 mask = 0xffe3;  /* AR8031 */
 230
 231         val &= mask;
 232         val |= 0x18;
 233         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 234
 235         /* introduce tx clock delay */
 236         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 237         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 238         val |= 0x0100;
 239         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 240
 241         return 0;
 242 }
 243
 244 int board_phy_config(struct phy_device *phydev)
 245 {
 246         ar8031_phy_fixup(phydev);
 247
 248         if (phydev->drv->config)
 249                 phydev->drv->config(phydev);
 250
 251         return 0;
 252 }
 253
 254 #if defined(CONFIG_VIDEO_IPUV3)
 255 struct i2c_pads_info mx6q_i2c2_pad_info = {
 256         .scl = {
 257                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 258                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 259                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 260                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 261                 .gp = IMX_GPIO_NR(4, 12)
 262         },
 263         .sda = {
 264                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 265                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 266                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 267                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 268                 .gp = IMX_GPIO_NR(4, 13)
 269         }
 270 };
 271
 272 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 273         .scl = {
 274                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 275                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 276                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 277                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 278                 .gp = IMX_GPIO_NR(4, 12)
 279         },
 280         .sda = {
 281                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 282                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 283                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 284                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 285                 .gp = IMX_GPIO_NR(4, 13)
 286         }
 287 };
 288
 289 struct i2c_pads_info mx6q_i2c3_pad_info = {
 290         .scl = {
 291                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
 292                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 293                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
 294                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 295                 .gp = IMX_GPIO_NR(1, 5)
 296         },
 297         .sda = {
 298                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
 299                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 300                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
 301                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 302                 .gp = IMX_GPIO_NR(7, 11)
 303         }
 304 };
 305
 306 struct i2c_pads_info mx6dl_i2c3_pad_info = {
 307         .scl = {
 308                 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
 309                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 310                 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
 311                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 312                 .gp = IMX_GPIO_NR(1, 5)
 313         },
 314         .sda = {
 315                 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
 316                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 317                 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
 318                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 319                 .gp = IMX_GPIO_NR(7, 11)
 320         }
 321 };
 322
 323 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 324         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 325         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 326         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 327         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 328         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 329         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 330         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 331         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 332         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 333         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 334         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 335         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 336         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 337         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 338         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 339         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 340         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 341         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 342         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 343         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 344         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 345         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 346         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 347         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 348         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 349 };
 350
 351 static void do_enable_hdmi(struct display_info_t const *dev)
 352 {
 353         imx_enable_hdmi_phy();
 354 }
 355
 356 static int detect_i2c(struct display_info_t const *dev)
 357 {
 358 #ifdef CONFIG_DM_I2C
 359         struct udevice *bus, *udev;
 360         int rc;
 361
 362         rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
 363         if (rc)
 364                 return rc;
 365         rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
 366         if (rc)
 367                 return 0;
 368         return 1;
 369 #else
 370         return (0 == i2c_set_bus_num(dev->bus)) &&
 371                         (0 == i2c_probe(dev->addr));
 372 #endif
 373 }
 374
 375 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 376 {
 377         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 378
 379         gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
 380         gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 381         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 382         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 383 }
 384
 385 struct display_info_t const displays[] = {{
 386         .bus    = -1,
 387         .addr   = 0,
 388         .pixfmt = IPU_PIX_FMT_RGB24,
 389         .detect = detect_hdmi,
 390         .enable = do_enable_hdmi,
 391         .mode   = {
 392                 .name           = "HDMI",
 393                 .refresh        = 60,
 394                 .xres           = 1024,
 395                 .yres           = 768,
 396                 .pixclock       = 15385,
 397                 .left_margin    = 220,
 398                 .right_margin   = 40,
 399                 .upper_margin   = 21,
 400                 .lower_margin   = 7,
 401                 .hsync_len      = 60,
 402                 .vsync_len      = 10,
 403                 .sync           = FB_SYNC_EXT,
 404                 .vmode          = FB_VMODE_NONINTERLACED
 405 } }, {
 406         .bus    = 1,
 407         .addr   = 0x10,
 408         .pixfmt = IPU_PIX_FMT_RGB666,
 409         .detect = detect_i2c,
 410         .enable = enable_fwadapt_7wvga,
 411         .mode   = {
 412                 .name           = "FWBADAPT-LCD-F07A-0102",
 413                 .refresh        = 60,
 414                 .xres           = 800,
 415                 .yres           = 480,
 416                 .pixclock       = 33260,
 417                 .left_margin    = 128,
 418                 .right_margin   = 128,
 419                 .upper_margin   = 22,
 420                 .lower_margin   = 22,
 421                 .hsync_len      = 1,
 422                 .vsync_len      = 1,
 423                 .sync           = 0,
 424                 .vmode          = FB_VMODE_NONINTERLACED
 425 } } };
 426 size_t display_count = ARRAY_SIZE(displays);
 427
 428 static void setup_display(void)
 429 {
 430         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 431         int reg;
 432
 433         enable_ipu_clock();
 434         imx_setup_hdmi();
 435
 436         reg = readl(&mxc_ccm->chsccdr);
 437         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 438                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 439         writel(reg, &mxc_ccm->chsccdr);
 440
 441         /* Disable LCD backlight */
 442         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 443         gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 444         gpio_direction_input(IMX_GPIO_NR(4, 20));
 445 }
 446 #endif /* CONFIG_VIDEO_IPUV3 */
 447
 448 int board_eth_init(bd_t *bis)
 449 {
 450         setup_iomux_enet();
 451
 452         return cpu_eth_init(bis);
 453 }
 454
 455 int board_early_init_f(void)
 456 {
 457         setup_iomux_uart();
 458 #ifdef CONFIG_SATA
 459         setup_sata();
 460 #endif
 461
 462         return 0;
 463 }
 464
 465 #define PMIC_I2C_BUS            2
 466
 467 int power_init_board(void)
 468 {
 469         struct udevice *dev;
 470         int reg, ret;
 471
 472         puts("PMIC:  ");
 473
 474         ret = pmic_get("pfuze100", &dev);
 475         if (ret < 0) {
 476                 printf("pmic_get() ret %d\n", ret);
 477                 return 0;
 478         }
 479
 480         reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
 481         if (reg < 0) {
 482                 printf("pmic_reg_read() ret %d\n", reg);
 483                 return 0;
 484         }
 485         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 486         with_pmic = true;
 487
 488         /* Set VGEN2 to 1.5V and enable */
 489         reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
 490         reg &= ~(LDO_VOL_MASK);
 491         reg |= (LDOA_1_50V | (1 << (LDO_EN)));
 492         pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 493         return 0;
 494 }
 495
 496 /*
 497  * Do not overwrite the console
 498  * Use always serial for U-Boot console
 499  */
 500 int overwrite_console(void)
 501 {
 502         return 1;
 503 }
 504
 505 #ifdef CONFIG_CMD_BMODE
 506 static const struct boot_mode board_boot_modes[] = {
 507         /* 4 bit bus width */
 508         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 509         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 510         {NULL,   0},
 511 };
 512 #endif
 513
 514 static bool is_revc1(void)
 515 {
 516         SETUP_IOMUX_PADS(rev_detection_pad);
 517         gpio_direction_input(REV_DETECTION);
 518
 519         if (gpio_get_value(REV_DETECTION))
 520                 return true;
 521         else
 522                 return false;
 523 }
 524
 525 static bool is_revd1(void)
 526 {
 527         if (with_pmic)
 528                 return true;
 529         else
 530                 return false;
 531 }
 532
 533 int board_late_init(void)
 534 {
 535 #ifdef CONFIG_CMD_BMODE
 536         add_board_boot_modes(board_boot_modes);
 537 #endif
 538
 539 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 540         if (is_mx6dqp())
 541                 env_set("board_rev", "MX6QP");
 542         else if (is_mx6dq())
 543                 env_set("board_rev", "MX6Q");
 544         else
 545                 env_set("board_rev", "MX6DL");
 546
 547         if (is_revd1())
 548                 env_set("board_name", "D1");
 549         else if (is_revc1())
 550                 env_set("board_name", "C1");
 551         else
 552                 env_set("board_name", "B1");
 553 #endif
 554         return 0;
 555 }
 556
 557 int board_init(void)
 558 {
 559         /* address of boot parameters */
 560         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 561
 562 #if defined(CONFIG_VIDEO_IPUV3)
 563         setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 564         if (is_mx6dq() || is_mx6dqp()) {
 565                 setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 566                 setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
 567         } else {
 568                 setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 569                 setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
 570         }
 571
 572         setup_display();
 573 #endif
 574
 575         return 0;
 576 }
 577
 578 int checkboard(void)
 579 {
 580         gpio_request(REV_DETECTION, "REV_DETECT");
 581
 582         if (is_revd1())
 583                 puts("Board: Wandboard rev D1\n");
 584         else if (is_revc1())
 585                 puts("Board: Wandboard rev C1\n");
 586         else
 587                 puts("Board: Wandboard rev B1\n");
 588
 589         return 0;
 590 }