board/wandboard/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Wandboard
   4  * Author: Tungyi Lin <tungyilin1127@gmail.com>
   5  *         Richard Hu <hakahu@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <linux/errno.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <spl.h>
  24
  25 #include <asm/arch/mx6-ddr.h>
  26 /*
  27  * Driving strength:
  28  *   0x30 == 40 Ohm
  29  *   0x28 == 48 Ohm
  30  */
  31
  32 #define IMX6DQ_DRIVE_STRENGTH           0x30
  33 #define IMX6SDL_DRIVE_STRENGTH          0x28
  34 #define IMX6QP_DRIVE_STRENGTH           0x28
  35
  36 /* configure MX6Q/DUAL mmdc DDR io registers */
  37 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  38         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  39         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  40         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  41         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  42         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  43         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  44         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  45         .dram_sdba2 = 0x00000000,
  46         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  47         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  48         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  53         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  58         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  59         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  60         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  61         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  62         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  63         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  64 };
  65
  66 /* configure MX6QP mmdc DDR io registers */
  67 static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
  68         .dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
  69         .dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
  70         .dram_cas = IMX6QP_DRIVE_STRENGTH,
  71         .dram_ras = IMX6QP_DRIVE_STRENGTH,
  72         .dram_reset = IMX6QP_DRIVE_STRENGTH,
  73         .dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
  74         .dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
  75         .dram_sdba2 = 0x00000000,
  76         .dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
  77         .dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
  78         .dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
  79         .dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
  80         .dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
  81         .dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
  82         .dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
  83         .dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
  84         .dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
  85         .dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
  86         .dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
  87         .dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
  88         .dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
  89         .dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
  90         .dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
  91         .dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
  92         .dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
  93         .dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
  94 };
  95
  96 /* configure MX6Q/DUAL mmdc GRP io registers */
  97 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  98         .grp_ddr_type = 0x000c0000,
  99         .grp_ddrmode_ctl = 0x00020000,
 100         .grp_ddrpke = 0x00000000,
 101         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
 102         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
 103         .grp_ddrmode = 0x00020000,
 104         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
 105         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
 106         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
 107         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
 108         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
 109         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
 110         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
 111         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 112 };
 113
 114 /* configure MX6QP mmdc GRP io registers */
 115 static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
 116         .grp_ddr_type = 0x000c0000,
 117         .grp_ddrmode_ctl = 0x00020000,
 118         .grp_ddrpke = 0x00000000,
 119         .grp_addds = IMX6QP_DRIVE_STRENGTH,
 120         .grp_ctlds = IMX6QP_DRIVE_STRENGTH,
 121         .grp_ddrmode = 0x00020000,
 122         .grp_b0ds = IMX6QP_DRIVE_STRENGTH,
 123         .grp_b1ds = IMX6QP_DRIVE_STRENGTH,
 124         .grp_b2ds = IMX6QP_DRIVE_STRENGTH,
 125         .grp_b3ds = IMX6QP_DRIVE_STRENGTH,
 126         .grp_b4ds = IMX6QP_DRIVE_STRENGTH,
 127         .grp_b5ds = IMX6QP_DRIVE_STRENGTH,
 128         .grp_b6ds = IMX6QP_DRIVE_STRENGTH,
 129         .grp_b7ds = IMX6QP_DRIVE_STRENGTH,
 130 };
 131
 132 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 133 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 134         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 135         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 136         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 137         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 138         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 139         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 140         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 141         .dram_sdba2 = 0x00000000,
 142         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 143         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 144         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 145         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 146         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 147         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 148         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 149         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 150         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 151         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 152         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 153         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 154         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 155         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 156         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 157         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 158         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 159         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 160 };
 161
 162 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 163 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 164         .grp_ddr_type = 0x000c0000,
 165         .grp_ddrmode_ctl = 0x00020000,
 166         .grp_ddrpke = 0x00000000,
 167         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 168         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 169         .grp_ddrmode = 0x00020000,
 170         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 171         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 172         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 173         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 174         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 175         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 176         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 177         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 178 };
 179
 180 /* H5T04G63AFR-PB */
 181 static struct mx6_ddr3_cfg h5t04g63afr = {
 182         .mem_speed = 1600,
 183         .density = 4,
 184         .width = 16,
 185         .banks = 8,
 186         .rowaddr = 15,
 187         .coladdr = 10,
 188         .pagesz = 2,
 189         .trcd = 1375,
 190         .trcmin = 4875,
 191         .trasmin = 3500,
 192 };
 193
 194 /* H5TQ2G63DFR-H9 */
 195 static struct mx6_ddr3_cfg h5tq2g63dfr = {
 196         .mem_speed = 1333,
 197         .density = 2,
 198         .width = 16,
 199         .banks = 8,
 200         .rowaddr = 14,
 201         .coladdr = 10,
 202         .pagesz = 2,
 203         .trcd = 1350,
 204         .trcmin = 4950,
 205         .trasmin = 3600,
 206 };
 207
 208 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
 209         .p0_mpwldectrl0 = 0x001f001f,
 210         .p0_mpwldectrl1 = 0x001f001f,
 211         .p1_mpwldectrl0 = 0x001f001f,
 212         .p1_mpwldectrl1 = 0x001f001f,
 213         .p0_mpdgctrl0 = 0x4301030d,
 214         .p0_mpdgctrl1 = 0x03020277,
 215         .p1_mpdgctrl0 = 0x4300030a,
 216         .p1_mpdgctrl1 = 0x02780248,
 217         .p0_mprddlctl = 0x4536393b,
 218         .p1_mprddlctl = 0x36353441,
 219         .p0_mpwrdlctl = 0x41414743,
 220         .p1_mpwrdlctl = 0x462f453f,
 221 };
 222
 223 /* DDR 64bit 2GB */
 224 static struct mx6_ddr_sysinfo mem_q = {
 225         .dsize          = 2,
 226         .cs1_mirror     = 0,
 227         /* config for full 4GB range so that get_mem_size() works */
 228         .cs_density     = 32,
 229         .ncs            = 1,
 230         .bi_on          = 1,
 231         .rtt_nom        = 1,
 232         .rtt_wr         = 0,
 233         .ralat          = 5,
 234         .walat          = 0,
 235         .mif3_mode      = 3,
 236         .rst_to_cke     = 0x23,
 237         .sde_to_rst     = 0x10,
 238         .refsel = 1,    /* Refresh cycles at 32KHz */
 239         .refr = 3,      /* 4 refresh commands per refresh cycle */
 240 };
 241
 242 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 243         .p0_mpwldectrl0 = 0x001f001f,
 244         .p0_mpwldectrl1 = 0x001f001f,
 245         .p1_mpwldectrl0 = 0x001f001f,
 246         .p1_mpwldectrl1 = 0x001f001f,
 247         .p0_mpdgctrl0 = 0x420e020e,
 248         .p0_mpdgctrl1 = 0x02000200,
 249         .p1_mpdgctrl0 = 0x42020202,
 250         .p1_mpdgctrl1 = 0x01720172,
 251         .p0_mprddlctl = 0x494c4f4c,
 252         .p1_mprddlctl = 0x4a4c4c49,
 253         .p0_mpwrdlctl = 0x3f3f3133,
 254         .p1_mpwrdlctl = 0x39373f2e,
 255 };
 256
 257 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
 258         .p0_mpwldectrl0 = 0x0040003c,
 259         .p0_mpwldectrl1 = 0x0032003e,
 260         .p0_mpdgctrl0 = 0x42350231,
 261         .p0_mpdgctrl1 = 0x021a0218,
 262         .p0_mprddlctl = 0x4b4b4e49,
 263         .p0_mpwrdlctl = 0x3f3f3035,
 264 };
 265
 266 /* DDR 64bit 1GB */
 267 static struct mx6_ddr_sysinfo mem_dl = {
 268         .dsize          = 2,
 269         .cs1_mirror     = 0,
 270         /* config for full 4GB range so that get_mem_size() works */
 271         .cs_density     = 32,
 272         .ncs            = 1,
 273         .bi_on          = 1,
 274         .rtt_nom        = 1,
 275         .rtt_wr         = 0,
 276         .ralat          = 5,
 277         .walat          = 0,
 278         .mif3_mode      = 3,
 279         .rst_to_cke     = 0x23,
 280         .sde_to_rst     = 0x10,
 281         .refsel = 1,    /* Refresh cycles at 32KHz */
 282         .refr = 3,      /* 4 refresh commands per refresh cycle */
 283 };
 284
 285 /* DDR 32bit 512MB */
 286 static struct mx6_ddr_sysinfo mem_s = {
 287         .dsize          = 1,
 288         .cs1_mirror     = 0,
 289         /* config for full 4GB range so that get_mem_size() works */
 290         .cs_density     = 32,
 291         .ncs            = 1,
 292         .bi_on          = 1,
 293         .rtt_nom        = 1,
 294         .rtt_wr         = 0,
 295         .ralat          = 5,
 296         .walat          = 0,
 297         .mif3_mode      = 3,
 298         .rst_to_cke     = 0x23,
 299         .sde_to_rst     = 0x10,
 300         .refsel = 1,    /* Refresh cycles at 32KHz */
 301         .refr = 3,      /* 4 refresh commands per refresh cycle */
 302 };
 303
 304 static void ccgr_init(void)
 305 {
 306         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 307
 308         writel(0x00C03F3F, &ccm->CCGR0);
 309         writel(0x0030FC03, &ccm->CCGR1);
 310         writel(0x0FFFC000, &ccm->CCGR2);
 311         writel(0x3FF03000, &ccm->CCGR3);
 312         writel(0x00FFF300, &ccm->CCGR4);
 313         writel(0x0F0000C3, &ccm->CCGR5);
 314         writel(0x000003FF, &ccm->CCGR6);
 315 }
 316
 317 static void spl_dram_init_imx6qp_lpddr3(void)
 318 {
 319         /* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
 320         writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
 321         /* Calibrations - ZQ */
 322         writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
 323         /* write leveling */
 324         writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
 325         writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
 326         writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
 327         writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
 328         /*
 329          * DQS gating, read delay, write delay calibration values
 330          * based on calibration compare of 0x00ffff00
 331          */
 332         writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
 333         writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
 334         writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
 335         writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
 336         writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
 337         writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
 338         writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
 339         writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
 340         writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
 341         writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
 342         writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
 343         writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
 344         writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
 345         writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
 346         writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
 347         writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
 348         writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
 349         writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
 350         writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
 351         writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
 352         /* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
 353         writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
 354         writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
 355         writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
 356         writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
 357         writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
 358         writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
 359         writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
 360         writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
 361         writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
 362         writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
 363         writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
 364         writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
 365         writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
 366         /* add NOC DDR configuration */
 367         writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
 368         writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
 369         writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
 370         writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
 371         writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
 372         writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
 373         writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
 374         writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
 375         writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
 376         writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
 377         writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
 378         writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
 379         writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
 380         writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
 381         writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
 382         writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
 383         writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
 384 }
 385
 386 static void spl_dram_init(void)
 387 {
 388         if (is_mx6dqp()) {
 389                 mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
 390                 spl_dram_init_imx6qp_lpddr3();
 391         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 392                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 393                 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
 394         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 395                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 396                 mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
 397         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 398                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 399                 mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
 400         }
 401
 402         udelay(100);
 403 }
 404
 405 void board_init_f(ulong dummy)
 406 {
 407         ccgr_init();
 408
 409         /* setup AIPS and disable watchdog */
 410         arch_cpu_init();
 411
 412         gpr_init();
 413
 414         /* iomux */
 415         board_early_init_f();
 416
 417         /* setup GP timer */
 418         timer_init();
 419
 420         /* UART clocks enabled and gd valid - init serial console */
 421         preloader_console_init();
 422
 423         /* DDR initialization */
 424         spl_dram_init();
 425 }
 426
 427 #define USDHC1_CD_GPIO          IMX_GPIO_NR(1, 2)
 428 #define USDHC3_CD_GPIO          IMX_GPIO_NR(3, 9)
 429
 430 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 431         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
 432         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 433
 434 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 435         {USDHC3_BASE_ADDR},
 436         {USDHC1_BASE_ADDR},
 437 };
 438
 439 static iomux_v3_cfg_t const usdhc1_pads[] = {
 440         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 441         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 442         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 443         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 444         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 445         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 446         /* Carrier MicroSD Card Detect */
 447         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 448 };
 449
 450 static iomux_v3_cfg_t const usdhc3_pads[] = {
 451         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 452         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 453         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 454         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 455         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 456         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 457         /* SOM MicroSD Card Detect */
 458         IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 459 };
 460
 461 int board_mmc_getcd(struct mmc *mmc)
 462 {
 463         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 464         int ret = 0;
 465
 466         switch (cfg->esdhc_base) {
 467         case USDHC1_BASE_ADDR:
 468                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 469                 break;
 470         case USDHC3_BASE_ADDR:
 471                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 472                 break;
 473         }
 474
 475         return ret;
 476 }
 477
 478 int board_mmc_init(bd_t *bis)
 479 {
 480         int ret;
 481         u32 index = 0;
 482
 483         /*
 484          * Following map is done:
 485          * (U-Boot device node)    (Physical Port)
 486          * mmc0                    SOM MicroSD
 487          * mmc1                    Carrier board MicroSD
 488          */
 489         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 490                 switch (index) {
 491                 case 0:
 492                         SETUP_IOMUX_PADS(usdhc3_pads);
 493                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 494                         usdhc_cfg[0].max_bus_width = 4;
 495                         gpio_direction_input(USDHC3_CD_GPIO);
 496                         break;
 497                 case 1:
 498                         SETUP_IOMUX_PADS(usdhc1_pads);
 499                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 500                         usdhc_cfg[1].max_bus_width = 4;
 501                         gpio_direction_input(USDHC1_CD_GPIO);
 502                         break;
 503                 default:
 504                         printf("Warning: you configured more USDHC controllers"
 505                                "(%d) then supported by the board (%d)\n",
 506                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 507                         return -EINVAL;
 508                 }
 509
 510                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 511                 if (ret)
 512                         return ret;
 513         }
 514
 515         return 0;
 516 }