board/variscite/dart_6ul/dart_6ul.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2019 Variscite Ltd.
   4  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
   5  */
   6
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/mx6-pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/mach-imx/mxc_i2c.h>
  14 #include <fsl_esdhc_imx.h>
  15 #include <linux/bitops.h>
  16 #include <miiphy.h>
  17 #include <netdev.h>
  18 #include <usb.h>
  19 #include <usb/ehci-ci.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int dram_init(void)
  24 {
  25         gd->ram_size = imx_ddr_size();
  26
  27         return 0;
  28 }
  29
  30 #ifdef CONFIG_NAND_MXS
  31 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  32 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  33                         PAD_CTL_SRE_FAST)
  34 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  35 static iomux_v3_cfg_t const nand_pads[] = {
  36         MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  37         MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  38         MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  39         MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  40         MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  41         MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  42         MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  43         MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  44         MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  45         MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  46         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  47         MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  48         MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  49         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  50         MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  51         MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  52 };
  53
  54 static void setup_gpmi_nand(void)
  55 {
  56         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  57
  58         /* config gpmi nand iomux */
  59         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  60
  61         clrbits_le32(&mxc_ccm->CCGR4,
  62                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  63                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  64                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  65                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  66                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  67
  68         /*
  69          * config gpmi and bch clock to 100 MHz
  70          * bch/gpmi select PLL2 PFD2 400M
  71          * 100M = 400M / 4
  72          */
  73         clrbits_le32(&mxc_ccm->cscmr1,
  74                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  75                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  76         clrsetbits_le32(&mxc_ccm->cscdr1,
  77                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  78                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  79                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  80                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  81
  82         /* enable gpmi and bch clock gating */
  83         setbits_le32(&mxc_ccm->CCGR4,
  84                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  85                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  86                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  87                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  88                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  89
  90         /* enable apbh clock gating */
  91         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  92 }
  93 #endif
  94
  95 #ifdef CONFIG_FEC_MXC
  96 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  97 #define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       | \
  98                            PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
  99                            PAD_CTL_SRE_FAST)
 100 #define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      | \
 101                            PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
 102                            PAD_CTL_ODE)
 103 /*
 104  * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
 105  * be used for ENET1 or ENET2, cannot be used for both.
 106  */
 107 static iomux_v3_cfg_t const fec1_pads[] = {
 108         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 109         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 114         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118 };
 119
 120 static iomux_v3_cfg_t const fec2_pads[] = {
 121         MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 122         MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 125         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 126         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 127         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 128         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 129         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 130         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 131 };
 132
 133 static void setup_iomux_fec(int fec_id)
 134 {
 135         if (fec_id == 0)
 136                 imx_iomux_v3_setup_multiple_pads(fec1_pads,
 137                                                  ARRAY_SIZE(fec1_pads));
 138         else
 139                 imx_iomux_v3_setup_multiple_pads(fec2_pads,
 140                                                  ARRAY_SIZE(fec2_pads));
 141 }
 142
 143 int board_eth_init(bd_t *bis)
 144 {
 145         int ret = 0;
 146
 147         ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
 148                                       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 149
 150 #if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
 151         /* USB Ethernet Gadget */
 152         usb_eth_initialize(bis);
 153 #endif
 154         return ret;
 155 }
 156
 157 static int setup_fec(int fec_id)
 158 {
 159         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 160         int ret;
 161
 162         if (fec_id == 0) {
 163                 /*
 164                  * Use 50M anatop loopback REF_CLK1 for ENET1,
 165                  * clear gpr1[13], set gpr1[17].
 166                  */
 167                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 168                                 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 169         } else {
 170                 /*
 171                  * Use 50M anatop loopback REF_CLK2 for ENET2,
 172                  * clear gpr1[14], set gpr1[18].
 173                  */
 174                 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 175                                 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 176         }
 177
 178         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 179         if (ret)
 180                 return ret;
 181
 182         enable_enet_clk(1);
 183
 184         return 0;
 185 }
 186
 187 int board_phy_config(struct phy_device *phydev)
 188 {
 189         /*
 190          * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
 191          * 50 MHz RMII clock mode.
 192          */
 193         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 194
 195         if (phydev->drv->config)
 196                 phydev->drv->config(phydev);
 197
 198         return 0;
 199 }
 200 #endif /* CONFIG_FEC_MXC */
 201
 202 int board_early_init_f(void)
 203 {
 204         setup_iomux_fec(CONFIG_FEC_ENET_DEV);
 205
 206         return 0;
 207 }
 208
 209 int board_init(void)
 210 {
 211         /* Address of boot parameters */
 212         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 213
 214 #ifdef CONFIG_FEC_MXC
 215         setup_fec(CONFIG_FEC_ENET_DEV);
 216 #endif
 217
 218 #ifdef CONFIG_NAND_MXS
 219         setup_gpmi_nand();
 220 #endif
 221         return 0;
 222 }
 223
 224 int checkboard(void)
 225 {
 226         puts("Board: Variscite DART-6UL Evaluation Kit\n");
 227
 228         return 0;
 229 }