board/udoo/udoo_spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Udoo
   4  * Author: Tungyi Lin <tungyilin1127@gmail.com>
   5  *         Richard Hu <hakahu@gmail.com>
   6  * Based on board/wandboard/spl.c
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/video.h>
  20 #include <mmc.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <spl.h>
  26
  27 #if defined(CONFIG_SPL_BUILD)
  28 #include <asm/arch/mx6-ddr.h>
  29
  30 /*
  31  * Driving strength:
  32  *   0x30 == 40 Ohm
  33  *   0x28 == 48 Ohm
  34  */
  35 #define IMX6DQ_DRIVE_STRENGTH           0x30
  36 #define IMX6SDL_DRIVE_STRENGTH  0x28
  37
  38 /* configure MX6Q/DUAL mmdc DDR io registers */
  39 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  40         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  41         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  42         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  43         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  44         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  45         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  46         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  47         .dram_sdba2 = 0x00000000,
  48         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  53         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  58         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  59         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  60         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  61         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  62         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  63         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  64         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  65         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  66 };
  67
  68 /* configure MX6Q/DUAL mmdc GRP io registers */
  69 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  70         .grp_ddr_type = 0x000c0000,
  71         .grp_ddrmode_ctl = 0x00020000,
  72         .grp_ddrpke = 0x00000000,
  73         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  74         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  75         .grp_ddrmode = 0x00020000,
  76         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  77         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  78         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  79         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  80         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  81         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  82         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  83         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  84 };
  85
  86 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  87 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  88         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  89         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  90         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  91         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  92         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  93         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  94         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  95         .dram_sdba2 = 0x00000000,
  96         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  97         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  98         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  99         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 100         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 101         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 102         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 103         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 104         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 105         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 106         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 107         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 108         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 109         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 110         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 111         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 112         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 113         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 114 };
 115
 116 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 117 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 118         .grp_ddr_type = 0x000c0000,
 119         .grp_ddrmode_ctl = 0x00020000,
 120         .grp_ddrpke = 0x00000000,
 121         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 122         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 123         .grp_ddrmode = 0x00020000,
 124         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 125         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 126         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 127         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 128         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 129         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 130         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 131         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 132 };
 133
 134 /* MT41K128M16JT-125 */
 135 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 136         /* quad = 1066, duallite = 800 */
 137         .mem_speed = 1066,
 138         .density = 2,
 139         .width = 16,
 140         .banks = 8,
 141         .rowaddr = 14,
 142         .coladdr = 10,
 143         .pagesz = 2,
 144         .trcd = 1375,
 145         .trcmin = 4875,
 146         .trasmin = 3500,
 147         .SRT = 0,
 148 };
 149
 150 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
 151         .p0_mpwldectrl0 = 0x00350035,
 152         .p0_mpwldectrl1 = 0x001F001F,
 153         .p1_mpwldectrl0 = 0x00010001,
 154         .p1_mpwldectrl1 = 0x00010001,
 155         .p0_mpdgctrl0 = 0x43510360,
 156         .p0_mpdgctrl1 = 0x0342033F,
 157         .p1_mpdgctrl0 = 0x033F033F,
 158         .p1_mpdgctrl1 = 0x03290266,
 159         .p0_mprddlctl = 0x4B3E4141,
 160         .p1_mprddlctl = 0x47413B4A,
 161         .p0_mpwrdlctl = 0x42404843,
 162         .p1_mpwrdlctl = 0x4C3F4C45,
 163 };
 164
 165 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 166         .p0_mpwldectrl0 = 0x002F0038,
 167         .p0_mpwldectrl1 = 0x001F001F,
 168         .p1_mpwldectrl0 = 0x001F001F,
 169         .p1_mpwldectrl1 = 0x001F001F,
 170         .p0_mpdgctrl0 = 0x425C0251,
 171         .p0_mpdgctrl1 = 0x021B021E,
 172         .p1_mpdgctrl0 = 0x021B021E,
 173         .p1_mpdgctrl1 = 0x01730200,
 174         .p0_mprddlctl = 0x45474C45,
 175         .p1_mprddlctl = 0x44464744,
 176         .p0_mpwrdlctl = 0x3F3F3336,
 177         .p1_mpwrdlctl = 0x32383630,
 178 };
 179
 180 /* DDR 64bit 1GB */
 181 static struct mx6_ddr_sysinfo mem_qdl = {
 182         .dsize = 2,
 183         .cs1_mirror = 0,
 184         /* config for full 4GB range so that get_mem_size() works */
 185         .cs_density = 32,
 186         .ncs = 1,
 187         .bi_on = 1,
 188         /* quad = 2, duallite = 1 */
 189         .rtt_nom = 2,
 190         /* quad = 2, duallite = 1 */
 191         .rtt_wr = 2,
 192         .ralat = 5,
 193         .walat = 0,
 194         .mif3_mode = 3,
 195         .rst_to_cke = 0x23,
 196         .sde_to_rst = 0x10,
 197         .refsel = 1,    /* Refresh cycles at 32KHz */
 198         .refr = 7,      /* 8 refresh commands per refresh cycle */
 199 };
 200
 201 static void ccgr_init(void)
 202 {
 203         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 204
 205         /* set the default clock gate to save power */
 206         writel(0x00C03F3F, &ccm->CCGR0);
 207         writel(0x0030FC03, &ccm->CCGR1);
 208         writel(0x0FFFC000, &ccm->CCGR2);
 209         writel(0x3FF00000, &ccm->CCGR3);
 210         writel(0x00FFF300, &ccm->CCGR4);
 211         writel(0x0F0000C3, &ccm->CCGR5);
 212         writel(0x000003FF, &ccm->CCGR6);
 213 }
 214
 215 static void spl_dram_init(void)
 216 {
 217         if (is_cpu_type(MXC_CPU_MX6DL)) {
 218                 mt41k128m16jt_125.mem_speed = 800;
 219                 mem_qdl.rtt_nom = 1;
 220                 mem_qdl.rtt_wr = 1;
 221
 222                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 223                 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
 224         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 225                 mt41k128m16jt_125.mem_speed = 1066;
 226                 mem_qdl.rtt_nom = 2;
 227                 mem_qdl.rtt_wr = 2;
 228
 229                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 230                 mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
 231         }
 232
 233         udelay(100);
 234 }
 235
 236 void board_init_f(ulong dummy)
 237 {
 238         ccgr_init();
 239
 240         /* setup AIPS and disable watchdog */
 241         arch_cpu_init();
 242
 243         gpr_init();
 244
 245         /* iomux */
 246         board_early_init_f();
 247
 248         /* setup GP timer */
 249         timer_init();
 250
 251         /* UART clocks enabled and gd valid - init serial console */
 252         preloader_console_init();
 253
 254         /* DDR initialization */
 255         spl_dram_init();
 256 }
 257 #endif