board/udoo/neo/neo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
   4  * Copyright (C) Jasbir Matharu
   5  * Copyright (C) UDOO Team
   6  *
   7  * Author: Breno Lima <breno.lima@nxp.com>
   8  * Author: Francesco Montefoschi <francesco.monte@gmail.com>
   9  */
  10
  11 #include <init.h>
  12 #include <net.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <env.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <asm/arch/crm_regs.h>
  24 #include <asm/io.h>
  25 #include <asm/mach-imx/mxc_i2c.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <spl.h>
  28 #include <linux/delay.h>
  29 #include <linux/sizes.h>
  30 #include <common.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/pfuze3000_pmic.h>
  36 #include <malloc.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 enum {
  41         UDOO_NEO_TYPE_BASIC,
  42         UDOO_NEO_TYPE_BASIC_KS,
  43         UDOO_NEO_TYPE_FULL,
  44         UDOO_NEO_TYPE_EXTENDED,
  45 };
  46
  47 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  48         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  49         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  52         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  53         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |               \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  57         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |               \
  58         PAD_CTL_ODE)
  59
  60 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  61         PAD_CTL_SPEED_MED   |                                   \
  62         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  63
  64 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  65         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  66
  67 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  68         PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
  69
  70 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |  \
  71         PAD_CTL_DSE_40ohm)
  72
  73 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |              \
  74         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  75         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  76 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |     \
  77         MUX_MODE_SION)
  78
  79 int dram_init(void)
  80 {
  81         gd->ram_size = imx_ddr_size();
  82         return 0;
  83 }
  84
  85 #ifdef CONFIG_SYS_I2C_MXC
  86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  87 /* I2C1 for PMIC */
  88 static struct i2c_pads_info i2c_pad_info1 = {
  89         .scl = {
  90                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  91                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  92                 .gp = IMX_GPIO_NR(1, 0),
  93         },
  94         .sda = {
  95                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  96                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  97                 .gp = IMX_GPIO_NR(1, 1),
  98         },
  99 };
 100 #endif
 101
 102 #ifdef CONFIG_POWER
 103 int power_init_board(void)
 104 {
 105         struct pmic *p;
 106         int ret;
 107         unsigned int reg, rev_id;
 108
 109         ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
 110         if (ret)
 111                 return ret;
 112
 113         p = pmic_get("PFUZE3000");
 114         ret = pmic_probe(p);
 115         if (ret)
 116                 return ret;
 117
 118         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 119         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 120         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 121
 122         /* disable Low Power Mode during standby mode */
 123         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 124         reg |= 0x1;
 125         ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 126         if (ret)
 127                 return ret;
 128
 129         ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
 130         if (ret)
 131                 return ret;
 132
 133         ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
 134         if (ret)
 135                 return ret;
 136
 137         ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
 138         if (ret)
 139                 return ret;
 140
 141         ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
 142         if (ret)
 143                 return ret;
 144
 145         /* set SW1A standby voltage 0.975V */
 146         pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
 147         reg &= ~0x3f;
 148         reg |= PFUZE3000_SW1AB_SETP(9750);
 149         ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 150         if (ret)
 151                 return ret;
 152
 153         /* set SW1B standby voltage 0.975V */
 154         pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
 155         reg &= ~0x3f;
 156         reg |= PFUZE3000_SW1AB_SETP(9750);
 157         ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 158         if (ret)
 159                 return ret;
 160
 161         /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
 162         pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
 163         reg &= ~0xc0;
 164         reg |= 0x40;
 165         ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
 166         if (ret)
 167                 return ret;
 168
 169         /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
 170         pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
 171         reg &= ~0xc0;
 172         reg |= 0x40;
 173         ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
 174         if (ret)
 175                 return ret;
 176
 177         /* set VDD_ARM_IN to 1.350V */
 178         pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
 179         reg &= ~0x3f;
 180         reg |= PFUZE3000_SW1AB_SETP(13500);
 181         ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
 182         if (ret)
 183                 return ret;
 184
 185         /* set VDD_SOC_IN to 1.350V */
 186         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 187         reg &= ~0x3f;
 188         reg |= PFUZE3000_SW1AB_SETP(13500);
 189         ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 190         if (ret)
 191                 return ret;
 192
 193         /* set DDR_1_5V to 1.350V */
 194         pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
 195         reg &= ~0x0f;
 196         reg |= PFUZE3000_SW3_SETP(13500);
 197         ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
 198         if (ret)
 199                 return ret;
 200
 201         /* set VGEN2_1V5 to 1.5V */
 202         pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
 203         reg &= ~0x0f;
 204         reg |= PFUZE3000_VLDO_SETP(15000);
 205         /*  enable  */
 206         reg |= 0x10;
 207         ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
 208         if (ret)
 209                 return ret;
 210
 211         return 0;
 212 }
 213 #endif
 214
 215 static iomux_v3_cfg_t const uart1_pads[] = {
 216         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 217         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 218 };
 219
 220 static iomux_v3_cfg_t const usdhc2_pads[] = {
 221         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 222         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 223         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 224         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 225         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 226         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 227         /* CD pin */
 228         MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
 229         /* Power */
 230         MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 231 };
 232
 233 static iomux_v3_cfg_t const fec1_pads[] = {
 234         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 236         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 237         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 238         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 239         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 240         MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 241         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 242         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 243         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 244         MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 245         MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 246 };
 247
 248 static iomux_v3_cfg_t const phy_control_pads[] = {
 249         /* 25MHz Ethernet PHY Clock */
 250         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
 251         MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 252 };
 253
 254 static iomux_v3_cfg_t const board_recognition_pads[] = {
 255         /*Connected to R184*/
 256         MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
 257         /*Connected to R185*/
 258         MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
 259 };
 260
 261 static iomux_v3_cfg_t const wdog_b_pad = {
 262         MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 263 };
 264
 265 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 266         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 267 };
 268
 269 static void setup_iomux_uart(void)
 270 {
 271         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 272 }
 273
 274 static int setup_fec(int fec_id)
 275 {
 276         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 277         int reg;
 278
 279         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 280                                          ARRAY_SIZE(phy_control_pads));
 281
 282         /* Reset PHY */
 283         gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
 284         udelay(10000);
 285         gpio_set_value(IMX_GPIO_NR(2, 1), 1);
 286         udelay(100);
 287
 288         reg = readl(&anatop->pll_enet);
 289         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 290         writel(reg, &anatop->pll_enet);
 291
 292         return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
 293 }
 294
 295 int board_eth_init(bd_t *bis)
 296 {
 297         uint32_t base = IMX_FEC_BASE;
 298         struct mii_dev *bus = NULL;
 299         struct phy_device *phydev = NULL;
 300         int ret;
 301
 302         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 303
 304         setup_fec(CONFIG_FEC_ENET_DEV);
 305
 306         bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
 307         if (!bus)
 308                 return -EINVAL;
 309
 310         phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
 311                                         PHY_INTERFACE_MODE_RMII);
 312         if (!phydev) {
 313                 free(bus);
 314                 return -EINVAL;
 315         }
 316
 317         ret  = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
 318         if (ret) {
 319                 free(bus);
 320                 free(phydev);
 321                 return ret;
 322         }
 323         return 0;
 324 }
 325
 326 int board_phy_config(struct phy_device *phydev)
 327 {
 328         if (phydev->drv->config)
 329                 phydev->drv->config(phydev);
 330
 331         return 0;
 332 }
 333
 334 int board_init(void)
 335 {
 336         /* Address of boot parameters */
 337         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 338
 339         /*
 340          * Because kernel set WDOG_B mux before pad with the commone pinctrl
 341          * framwork now and wdog reset will be triggered once set WDOG_B mux
 342          * with default pad setting, we set pad setting here to workaround this.
 343          * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
 344          * as GPIO mux firstly here to workaround it.
 345          */
 346         imx_iomux_v3_setup_pad(wdog_b_pad);
 347
 348         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 349         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 350                                          ARRAY_SIZE(peri_3v3_pads));
 351
 352         /* Active high for ncp692 */
 353         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 354
 355 #ifdef CONFIG_SYS_I2C_MXC
 356         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 357 #endif
 358
 359         return 0;
 360 }
 361
 362 static int get_board_value(void)
 363 {
 364         int r184, r185;
 365
 366         imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
 367                                          ARRAY_SIZE(board_recognition_pads));
 368
 369         gpio_direction_input(IMX_GPIO_NR(4, 13));
 370         gpio_direction_input(IMX_GPIO_NR(4, 0));
 371
 372         r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
 373         r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
 374
 375         /*
 376          * Machine selection -
 377          * Machine          r184,    r185
 378          * ---------------------------------
 379          * Basic              0        0
 380          * Basic Ks           0        1
 381          * Full               1        0
 382          * Extended           1        1
 383          */
 384
 385         return (r184 << 1) + r185;
 386 }
 387
 388 int board_early_init_f(void)
 389 {
 390         setup_iomux_uart();
 391
 392         return 0;
 393 }
 394
 395 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 396         {USDHC2_BASE_ADDR, 0, 4},
 397 };
 398
 399 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
 400 #define USDHC2_CD_GPIO  IMX_GPIO_NR(6, 2)
 401
 402 int board_mmc_getcd(struct mmc *mmc)
 403 {
 404         return !gpio_get_value(USDHC2_CD_GPIO);
 405 }
 406
 407 int board_mmc_init(bd_t *bis)
 408 {
 409         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 410         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 411         usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 412         gpio_direction_input(USDHC2_CD_GPIO);
 413         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 414
 415         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 416         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 417 }
 418
 419 static char *board_string(void)
 420 {
 421         switch (get_board_value()) {
 422         case UDOO_NEO_TYPE_BASIC:
 423                 return "BASIC";
 424         case UDOO_NEO_TYPE_BASIC_KS:
 425                 return "BASICKS";
 426         case UDOO_NEO_TYPE_FULL:
 427                 return "FULL";
 428         case UDOO_NEO_TYPE_EXTENDED:
 429                 return "EXTENDED";
 430         }
 431         return "UNDEFINED";
 432 }
 433
 434 int checkboard(void)
 435 {
 436         printf("Board: UDOO Neo %s\n", board_string());
 437         return 0;
 438 }
 439
 440 int board_late_init(void)
 441 {
 442 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 443         env_set("board_name", board_string());
 444 #endif
 445
 446         return 0;
 447 }
 448
 449 #ifdef CONFIG_SPL_BUILD
 450
 451 #include <linux/libfdt.h>
 452 #include <asm/arch/mx6-ddr.h>
 453
 454 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 455         .dram_dqm0 = 0x00000028,
 456         .dram_dqm1 = 0x00000028,
 457         .dram_dqm2 = 0x00000028,
 458         .dram_dqm3 = 0x00000028,
 459         .dram_ras = 0x00000020,
 460         .dram_cas = 0x00000020,
 461         .dram_odt0 = 0x00000020,
 462         .dram_odt1 = 0x00000020,
 463         .dram_sdba2 = 0x00000000,
 464         .dram_sdcke0 = 0x00003000,
 465         .dram_sdcke1 = 0x00003000,
 466         .dram_sdclk_0 = 0x00000030,
 467         .dram_sdqs0 = 0x00000028,
 468         .dram_sdqs1 = 0x00000028,
 469         .dram_sdqs2 = 0x00000028,
 470         .dram_sdqs3 = 0x00000028,
 471         .dram_reset = 0x00000020,
 472 };
 473
 474 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 475         .grp_addds = 0x00000020,
 476         .grp_ddrmode_ctl = 0x00020000,
 477         .grp_ddrpke = 0x00000000,
 478         .grp_ddrmode = 0x00020000,
 479         .grp_b0ds = 0x00000028,
 480         .grp_b1ds = 0x00000028,
 481         .grp_ctlds = 0x00000020,
 482         .grp_ddr_type = 0x000c0000,
 483         .grp_b2ds = 0x00000028,
 484         .grp_b3ds = 0x00000028,
 485 };
 486
 487 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
 488         .p0_mpwldectrl0 = 0x000E000B,
 489         .p0_mpwldectrl1 = 0x000E0010,
 490         .p0_mpdgctrl0 = 0x41600158,
 491         .p0_mpdgctrl1 = 0x01500140,
 492         .p0_mprddlctl = 0x3A383E3E,
 493         .p0_mpwrdlctl = 0x3A383C38,
 494 };
 495
 496 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
 497         .p0_mpwldectrl0 = 0x001E0022,
 498         .p0_mpwldectrl1 = 0x001C0019,
 499         .p0_mpdgctrl0 = 0x41540150,
 500         .p0_mpdgctrl1 = 0x01440138,
 501         .p0_mprddlctl = 0x403E4644,
 502         .p0_mpwrdlctl = 0x3C3A4038,
 503 };
 504
 505 /* MT41K256M16 */
 506 static struct mx6_ddr3_cfg neo_mem_ddr = {
 507         .mem_speed = 1600,
 508         .density = 4,
 509         .width = 16,
 510         .banks = 8,
 511         .rowaddr = 15,
 512         .coladdr = 10,
 513         .pagesz = 2,
 514         .trcd = 1375,
 515         .trcmin = 4875,
 516         .trasmin = 3500,
 517 };
 518
 519 /* MT41K128M16 */
 520 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
 521         .mem_speed = 1600,
 522         .density = 2,
 523         .width = 16,
 524         .banks = 8,
 525         .rowaddr = 14,
 526         .coladdr = 10,
 527         .pagesz = 2,
 528         .trcd = 1375,
 529         .trcmin = 4875,
 530         .trasmin = 3500,
 531 };
 532
 533 static void ccgr_init(void)
 534 {
 535         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 536
 537         writel(0xFFFFFFFF, &ccm->CCGR0);
 538         writel(0xFFFFFFFF, &ccm->CCGR1);
 539         writel(0xFFFFFFFF, &ccm->CCGR2);
 540         writel(0xFFFFFFFF, &ccm->CCGR3);
 541         writel(0xFFFFFFFF, &ccm->CCGR4);
 542         writel(0xFFFFFFFF, &ccm->CCGR5);
 543         writel(0xFFFFFFFF, &ccm->CCGR6);
 544         writel(0xFFFFFFFF, &ccm->CCGR7);
 545 }
 546
 547 static void spl_dram_init(void)
 548 {
 549         int board = get_board_value();
 550
 551         struct mx6_ddr_sysinfo sysinfo = {
 552                 .dsize = 1, /* width of data bus: 1 = 32 bits */
 553                 .cs_density = 24,
 554                 .ncs = 1,
 555                 .cs1_mirror = 0,
 556                 .rtt_wr = 2,
 557                 .rtt_nom = 2,           /* RTT_Nom = RZQ/2 */
 558                 .walat = 1,             /* Write additional latency */
 559                 .ralat = 5,             /* Read additional latency */
 560                 .mif3_mode = 3,         /* Command prediction working mode */
 561                 .bi_on = 1,             /* Bank interleaving enabled */
 562                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 563                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 564         };
 565
 566         mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 567         if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
 568                 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
 569                              &neo_basic_mem_ddr);
 570         else
 571                 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
 572 }
 573
 574 void board_init_f(ulong dummy)
 575 {
 576         ccgr_init();
 577
 578         /* setup AIPS and disable watchdog */
 579         arch_cpu_init();
 580
 581         board_early_init_f();
 582
 583         /* setup GP timer */
 584         timer_init();
 585
 586         /* UART clocks enabled and gd valid - init serial console */
 587         preloader_console_init();
 588
 589         /* DDR initialization */
 590         spl_dram_init();
 591
 592         /* Clear the BSS. */
 593         memset(__bss_start, 0, __bss_end - __bss_start);
 594
 595         /* load/boot image from boot device */
 596         board_init_r(NULL, 0);
 597 }
 598
 599 #endif