board/udoo/neo/neo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
   4  * Copyright (C) Jasbir Matharu
   5  * Copyright (C) UDOO Team
   6  *
   7  * Author: Breno Lima <breno.lima@nxp.com>
   8  * Author: Francesco Montefoschi <francesco.monte@gmail.com>
   9  */
  10
  11 #include <init.h>
  12 #include <net.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <env.h>
  21 #include <mmc.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <asm/arch/crm_regs.h>
  24 #include <asm/io.h>
  25 #include <asm/mach-imx/mxc_i2c.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <spl.h>
  28 #include <linux/sizes.h>
  29 #include <common.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <netdev.h>
  33 #include <power/pmic.h>
  34 #include <power/pfuze3000_pmic.h>
  35 #include <malloc.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         UDOO_NEO_TYPE_BASIC,
  41         UDOO_NEO_TYPE_BASIC_KS,
  42         UDOO_NEO_TYPE_FULL,
  43         UDOO_NEO_TYPE_EXTENDED,
  44 };
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  47         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  48         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  51         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  52         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |               \
  55         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  56         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |               \
  57         PAD_CTL_ODE)
  58
  59 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  60         PAD_CTL_SPEED_MED   |                                   \
  61         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  62
  63 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  64         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  65
  66 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  67         PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
  68
  69 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |  \
  70         PAD_CTL_DSE_40ohm)
  71
  72 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |              \
  73         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  74         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  75 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |     \
  76         MUX_MODE_SION)
  77
  78 int dram_init(void)
  79 {
  80         gd->ram_size = imx_ddr_size();
  81         return 0;
  82 }
  83
  84 #ifdef CONFIG_SYS_I2C_MXC
  85 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  86 /* I2C1 for PMIC */
  87 static struct i2c_pads_info i2c_pad_info1 = {
  88         .scl = {
  89                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  90                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  91                 .gp = IMX_GPIO_NR(1, 0),
  92         },
  93         .sda = {
  94                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  95                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  96                 .gp = IMX_GPIO_NR(1, 1),
  97         },
  98 };
  99 #endif
 100
 101 #ifdef CONFIG_POWER
 102 int power_init_board(void)
 103 {
 104         struct pmic *p;
 105         int ret;
 106         unsigned int reg, rev_id;
 107
 108         ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
 109         if (ret)
 110                 return ret;
 111
 112         p = pmic_get("PFUZE3000");
 113         ret = pmic_probe(p);
 114         if (ret)
 115                 return ret;
 116
 117         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
 118         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
 119         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 120
 121         /* disable Low Power Mode during standby mode */
 122         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
 123         reg |= 0x1;
 124         ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 125         if (ret)
 126                 return ret;
 127
 128         ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
 129         if (ret)
 130                 return ret;
 131
 132         ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
 133         if (ret)
 134                 return ret;
 135
 136         ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
 137         if (ret)
 138                 return ret;
 139
 140         ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
 141         if (ret)
 142                 return ret;
 143
 144         /* set SW1A standby voltage 0.975V */
 145         pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
 146         reg &= ~0x3f;
 147         reg |= PFUZE3000_SW1AB_SETP(9750);
 148         ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 149         if (ret)
 150                 return ret;
 151
 152         /* set SW1B standby voltage 0.975V */
 153         pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
 154         reg &= ~0x3f;
 155         reg |= PFUZE3000_SW1AB_SETP(9750);
 156         ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 157         if (ret)
 158                 return ret;
 159
 160         /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
 161         pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
 162         reg &= ~0xc0;
 163         reg |= 0x40;
 164         ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
 165         if (ret)
 166                 return ret;
 167
 168         /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
 169         pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
 170         reg &= ~0xc0;
 171         reg |= 0x40;
 172         ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
 173         if (ret)
 174                 return ret;
 175
 176         /* set VDD_ARM_IN to 1.350V */
 177         pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
 178         reg &= ~0x3f;
 179         reg |= PFUZE3000_SW1AB_SETP(13500);
 180         ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
 181         if (ret)
 182                 return ret;
 183
 184         /* set VDD_SOC_IN to 1.350V */
 185         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 186         reg &= ~0x3f;
 187         reg |= PFUZE3000_SW1AB_SETP(13500);
 188         ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 189         if (ret)
 190                 return ret;
 191
 192         /* set DDR_1_5V to 1.350V */
 193         pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
 194         reg &= ~0x0f;
 195         reg |= PFUZE3000_SW3_SETP(13500);
 196         ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
 197         if (ret)
 198                 return ret;
 199
 200         /* set VGEN2_1V5 to 1.5V */
 201         pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
 202         reg &= ~0x0f;
 203         reg |= PFUZE3000_VLDO_SETP(15000);
 204         /*  enable  */
 205         reg |= 0x10;
 206         ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
 207         if (ret)
 208                 return ret;
 209
 210         return 0;
 211 }
 212 #endif
 213
 214 static iomux_v3_cfg_t const uart1_pads[] = {
 215         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 216         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 217 };
 218
 219 static iomux_v3_cfg_t const usdhc2_pads[] = {
 220         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 221         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 222         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 223         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 224         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 225         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 226         /* CD pin */
 227         MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
 228         /* Power */
 229         MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 230 };
 231
 232 static iomux_v3_cfg_t const fec1_pads[] = {
 233         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 236         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 237         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 238         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 239         MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 240         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 241         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 242         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 243         MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 244         MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 245 };
 246
 247 static iomux_v3_cfg_t const phy_control_pads[] = {
 248         /* 25MHz Ethernet PHY Clock */
 249         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
 250         MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 251 };
 252
 253 static iomux_v3_cfg_t const board_recognition_pads[] = {
 254         /*Connected to R184*/
 255         MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
 256         /*Connected to R185*/
 257         MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
 258 };
 259
 260 static iomux_v3_cfg_t const wdog_b_pad = {
 261         MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 262 };
 263
 264 static iomux_v3_cfg_t const peri_3v3_pads[] = {
 265         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 266 };
 267
 268 static void setup_iomux_uart(void)
 269 {
 270         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 271 }
 272
 273 static int setup_fec(int fec_id)
 274 {
 275         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 276         int reg;
 277
 278         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 279                                          ARRAY_SIZE(phy_control_pads));
 280
 281         /* Reset PHY */
 282         gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
 283         udelay(10000);
 284         gpio_set_value(IMX_GPIO_NR(2, 1), 1);
 285         udelay(100);
 286
 287         reg = readl(&anatop->pll_enet);
 288         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 289         writel(reg, &anatop->pll_enet);
 290
 291         return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
 292 }
 293
 294 int board_eth_init(bd_t *bis)
 295 {
 296         uint32_t base = IMX_FEC_BASE;
 297         struct mii_dev *bus = NULL;
 298         struct phy_device *phydev = NULL;
 299         int ret;
 300
 301         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 302
 303         setup_fec(CONFIG_FEC_ENET_DEV);
 304
 305         bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
 306         if (!bus)
 307                 return -EINVAL;
 308
 309         phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
 310                                         PHY_INTERFACE_MODE_RMII);
 311         if (!phydev) {
 312                 free(bus);
 313                 return -EINVAL;
 314         }
 315
 316         ret  = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
 317         if (ret) {
 318                 free(bus);
 319                 free(phydev);
 320                 return ret;
 321         }
 322         return 0;
 323 }
 324
 325 int board_phy_config(struct phy_device *phydev)
 326 {
 327         if (phydev->drv->config)
 328                 phydev->drv->config(phydev);
 329
 330         return 0;
 331 }
 332
 333 int board_init(void)
 334 {
 335         /* Address of boot parameters */
 336         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 337
 338         /*
 339          * Because kernel set WDOG_B mux before pad with the commone pinctrl
 340          * framwork now and wdog reset will be triggered once set WDOG_B mux
 341          * with default pad setting, we set pad setting here to workaround this.
 342          * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
 343          * as GPIO mux firstly here to workaround it.
 344          */
 345         imx_iomux_v3_setup_pad(wdog_b_pad);
 346
 347         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 348         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 349                                          ARRAY_SIZE(peri_3v3_pads));
 350
 351         /* Active high for ncp692 */
 352         gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 353
 354 #ifdef CONFIG_SYS_I2C_MXC
 355         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 356 #endif
 357
 358         return 0;
 359 }
 360
 361 static int get_board_value(void)
 362 {
 363         int r184, r185;
 364
 365         imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
 366                                          ARRAY_SIZE(board_recognition_pads));
 367
 368         gpio_direction_input(IMX_GPIO_NR(4, 13));
 369         gpio_direction_input(IMX_GPIO_NR(4, 0));
 370
 371         r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
 372         r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
 373
 374         /*
 375          * Machine selection -
 376          * Machine          r184,    r185
 377          * ---------------------------------
 378          * Basic              0        0
 379          * Basic Ks           0        1
 380          * Full               1        0
 381          * Extended           1        1
 382          */
 383
 384         return (r184 << 1) + r185;
 385 }
 386
 387 int board_early_init_f(void)
 388 {
 389         setup_iomux_uart();
 390
 391         return 0;
 392 }
 393
 394 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 395         {USDHC2_BASE_ADDR, 0, 4},
 396 };
 397
 398 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
 399 #define USDHC2_CD_GPIO  IMX_GPIO_NR(6, 2)
 400
 401 int board_mmc_getcd(struct mmc *mmc)
 402 {
 403         return !gpio_get_value(USDHC2_CD_GPIO);
 404 }
 405
 406 int board_mmc_init(bd_t *bis)
 407 {
 408         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 409         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 410         usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 411         gpio_direction_input(USDHC2_CD_GPIO);
 412         gpio_direction_output(USDHC2_PWR_GPIO, 1);
 413
 414         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 415         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 416 }
 417
 418 static char *board_string(void)
 419 {
 420         switch (get_board_value()) {
 421         case UDOO_NEO_TYPE_BASIC:
 422                 return "BASIC";
 423         case UDOO_NEO_TYPE_BASIC_KS:
 424                 return "BASICKS";
 425         case UDOO_NEO_TYPE_FULL:
 426                 return "FULL";
 427         case UDOO_NEO_TYPE_EXTENDED:
 428                 return "EXTENDED";
 429         }
 430         return "UNDEFINED";
 431 }
 432
 433 int checkboard(void)
 434 {
 435         printf("Board: UDOO Neo %s\n", board_string());
 436         return 0;
 437 }
 438
 439 int board_late_init(void)
 440 {
 441 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 442         env_set("board_name", board_string());
 443 #endif
 444
 445         return 0;
 446 }
 447
 448 #ifdef CONFIG_SPL_BUILD
 449
 450 #include <linux/libfdt.h>
 451 #include <asm/arch/mx6-ddr.h>
 452
 453 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 454         .dram_dqm0 = 0x00000028,
 455         .dram_dqm1 = 0x00000028,
 456         .dram_dqm2 = 0x00000028,
 457         .dram_dqm3 = 0x00000028,
 458         .dram_ras = 0x00000020,
 459         .dram_cas = 0x00000020,
 460         .dram_odt0 = 0x00000020,
 461         .dram_odt1 = 0x00000020,
 462         .dram_sdba2 = 0x00000000,
 463         .dram_sdcke0 = 0x00003000,
 464         .dram_sdcke1 = 0x00003000,
 465         .dram_sdclk_0 = 0x00000030,
 466         .dram_sdqs0 = 0x00000028,
 467         .dram_sdqs1 = 0x00000028,
 468         .dram_sdqs2 = 0x00000028,
 469         .dram_sdqs3 = 0x00000028,
 470         .dram_reset = 0x00000020,
 471 };
 472
 473 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 474         .grp_addds = 0x00000020,
 475         .grp_ddrmode_ctl = 0x00020000,
 476         .grp_ddrpke = 0x00000000,
 477         .grp_ddrmode = 0x00020000,
 478         .grp_b0ds = 0x00000028,
 479         .grp_b1ds = 0x00000028,
 480         .grp_ctlds = 0x00000020,
 481         .grp_ddr_type = 0x000c0000,
 482         .grp_b2ds = 0x00000028,
 483         .grp_b3ds = 0x00000028,
 484 };
 485
 486 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
 487         .p0_mpwldectrl0 = 0x000E000B,
 488         .p0_mpwldectrl1 = 0x000E0010,
 489         .p0_mpdgctrl0 = 0x41600158,
 490         .p0_mpdgctrl1 = 0x01500140,
 491         .p0_mprddlctl = 0x3A383E3E,
 492         .p0_mpwrdlctl = 0x3A383C38,
 493 };
 494
 495 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
 496         .p0_mpwldectrl0 = 0x001E0022,
 497         .p0_mpwldectrl1 = 0x001C0019,
 498         .p0_mpdgctrl0 = 0x41540150,
 499         .p0_mpdgctrl1 = 0x01440138,
 500         .p0_mprddlctl = 0x403E4644,
 501         .p0_mpwrdlctl = 0x3C3A4038,
 502 };
 503
 504 /* MT41K256M16 */
 505 static struct mx6_ddr3_cfg neo_mem_ddr = {
 506         .mem_speed = 1600,
 507         .density = 4,
 508         .width = 16,
 509         .banks = 8,
 510         .rowaddr = 15,
 511         .coladdr = 10,
 512         .pagesz = 2,
 513         .trcd = 1375,
 514         .trcmin = 4875,
 515         .trasmin = 3500,
 516 };
 517
 518 /* MT41K128M16 */
 519 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
 520         .mem_speed = 1600,
 521         .density = 2,
 522         .width = 16,
 523         .banks = 8,
 524         .rowaddr = 14,
 525         .coladdr = 10,
 526         .pagesz = 2,
 527         .trcd = 1375,
 528         .trcmin = 4875,
 529         .trasmin = 3500,
 530 };
 531
 532 static void ccgr_init(void)
 533 {
 534         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 535
 536         writel(0xFFFFFFFF, &ccm->CCGR0);
 537         writel(0xFFFFFFFF, &ccm->CCGR1);
 538         writel(0xFFFFFFFF, &ccm->CCGR2);
 539         writel(0xFFFFFFFF, &ccm->CCGR3);
 540         writel(0xFFFFFFFF, &ccm->CCGR4);
 541         writel(0xFFFFFFFF, &ccm->CCGR5);
 542         writel(0xFFFFFFFF, &ccm->CCGR6);
 543         writel(0xFFFFFFFF, &ccm->CCGR7);
 544 }
 545
 546 static void spl_dram_init(void)
 547 {
 548         int board = get_board_value();
 549
 550         struct mx6_ddr_sysinfo sysinfo = {
 551                 .dsize = 1, /* width of data bus: 1 = 32 bits */
 552                 .cs_density = 24,
 553                 .ncs = 1,
 554                 .cs1_mirror = 0,
 555                 .rtt_wr = 2,
 556                 .rtt_nom = 2,           /* RTT_Nom = RZQ/2 */
 557                 .walat = 1,             /* Write additional latency */
 558                 .ralat = 5,             /* Read additional latency */
 559                 .mif3_mode = 3,         /* Command prediction working mode */
 560                 .bi_on = 1,             /* Bank interleaving enabled */
 561                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 562                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 563         };
 564
 565         mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 566         if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
 567                 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
 568                              &neo_basic_mem_ddr);
 569         else
 570                 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
 571 }
 572
 573 void board_init_f(ulong dummy)
 574 {
 575         ccgr_init();
 576
 577         /* setup AIPS and disable watchdog */
 578         arch_cpu_init();
 579
 580         board_early_init_f();
 581
 582         /* setup GP timer */
 583         timer_init();
 584
 585         /* UART clocks enabled and gd valid - init serial console */
 586         preloader_console_init();
 587
 588         /* DDR initialization */
 589         spl_dram_init();
 590
 591         /* Clear the BSS. */
 592         memset(__bss_start, 0, __bss_end - __bss_start);
 593
 594         /* load/boot image from boot device */
 595         board_init_r(NULL, 0);
 596 }
 597
 598 #endif